CN103441068A - Method for forming double patterning based on DARC mask structure - Google Patents
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Abstract
The invention relates to the technical field of microelectronics, in particular to a method for forming double patterning based on a DARC mask structure. Advanced patterning films are respectively adopted in two times of etching processes of a double patterning forming process to be used as the masks of the etching processes, patterns in a light resistor are transferred to grid polycrystalline silicon, and therefore the difference between the key sizes of the two times of etching processes is greatly improved to improve the uniformity of the key sizes, meanwhile, an APF replaces a traditional monox hard mask, a base layer structure ODL based on spin coating and a middle later structure SHB, process cost is saved, meanwhile, the technological processes with APFs as masks adopted by mature technological nodes of 40nm and more than 40nm are made to last to the technological nodes of 28/20nm and lower than 28/20nm, and therefore the maturity and the stability of the grid manufacturing processes of the technological nodes of 28/20nm and lower than 28/20nm are improved.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of double-pattern forming method based on the DARC mask structure.
Background technology
At present, on 32nm and following technology node thereof, be applied to the photoetching process of key level, because its required resolution index has surpassed the limit capacity of existing optical lithography platform, industry has adopted the multiple technologies scheme to solve this technical problem, and, according to shown in the ITRS route map, Dual graphing technology (Double Patterning Technology is called for short DPT), extreme ultraviolet line technology (EUV), electronics art are directly write technical schemes such as (EBL) and all by industry, have been expressed great expectations.
Wherein, Dual graphing technology (DPT) is that a set of highdensity circuitous pattern is decomposed and is split as two covers or overlaps the circuit diagram that closeness is lower more, then make respectively reticle, and successively complete corresponding exposure and etching technics, the final high density graph that forms initial demand that merges.
Along with the mask aligner software and hardware technology is constantly progressive, Dual graphing technology based on immersed photoetching machine, limiting resolution and the technical life of 193nm immersion optical lithography platform further can be extended, thereby can fill up between immersed photoetching machine and EUV or even the blank of the photoetching technique of less technology node.
According to the technical investigation result, micro-shadow-etching-micro-shadow-etching (Litho-Etch-Litho-Etch, abbreviation LELE) technology is one of current several Dual graphing mainstream technology schemes, become targeted graphical by minute other photoetching of twice with the etching row, and this targeted graphical comprises two kinds of linear (line) and grooves (trench).
Fig. 1 a is the structural representation that in the double-pattern metallization processes during traditional gate line tail cuts, photoetching process forms for the first time, Fig. 1 b is the structural representation that in the double-pattern metallization processes during traditional gate line tail cuts, photoetching process forms for the second time, and Fig. 1 c carries out the structural representation that gate line tail cutting technique forms in the double-pattern metallization processes during traditional gate line tail cuts, as shown in Fig. 1 a-1c, as on 193nm immersion board (as NXT-1950i etc.), there is 38nm half pitch (Half Pitch, abbreviation HP) resolution, in order to meet 28/20nm(28nm line tail cutting and 22nm photoetching) design requirement of technology node active layer and grid layer, first carry out the first photoetching process formation structure as shown in Figure 1a, carry out again photoetching process for the second time and form structure as shown in Figure 1 b, and then the structure (Exposure2) shown in the structure (Exposure1) shown in Fig. 1 a and Fig. 1 b is formed to the structure (Final contour) as shown in Fig. 1 c by gate line tail cutting technique, i.e. first formation repeats, the line of single direction/isolation (Line/Space) figure, then carry out gate line tail cutting (Line-End-Cut) technique.
Traditional, in carrying out gate line tail cutting technique, be mainly by through chemical etching for the first time to polysilicon layer, the fabric ODL(Organic Under Layer of utilization based on spin coating (spin-on)) fill the bottom figure, and continuation employing interlayer structure SHB(SiO-based Hard Mask) be used as etched hard mask for the second time, finally prepare BARC(Bottom Anti-Reflective Coating) and PR(Photo Resist) structure before the secondary photoetching completed, adopt silica as hard mask, carry out the etch process of polysilicon layer.
Wherein, when carrying out above-mentioned etching technics for the first time, general advanced figure film (the advanced patterning film that adopts, be called for short APF) as softmask (soft-mask), while carrying out for the second time etching technics, be to adopt ODL and SHB as softmask, the critical size of the structure formed after twice etching technique before and after making is divided into two different levels, make the control difficulty to key size evenness (CDU) strengthen, if defect appears in key size evenness, very easily cause the reduction of properties of product and yield.
In addition, ODL and SHB are new materials, and its process costs is higher, and in the technique of 40 nanometers and above technology node thereof and be of little use; So these above-mentioned new materials of introduction require a great deal of time and go assessment and application with energy in the technique of 28 nanometers and following technology node thereof.
Chinese patent (CN102479700A) has been put down in writing a kind of method of Dual graphing, the method for formation interconnection structure, and described Double-patterning method comprises: substrate is provided; Form anti-reflecting layer in substrate; But form the first patterned media layer on anti-reflecting layer; But graphical the first patterned media layer, form the first structure; But form the second patterned media layer, cover the first structure and anti-reflecting layer, but and the thickness of the second patterned media layer be greater than the height of described the first structure; But remove part the second patterned media layer, but make the height of the thickness of the second patterned media layer and the first structure close, both difference scopes are less than 200 dusts; But graphically removed the second patterned media layer of part, formed the second structure; The described anti-reflecting layer of etching, expose described substrate, and the figure of described the first structure and the formation of the second structure is transferred to described anti-reflecting layer.The first structure of the present invention is identical with the height of the second structure, and in follow-up flatening process, flatening process is easy to control.
Chinese patent (CN102446704A) has been put down in writing a kind of Double-patterning method, comprising: substrate is provided, is formed with successively the first mask layer and the second mask layer on described substrate; Described the first mask layer of anisotropic etching and the second mask layer form the first opening in described the first mask layer and the second mask layer, and described the first opening exposes substrate surface; Described the second mask layer of side direction partial etching, form the second mask pattern, and described the second mask pattern exposes the first mask layer that is positioned at the second mask pattern both sides; Take the second mask pattern as mask, and etched portions the first mask layer thickness is until retain the first mask layer of the first thickness; Remove the second mask pattern; Form the 3rd mask layer at substrate surface, described the 3rd mask layer is partially filled opening; Described the 3rd mask layer of take is mask, and etching the first mask layer is until expose substrate.Double-patterning method of the present invention has been avoided the inhomogeneous problem of substrate etching, has effectively improved etching effect.
Summary of the invention
For above-mentioned technical problem, a kind of double-pattern forming method based on the DARC mask structure of the application, be applied in gate line tail cutting technique, by all adopting advanced figure film (Advanced Patterning Film in the twice etching technique at the double-pattern moulding process, be called for short APF) as the mask of etching technics, with the figure by photoresistance, be transferred on grid polycrystalline silicon, and then greatly improve the difference of critical size between twice etching technique, to improve key size evenness (CDU).
The present invention has put down in writing a kind of double-pattern forming method (A Method of double patterning technology based on single DARC mask layer for line-end-cut of poly gate) based on the DARC mask structure, wherein, comprise the following steps:
Have on the Semiconductor substrate of grid layer structure and deposit successively advanced figure rete and medium anti-reflecting layer in one;
Adopt the described medium anti-reflecting layer of etching technics etched portions, form the hard mask structure, and the upper surface of described advanced figure rete is all covered by remaining medium anti-reflecting layer;
The described hard mask structure of take is mask, and the described remaining medium anti-reflecting layer of etching and described advanced figure rete, to the surface of described grid layer structure, form advanced figure film mask;
Take described advanced figure film mask as the described grid layer structure of mask etching to the surface of described Semiconductor substrate, form grid structure.
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that described grid structure comprises grid oxide layer, polysilicon layer and silicon nitride layer;
Described grid oxide layer covers the surface of described Semiconductor substrate, and described polysilicon layer covers the surface of described grid oxide layer, and described silicon nitride layer covers the surface of described polysilicon layer, and described advanced figure rete covers the surface of described silicon nitride layer.
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that the thickness of described polysilicon layer is
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that the thickness of described silicon nitride layer is
The above-mentioned double-pattern forming method based on the DARC mask structure, it is characterized in that, while carrying out the described medium anti-reflecting layer of above-mentioned etched portions technique, etching stopping is in the inside of this medium anti-reflecting layer, and the distance between etching stopping position and described advanced figure rete upper surface is
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that the thickness of medium anti-reflecting layer is
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that the thickness of described advanced figure rete is
The above-mentioned double-pattern forming method based on the DARC mask structure, it is characterized in that, described etching technics comprises the first photoetching process, the first etching technics, the second photoetching process and the second etching technics successively, and described hard mask structure comprises the first hard mask structure and the second hard mask structure;
After preparing the first bottom anti-reflection layer in the surface of described medium anti-reflecting layer, adopt described the first photoetching process to form the first photoresistance on described the first bottom anti-reflection layer, and to take this first photoresistance be mask, adopt described the first bottom anti-reflection layer of the described etching of etching technics for the first time, and stop at the inside of described medium anti-reflecting layer, after removing described the first photoresistance and remaining the first bottom anti-reflection layer, form described the first hard mask structure in remaining medium anti-reflecting layer;
Prepare the second bottom anti-reflection layer and cover described remaining described medium anti-reflecting layer, adopt described the second photoetching process to prepare the second photoresistance in the surface of described the second bottom anti-reflection layer, and to take this second photoresistance be mask, adopt the second etching technics partly to remove described remaining medium anti-reflecting layer, after removing described the second photoresistance and remaining the second bottom anti-reflection layer, form described the second hard mask structure in remaining medium anti-reflecting layer after etching again.
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that the thickness of described the first bottom anti-reflection layer and described the second bottom anti-reflection layer is
The above-mentioned double-pattern forming method based on the DARC mask structure is characterized in that the thickness of described the first photoresistance and described the second photoresistance is
In sum, owing to having adopted technique scheme, a kind of double-pattern forming method based on the DARC mask structure of the present invention, by all adopting advanced figure film (Advanced Patterning Film in the twice etching technique at the double-pattern moulding process, be called for short APF) as the mask of etching technics, with the figure by photoresistance, be transferred on grid polycrystalline silicon, and then greatly improve the difference of critical size between twice etching technique, to improve key size evenness (CDU), this APF has also replaced traditional silica hard mask simultaneously, fabric ODL based on spin coating (spin-on) and interlayer structure SHB, when saving process costs, the APF that makes comparatively ripe 40nm and above technology node thereof adopt is extended on 28/20nm and following technology node thereof as the technological process of mask, and then maturity and the stability of 28/20nm and following technology node gate fabrication process thereof have been improved.
The accompanying drawing explanation
Fig. 1 a is the structural representation that in traditional double-pattern metallization processes, photoetching process forms for the first time;
Fig. 1 b is the structural representation that in traditional double-pattern metallization processes, photoetching process forms for the second time;
Fig. 1 c carries out the structural representation that gate line tail cutting technique forms in traditional double-pattern metallization processes;
Fig. 2-9th, the present invention is based on the flowage structure schematic diagram of an embodiment in the double-pattern forming method of DARC mask structure.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 2-9th, the present invention is based on the flowage structure schematic diagram of an embodiment in the double-pattern forming method of DARC mask structure; As shown in Fig. 2-9, a kind of double-pattern forming method based on the DARC mask structure, preferably be applied to 28/20 nanometer of carrying out on 193nm immersion optical lithography platform and the gate line tail cutting technique of following technology node thereof, and above-mentioned method comprises:
At first, as shown in Figure 2, deposit successively grid oxide layer 2, polysilicon layer (poly) 3, silicon nitride layer (SiN) 4, advanced figure rete (APF) 5 and medium anti-reflecting layer (Dielectric Anti_Reflectivity Coating on a silicon substrate (Silicon) 1, be called for short DARC) 6, to form structure as shown in Figure 2; Wherein, grid oxide layer 2, polysilicon layer (poly) 3 and silicon nitride layer (SiN) 4 common formation one grid layer structures; with the preparation for the subsequent gate structure; be that medium anti-reflecting layer 6 is of use not only in the advanced figure rete 5 of the middle protection of etching technics (opening mask etching) for the second time; can also, as photoetching process for the first time and the anti-reflecting layer in photoetching process for the second time, reduce the reflectivity of photoetching
Preferably, the thickness of polysilicon layer 3 is
(as
or
deng), the thickness of silicon nitride layer 4 is
(as
or
deng), the thickness of advanced figure rete 5 is
(as
or
deng), the thickness of medium anti-reflecting layer 6 is
(as
or
deng).
Further, the thickness of medium anti-reflecting layer 6 is
the thickness of advanced figure rete 5 is
the thickness of silicon nitride layer 4 is
the thickness of polysilicon layer 3 is
Secondly, on medium anti-reflecting layer 6, apply antireflection material, form the first bottom anti-reflection layer (Bottom Anti_Reflectivity Coating is called for short BARC) 7 that covers medium anti-reflecting layer 6 upper surfaces after solidifying, and continue follow-up etching technics.
Concrete, above-mentioned etching technics comprises the first photoetching process, the first etching technics, the second photoetching process and the second etching technics carried out successively; At the surperficial spin coating photoresist (PR) of the first above-mentioned bottom anti-reflection layer 7, after exposure, developing process, remove unnecessary photoresist, form the first photoresistance 8 with first hard mask structure plan, form structure as shown in Figure 3; Continuation be take this first photoresistance 8 and is carried out the first etching technics as mask, i.e. etching the first bottom anti-reflection layer 7, and stop at the inside of medium anti-reflecting layer 6, and the distance h between etching stopping position and advanced figure rete 5 upper surfaces is
(as
or
deng), after removing above-mentioned the first photoresistance 8 and remaining the first bottom anti-reflection layer, form the first hard mask structure 9 in remaining medium anti-reflecting layer 61, using for follow-up line tail cutting etching technics as the mask of opening advanced figure rete 5, be i.e. structure as shown in Figure 4.
Shown in Figure 5, again apply antireflection material, form the second bottom anti-reflection layer 71 that is full of (groove structure formed in the etching technics of front) and covers above-mentioned remaining hard mask layer after solidifying, surperficial spin coating photoresist in the second above-mentioned bottom anti-reflection layer 71, carry out that photoetching process (line-end-cut) for the second time exposes, after developing process, remove unnecessary photoresist, formation has the second photoresistance 81 of the second hard mask structure plan, forms structure as shown in Figure 5.
The second photoresistance 81 is take in continuation, and as mask carries out etching technics for the second time, (zone of this place's etching partially overlaps with the etch areas in the etching technics that forms the first hard mask structure 9, be that the etch areas of above-mentioned etching technics for the first time and the etch areas of the second etching technics have overlapping region, to complete gate line tail cutting technique), it is etching the second bottom anti-reflection layer 71, stop at the inside of remaining medium anti-reflecting layer 61, and the distance between this etching stopping position and advanced figure rete 5 upper surfaces is also
(as
or
deng), and with stop position in etching technics for the first time in the same horizontal line, after removing above-mentioned the second photoresistance 81 and remaining the second bottom anti-reflection layer, form the second hard mask structure 10 in remaining medium anti-reflecting layer 62 after etching again, using for follow-up line tail cutting etching technics as the mask of opening advanced figure rete 5, i.e. structure as shown in Figure 6.
Fig. 7 is the vertical view of structure shown in Fig. 6; As shown in Figure 7, in the second hard mask structure 10 formed in the second etching technics, because being carries out line tail cutting etching technics, make that in the second hard mask structure 10 of formation, at least one centre that the second hard mask structure is arranged to be arranged be cutting zone 101, the distance between this regional etching stopping position and advanced figure rete 5 upper surfaces is also h.
Further, the mode of because the hard mask structure (comprising the first hard mask structure 9 and the second hard mask structure 10) formed is the DARC hardmask structure of individual layer, common OES(optical emission spectroscopy) grabbing etching end point (endpoint) is difficult to realize; So, above-mentioned when darc layer is carried out to etching, utilize the forecast type endpoint Detection based on principle of interference to grab etching end point, as can be by utilizing the IEP(interferometric endpoint based on principle of interference on the 2300Kiyo EX board in LAM company) or LSR(Lam Spectral Reflectometer) the forecast type endpoint Detection is grabbed etching end point, so that etch process can stop at medium anti-reflecting layer h place accurately.
Preferably, in the above-mentioned nonoverlapping zone of Twi-lithography etching, the distance of the upper surface of the advanced figure rete of its etching stopping positional distance is
(as
or
deng), in the above-mentioned nonoverlapping zone of Twi-lithography etching, the distance of the upper surface of the advanced figure rete of its etching stopping positional distance is
(as
or
deng), effectively to avoid the advanced figure rete 5 that is arranged in below, at above-mentioned etching technics, sustain damage.
In addition, the interface that traditional OES detecting etching end point will be used two kinds of different medium materials, utilize the signal strength signal intensity of specific wavelength to jump to judge terminal, IEP and LSR utilize same medium to work as layer and the catoptrical interference effect of bottom is judged terminal, so the application only forms with individual layer DARC, the hardmask structure can be applied IEP or LSR carries out the crawl of etching end point.
Afterwards, the hard mask structure (jointly consisting of the first hard mask structure 9 and the second hard mask structure 10) of take is mask, remaining medium anti-reflecting layer 62 and advanced figure rete 5 are to the surface of silicon nitride layer 4 after etching again for etching successively, and the lip-deep advanced figure film mask 11(of silicon nitride layer 4 that is positioned at formed as shown in Figure 8 consists of final remaining medium anti-reflecting layer 63 and remaining advanced figure rete 51).
Finally, the above-mentioned advanced figure film mask 11 of take is mask, etch silicon nitride layer 4, polysilicon layer (poly) 3 and grid oxide layer 2 are to the surface of silicon substrate 1 successively, and remove above-mentioned advanced figure film mask 11, form by remaining silicon nitride layer 41, remaining polysilicon layer (poly) 31 and the common grid structure 13 formed of remaining grid oxide layer 21.
Wherein, the first above-mentioned bottom anti-reflection layer 7 and the thickness of the second bottom anti-reflection layer 71 all exist
(as
or
deng).
Further, in above-mentioned the first photoetching process and the second photoetching process, all adopt the ArF photoresist that wavelength is 193 nanometers to carry out the preparation of photoresistance, and its THICKNESS CONTROL exist
(as
or
deng).
Further, a kind of double-pattern forming method based on the DARC mask structure of the present embodiment, on the technology platforms such as Logic, Memory, RF, HV, CIS, Flash or eFlash, can be applicable in the technique of 32/38nm or 22nm and following technology node thereof.
Wherein, double-pattern metallization processes (Double patterning poly process) is for the technique of 22nm and following technology node thereof, by the employing technique that double exposes, solves the problem of photoetching resolution deficiency; Line-end-cut technique is the technique for 28nm and following technology node thereof, is used for cutting the poly line formed; And in this application, consider in line-end-cut technique that twice etching has overlapping part, so the thickness of the DARC of preparation or ONO structure is greater than the thickness of traditional structure.
To sum up, owing to having adopted technique scheme, the present invention proposes a kind of double-pattern forming method based on the DARC mask structure, by all adopting advanced figure film (Advanced Patterning Film in the twice etching technique at the double-pattern moulding process, be called for short APF) as the mask of etching technics, with the figure by photoresistance, be transferred on grid polycrystalline silicon, and then greatly improve the difference of critical size between twice etching technique, to improve key size evenness (CDU), this APF has also replaced traditional silica hard mask simultaneously, fabric ODL based on spin coating (spin-on) and interlayer structure SHB, when saving process costs, the APF that makes comparatively ripe 40nm and above technology node thereof adopt is extended on 28/20nm and following technology node thereof as the technological process of mask, and then maturity and the stability of 28/20nm and following technology node gate fabrication process thereof have been improved.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on spirit of the present invention, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.In claims scope, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. the double-pattern forming method based on the DARC mask structure, be applied to, in gate line tail cutting technique, it is characterized in that, comprises the following steps:
Have on the Semiconductor substrate of grid layer structure and deposit successively advanced figure rete and medium anti-reflecting layer in one;
Adopt the described medium anti-reflecting layer of etching technics etched portions, form the hard mask structure, and the upper surface of described advanced figure rete is all covered by remaining medium anti-reflecting layer;
The described hard mask structure of take is mask, and the described remaining medium anti-reflecting layer of etching and described advanced figure rete, to the surface of described grid layer structure, form advanced figure film mask;
Take described advanced figure film mask as the described grid layer structure of mask etching to the surface of described Semiconductor substrate, form grid structure;
Wherein, described etching technics includes gate line tail etching technics.
2. the double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, described grid structure comprises grid oxide layer, polysilicon layer and silicon nitride layer;
Described grid oxide layer covers the surface of described Semiconductor substrate, and described polysilicon layer covers the surface of described grid oxide layer, and described silicon nitride layer covers the surface of described polysilicon layer, and described advanced figure rete covers the surface of described silicon nitride layer.
3. the double-pattern forming method based on the DARC mask structure according to claim 2, is characterized in that, the thickness of described polysilicon layer is
4. the double-pattern forming method based on the DARC mask structure according to claim 2, is characterized in that, the thickness of described silicon nitride layer is
5. the double-pattern forming method based on the DARC mask structure according to claim 1, it is characterized in that, while carrying out the described medium anti-reflecting layer of above-mentioned etched portions technique, etching stopping is in the inside of this medium anti-reflecting layer, and the distance between etching stopping position and described advanced figure rete upper surface is
6. the double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, the thickness of medium anti-reflecting layer is
7. the double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, the thickness of described advanced figure rete is
8. the double-pattern forming method based on the DARC mask structure according to claim 1, it is characterized in that, described etching technics comprises the first photoetching process, the first etching technics, the second photoetching process and the second etching technics successively, and described hard mask structure comprises the first hard mask structure and the second hard mask structure;
After preparing the first bottom anti-reflection layer in the surface of described medium anti-reflecting layer, adopt described the first photoetching process to form the first photoresistance on described the first bottom anti-reflection layer, and to take this first photoresistance be mask, adopt described the first bottom anti-reflection layer of the described etching of etching technics for the first time, and stop at the inside of described medium anti-reflecting layer, after removing described the first photoresistance and remaining the first bottom anti-reflection layer, form described the first hard mask structure in remaining medium anti-reflecting layer;
Prepare the second bottom anti-reflection layer and cover described remaining described medium anti-reflecting layer, adopt described the second photoetching process to prepare the second photoresistance in the surface of described the second bottom anti-reflection layer, and to take this second photoresistance be mask, adopt the second etching technics partly to remove described remaining medium anti-reflecting layer, after removing described the second photoresistance and remaining the second bottom anti-reflection layer, form described the second hard mask structure in remaining medium anti-reflecting layer after etching again;
Wherein, described the second etching technics is gate line tail etching technics.
9. the double-pattern forming method based on the DARC mask structure according to claim 8, is characterized in that, the thickness of described the first bottom anti-reflection layer and described the second bottom anti-reflection layer is
10. the double-pattern forming method based on the DARC mask structure according to claim 8, is characterized in that, the thickness of described the first photoresistance and described the second photoresistance is
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346368A (en) * | 2010-07-23 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing double pattern exposure mask and double pattern exposure method |
| US20120034781A1 (en) * | 2010-08-05 | 2012-02-09 | Lung-En Kuo | Method for fabricating a semiconductor structure |
| US20120315748A1 (en) * | 2011-06-08 | 2012-12-13 | Feng-Yi Chang | Method for fabricating an aperture |
| US20130113085A1 (en) * | 2011-11-04 | 2013-05-09 | Applied Materials, Inc. | Atomic Layer Deposition Of Films Using Precursors Containing Hafnium Or Zirconium |
-
2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346368A (en) * | 2010-07-23 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing double pattern exposure mask and double pattern exposure method |
| US20120034781A1 (en) * | 2010-08-05 | 2012-02-09 | Lung-En Kuo | Method for fabricating a semiconductor structure |
| US20120315748A1 (en) * | 2011-06-08 | 2012-12-13 | Feng-Yi Chang | Method for fabricating an aperture |
| US20130113085A1 (en) * | 2011-11-04 | 2013-05-09 | Applied Materials, Inc. | Atomic Layer Deposition Of Films Using Precursors Containing Hafnium Or Zirconium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883477A (en) * | 2020-09-28 | 2020-11-03 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN111883477B (en) * | 2020-09-28 | 2020-12-22 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
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