CN103441066B - Based on the grid LELE double-pattern forming method of DARC mask structure - Google Patents
Based on the grid LELE double-pattern forming method of DARC mask structure Download PDFInfo
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Abstract
The present invention relates to microelectronics technology, particularly relate to a kind of grid LELE double-pattern forming method based on DARC mask structure, formed based on the dielectric anti reflective layer hard mask structure in advanced figure film layer by double exposure technique, to make the mask finally adopting APF as polysilicon etch process; In addition, in the second time etching technics of double-pattern moulding process, traditional silicon oxide hard mask is instead of, based on the fabric ODL of spin coating and interlayer structure SHB by utilizing DARC hard mask, make to adopt APF to be continued as the technological process of mask in comparatively ripe 40nm technology node, cost-effective while, also improve maturity and the stability of 22 nanometers and following technology node technique.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to a kind of grid LELE double-pattern forming method based on DARC mask structure.
Background technology
At present, on 32nm and following technology node thereof, be applied to the photoetching process of key level, resolution index needed for it has exceeded the limit capacity of existing optical lithography platform, industry have employed multiple technologies scheme and solves this technical problem, and according to ITRS route map, Dual graphing technology (DoublePatterningTechnology is called for short DPT), extreme ultraviolet line technology (EUV), electronics art are directly write technical schemes such as (EBL) and have all been expressed great expectations by industry.
Wherein, Dual graphing technology (DPT) is had great expectations of in the volume production of line tail cutting technique of the photoetching process of following 22nm and 28nm, this DPT technology is split as two covers by being decomposed by a set of highdensity circuitous pattern or overlaps the lower circuit diagram of closeness more, then reticle is made respectively, and successively complete corresponding exposure and etching technics, the final high density graph merging the initial demand of formation.
Along with the constantly progress of mask aligner software and hardware technology, based on the Dual graphing technology of immersed photoetching machine, the limiting resolution of 193nm immersion optical lithography platform and technical life further can be extended, thus can fill up between immersed photoetching machine and EUV or even the blank of the photoetching technique of less technology node.
According to technical investigation result, micro-shadow-etching-micro-shadow-etching (Litho-Etch-Litho-Etch, being called for short LELE) technology is one of current several Dual graphing mainstream technology scheme, namely go into targeted graphical by point other photoetching of twice with etching, and this targeted graphical comprises linear (line) and groove (trench) two kinds.
Fig. 1 a be in traditional double-pattern metallization processes first time the structural representation that formed of photoetching process, Fig. 1 b is the structural representation that in traditional double-pattern metallization processes, second time photoetching process is formed, and Fig. 1 c carries out the structural representation that grid LELE double-pattern moulding process formed in traditional double-pattern metallization processes, as illustrated by figures 1 a-1 c, as having 38nm half pitch (HalfPitch on 193nm immersion board (as NXT-1950i etc.), be called for short HP) resolution, in order to meet the design requirement of 22/20nm technology node active layer and gate layer, first carry out the first photoetching process formation structure as shown in Figure 1a, carry out second time photoetching process formation structure as shown in Figure 1 b again, and then by the structure (Exposure2) shown in the structure (Exposure1) shown in Fig. 1 a and Fig. 1 b by grid line end cutting technique formation structure (Finalcontour) as illustrated in figure 1 c, namely first formation repeats, line/isolation (Line/Space) figure of single direction, then grid line end cutting (Line-End-Cut) technique is carried out.
Traditional, in the grid technology of 22/20nm, mainly after first time chemical etching to polysilicon layer, utilize the fabric ODL(OrganicUnderLayer based on spin coating (spin-on)) fill underlying graphics, and continue to adopt interlayer structure SHB(SiO-basedHardMask) as the hard mask of for the second time etch process, finally prepare BARC(BottomAnti-ReflectiveCoating) and PR(PhotoResist) carried out the structure of secondary photoetching, namely adopt silica as hard mask, carry out the etch process of polysilicon layer.
Wherein, when carrying out above-mentioned first time etching technics, the advanced figure film of general employing (advancedpatterningfilm, be called for short APF) as softmask (soft-mask), then adopt ODL and SHB as softmask when carrying out second time etching technics, the critical size of the structure formed after making front and back twice etching technique is divided into two different levels, make to strengthen the control difficulty of key size evenness (CDU), if defect appears in key size evenness, very easily cause the reduction of properties of product and yield.
In addition, ODL and SHB is new material, and its process costs is higher, and is of little use in the technique of 40 nanometers and above technology node thereof; So, in the photoetching process of 22 nanometers and following technology node thereof, introduce these above-mentioned new materials to require a great deal of time and energy goes assessment and application.
Chinese patent (CN102446703A) describes a kind of method of Dual graphing, comprising: provide substrate, described substrate is formed with successively the first mask layer and the second mask layer; First mask layer described in anisotropic etching and the second mask layer, form the first opening in described first mask layer and the second mask layer, and described first opening exposes substrate surface; Second mask layer described in side direction partial etching; Form the 3rd mask layer over the substrate, described 3rd mask layer covers the first mask layer, and the second mask layer is exposed; Remove described second mask layer, in the 3rd mask layer, form the second opening, described second opening makes the first mask layer expose; With the 3rd mask layer for mask, the first mask layer below anisotropic etching second opening is until expose substrate; Remove described 3rd mask layer.Double-patterning method of the present invention avoids the uneven problem of substrate etching, effectively improves etching effect.
Chinese patent (CN102129968A) describes a kind of Double-patterning method, comprising: from bottom to top successively at deposited on substrates graph layer and spin coating first photoresist layer; Utilize ground floor litho pattern version photoetching first photoresist layer, and with the first photoresist layer after photoetching for mask etching graph layer; Remove the first photoresist layer, in the inter-pattern space that the surface of graph layer and graph layer etching are formed, deposit hard mask layer; Planarization is carried out to the surface of hard mask layer; The second photoresist layer is deposited at the flat surfaces of hard mask layer; Utilize second layer litho pattern version photoetching second photoresist layer, with the second photoresist layer after photoetching for mask etching hard mask layer and graph layer; Remove the second photoresist layer and hard mask layer.Double-patterning method of the present invention adds the evenness on surface, second layer photoetching process place, and then adds the process window of second layer photoetching process, improves second layer photoetching pattern control ability and etching technics window.
Summary of the invention
For above-mentioned technical problem, a kind of grid LELE double-pattern forming method based on DARC mask structure of the application, formed based at advanced figure film (AdvancedPatterningFilm by double exposure technique, be called for short APF) dielectric anti reflective layer (DielectricAnti-reflectiveCoating on layer, be called for short DARC) hard mask structure, to make the mask finally adopting APF as polysilicon etch process; In addition, in the second time etching technics of double-pattern moulding process, traditional silicon oxide hard mask is instead of, based on the fabric ODL of spin coating (spin-on) and interlayer structure SHB by utilizing DARC hard mask, make to adopt APF to be continued as the technological process of mask in comparatively ripe 40nm technology node, cost-effective while, also improve maturity and the stability of 22 nanometers and following technology node technique.
This invention describes a kind of grid LELE double-pattern forming method (AMethodofdoublepatterningtechnologybasedonsingleDARCmask layerforpolygate) based on DARC mask structure, wherein, comprise the following steps:
Upper surface in semi-conductive substrate deposits grid oxide layer, polysilicon layer, silicon nitride layer, advanced figure rete and dielectric anti reflective layer successively;
Etch described dielectric anti reflective layer, after forming hard mask structure, the upper surface of described advanced figure rete is all covered by remaining dielectric anti reflective layer;
With described hard mask structure for mask, etch described remaining dielectric anti reflective layer and the described advanced figure rete surface to described silicon nitride layer, form advanced figure film mask;
Etch described silicon nitride layer, described polysilicon layer and the described grid oxide layer upper surface to described Semiconductor substrate with described advanced figure film mask successively for mask, form grid structure.
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the thickness of described polysilicon layer is
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the thickness of described silicon nitride layer is
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, when carrying out dielectric anti reflective layer process described in above-mentioned etched portions, etching stopping is in the inside of this dielectric anti reflective layer, and the distance between etching stopping position and described advanced figure rete upper surface is
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the thickness of dielectric anti reflective layer is
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the thickness of described advanced figure rete is
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the technique of above-mentioned etching described dielectric anti reflective layer formation hard mask structure comprises: the first grid photoetching process of carrying out successively, first grid etching technics, second grid photoetching process and second grid etching technics;
After the first bottom anti-reflection layer is prepared on the surface of described dielectric anti reflective layer, described first grid photoetching process is adopted to form the first photoresistance in described first bottom anti-reflection layer, and with this first photoresistance for mask, described first grid etching technics is adopted to etch described first bottom anti-reflection layer, and stop at the inside of described dielectric anti reflective layer, after removing described first photoresistance and remaining first bottom anti-reflection layer, in remaining dielectric anti reflective layer, form the first hard mask structure;
Prepare the second bottom anti-reflection layer and cover described remaining described dielectric anti reflective layer, described second grid photoetching process is adopted to prepare the second photoresistance in the surface of described second bottom anti-reflection layer, and with this second photoresistance for mask, second grid etching technics part is adopted to remove described remaining dielectric anti reflective layer, after removing described second photoresistance and remaining second bottom anti-reflection layer, form the second hard mask structure in again etching in rear remaining dielectric anti reflective layer.
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, described hard mask structure comprises described first hard mask structure and described second hard mask structure.
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the thickness of described first bottom anti-reflection layer and described second bottom anti-reflection layer is
The above-mentioned grid LELE double-pattern forming method based on DARC mask structure, wherein, the thickness of described first photoresistance and described second photoresistance is
In sum, owing to have employed technique scheme, a kind of grid LELE double-pattern forming method based on DARC mask structure of the present invention, formed based at advanced figure film (AdvancedPatterningFilm by double exposure technique, be called for short APF) dielectric anti reflective layer (DielectricAnti-reflectiveCoating on layer, be called for short DARC) hard mask structure, to make the mask finally adopting APF as polysilicon etch process; In addition, in the second time etching technics of double-pattern moulding process, traditional silicon oxide hard mask is instead of, based on the fabric ODL of spin coating (spin-on) and interlayer structure SHB by utilizing DARC hard mask, make to adopt APF to be continued as the technological process of mask in comparatively ripe 40nm technology node, cost-effective while, also improve maturity and the stability of 22 nanometers and following technology node technique thereof.
Accompanying drawing explanation
Fig. 1 a be in traditional double-pattern metallization processes first time the structural representation that formed of photoetching process;
Fig. 1 b is the structural representation that in traditional double-pattern metallization processes, second time photoetching process is formed;
Fig. 1 c carries out the structural representation that grid LELE double-pattern moulding process formed in traditional double-pattern metallization processes;
Fig. 2-8 is flowage structure schematic diagrames of an embodiment in the grid LELE double-pattern forming method that the present invention is based on DARC mask structure.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 2-8 is flowage structure schematic diagrames of an embodiment in the grid LELE double-pattern forming method that the present invention is based on DARC mask structure; As illustrated in figs. 2 through 8, a kind of grid LELE double-pattern forming method based on DARC mask structure, preferably be applied to the grid line end cutting technique of 28/20 nanometer and the following technology node thereof carried out on 193nm immersion optical lithography platform, above-mentioned method comprises:
First, as shown in Figure 2, a silicon substrate (Silicon) 1 deposits grid oxide layer 2, polysilicon layer (poly) 3, silicon nitride layer (SiN) 4, advanced figure rete (APF) 5 and dielectric anti reflective layer (DielectricAnti_ReflectivityCoating successively, be called for short DARC) 6, to form structure as shown in Figure 2; Wherein, grid oxide layer 2, polysilicon layer (poly) 3 and silicon nitride layer (SiN) 4 form a grid layer jointly; for the preparation of subsequent gate structure; dielectric anti reflective layer 6 is then for the advanced figure rete 5 of protection in second time etching technics (opening mask etching); and as first time photoetching process and second time photoetching process in anti-reflecting layer, to reduce the reflectivity of photoetching.
Preferably, the thickness of polysilicon layer 3 is
(as
or
deng), the thickness of silicon nitride layer 4 is
(as
or
deng), the thickness of advanced figure rete 5 is
(as
or
deng), the thickness of dielectric anti reflective layer 6 is
(as
or
deng).
Further, the thickness of dielectric anti reflective layer 6 is
the thickness of advanced figure rete 5 is
the thickness of silicon nitride layer 4 is
the thickness of polysilicon layer 3 is
Secondly, in the upper surface coating antireflection material of dielectric anti reflective layer 6, form the first bottom anti-reflection layer (BottomAnti_ReflectivityCoating is called for short BARC) 7 covering dielectric anti reflective layer 6 upper surface after solidification, and continue follow-up etching technics.
Concrete, above-mentioned etching technics comprises the first grid photoetching process, first grid etching technics, second grid photoetching process and the second grid etching technics that carry out successively; Namely the surperficial spin coating photoresist (PR) of the first above-mentioned bottom anti-reflection layer 7, after exposure, developing process, remove unnecessary photoresist, form first photoresistance 8 with the first hard mask structure pattern, namely form structure as shown in Figure 3; Continue to carry out first grid etching technics with this first photoresistance 8 for mask, namely etch the first bottom anti-reflection layer 7, and stop at the inside of dielectric anti reflective layer 6, and the distance h between etching stopping position and advanced figure rete 5 upper surface is
(as
or
deng), after removing the first above-mentioned photoresistance 8 and remaining first bottom anti-reflection layer, in remaining dielectric anti reflective layer 61, form the first hard mask structure 9, in follow-up line tail grid etch technique as the mask opening advanced figure rete 5, i.e. structure as shown in Figure 4.
Shown in Figure 5, again apply antireflection material, formed after solidification and be full of (groove structure formed in etching technics) above and the second bottom anti-reflection layer 71 covering above-mentioned remaining hard mask layer, at the surperficial spin coating photoresist of the second above-mentioned bottom anti-reflection layer 71, carry out second grid photoetching process, namely after exposure, developing process, remove unnecessary photoresist, form second photoresistance 81 with the second hard mask structure pattern, namely form structure as shown in Figure 5.
Continue to carry out second time etching technics with the second photoresistance 81 for mask, namely etch the second bottom anti-reflection layer 71, stop at the inside of remaining dielectric anti reflective layer 61, and the distance between this etching stopping position and advanced figure rete 5 upper surface is also
(as
or
deng), and with stop position in above-mentioned first grid etching technics in the same horizontal line, after removing the second above-mentioned photoresistance 81 and remaining second bottom anti-reflection layer, the second hard mask structure 10 is formed in again etching in rear remaining dielectric anti reflective layer 62, this second hard mask structure 10 be also in follow-up line tail cutting etching technics as the mask opening advanced figure rete 5, i.e. structure as shown in Figure 6.
Further, because the hard mask structure (comprising the first hard mask structure 9 and the second hard mask structure 10) formed is the DARC hardmask structure of individual layer, common OES(opticalemissionspectroscopy) mode of grabbing etching end point (endpoint) is difficult to realize, so, above-mentioned darc layer is etched time, the forecast type endpoint Detection based on principle of interference is utilized to grab etching end point, as by utilizing the IEP(interferometricendpoint based on principle of interference on the 2300KiyoEX board of LAM company) or LSR(LamSpectralReflectometer) forecast type endpoint Detection grab etching end point, with the h place enabling etch process stop at dielectric anti reflective layer middle distance advanced figure rete 5 upper surface accurately, sustain damage at above-mentioned etching technics effectively to avoid the advanced figure rete 5 being arranged in below.
In addition, traditional OES detects the interface that etching end point will use two kinds of different medium materials, namely utilize the signal strength signal intensity of specific wavelength to jump and judge terminal, IEP and LSR then utilizes same medium to work as the interference effect of layer and bottom reverberation to judge terminal, so the application only forms hardmask structure with individual layer DARC can apply the crawl that IEP or LSR carries out etching end point.
Afterwards, with hard mask structure (being jointly made up of the first hard mask structure 9 and the second hard mask structure 10) for mask, etch the surface of the rear remaining dielectric anti reflective layer 62 of etching and advanced figure rete 5 to silicon nitride layer 4 again successively, and remove remaining dielectric anti reflective layer, form the advanced figure film mask 51 being positioned at silicon nitride layer 4 upper surface as shown in Figure 7.
Finally, with above-mentioned advanced figure film mask 51 for mask, the surface of etch nitride silicon layer 4, polysilicon layer (poly) 3 and grid oxide layer 2 to silicon substrate 1 successively, and remove above-mentioned advanced figure film mask 51, form the grid structure 13 be jointly made up of remaining silicon nitride layer 41, remaining polysilicon layer (poly) 31 and remaining grid oxide layer 21.
Wherein, the first above-mentioned bottom anti-reflection layer 7 and the thickness of the second bottom anti-reflection layer 71 all exist
(as
or
deng).
Further, in the first above-mentioned photoetching process and the second photoetching process, adopt wavelength to be the preparation that the ArF photoresist of 193 nanometers carries out photoresistance, and its THICKNESS CONTROL exist
(as
900
or
deng).
Further, a kind of grid LELE double-pattern forming method based on DARC mask structure of the present embodiment, on the technology platforms such as Logic, Memory, RF, HV, CIS, Flash or eFlash, can be applicable in the technique of 22nm and following technology node thereof.
Wherein, double-pattern metallization processes (Doublepatterningpolyprocess) in the technique of 22nm and following technology node thereof, the problem namely by adopting double exposure technique to solve photoetching resolution deficiency; Line-end-cut technique is then in the technique for 28nm and following technology node thereof, is namely used for cutting the polyline formed; And in this application, consider that in line-end-cut technique, twice etching has overlapping part, so the thickness of DARC or the ONO structure of preparation is greater than the thickness of traditional structure.
To sum up, owing to have employed technique scheme, the present invention proposes a kind of grid LELE double-pattern forming method based on DARC mask structure, formed based at advanced figure film (AdvancedPatterningFilm by double exposure technique, be called for short APF) dielectric anti reflective layer (DielectricAnti-reflectiveCoating on layer, be called for short DARC) hard mask structure, to make the mask finally adopting APF as polysilicon etch process; In addition, in the second time etching technics of double-pattern moulding process, traditional silicon oxide hard mask is instead of, based on the fabric ODL of spin coating (spin-on) and interlayer structure SHB by utilizing DARC hard mask, make to adopt APF to be continued as the technological process of mask in comparatively ripe 40nm technology node, cost-effective while, also improve maturity and the stability of 22 nanometers and following technology node technique.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (9)
1., based on a grid LELE double-pattern forming method for DARC mask structure, it is characterized in that, comprise the following steps:
Upper surface in semi-conductive substrate deposits grid oxide layer, polysilicon layer, silicon nitride layer, advanced figure rete and dielectric anti reflective layer successively;
Etch described dielectric anti reflective layer, after forming hard mask structure, the upper surface of described advanced figure rete is all covered by remaining dielectric anti reflective layer;
With described hard mask structure for mask, etch described remaining dielectric anti reflective layer and the described advanced figure rete surface to described silicon nitride layer, form advanced figure film mask;
Etch described silicon nitride layer, described polysilicon layer and the described grid oxide layer upper surface to described Semiconductor substrate with described advanced figure film mask successively for mask, form grid structure;
The technique wherein etching described dielectric anti reflective layer formation hard mask structure comprises:
The first grid photoetching process of carrying out successively, first grid etching technics, second grid photoetching process and second grid etching technics;
After the first bottom anti-reflection layer is prepared on the surface of described dielectric anti reflective layer, described first grid photoetching process is adopted to form the first photoresistance in described first bottom anti-reflection layer, and with this first photoresistance for mask, described first grid etching technics is adopted to etch described first bottom anti-reflection layer, and stop at the inside of described dielectric anti reflective layer, after removing described first photoresistance and remaining first bottom anti-reflection layer, in remaining dielectric anti reflective layer, form the first hard mask structure;
Prepare the second bottom anti-reflection layer and cover described remaining described dielectric anti reflective layer, described second grid photoetching process is adopted to prepare the second photoresistance in the surface of described second bottom anti-reflection layer, and with this second photoresistance for mask, second grid etching technics part is adopted to remove described remaining dielectric anti reflective layer, after removing described second photoresistance and remaining second bottom anti-reflection layer, form the second hard mask structure in again etching in rear remaining dielectric anti reflective layer.
2. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, the thickness of described polysilicon layer is
3. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, the thickness of described silicon nitride layer is
4. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, when carrying out dielectric anti reflective layer process described in above-mentioned etched portions, etching stopping is in the inside of this dielectric anti reflective layer, and the distance between etching stopping position and described advanced figure rete upper surface is
5. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, the thickness of dielectric anti reflective layer is
6. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, the thickness of described advanced figure rete is
7. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, described hard mask structure comprises described first hard mask structure and described second hard mask structure.
8. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, the thickness of described first bottom anti-reflection layer and described second bottom anti-reflection layer is
9. the grid LELE double-pattern forming method based on DARC mask structure according to claim 1, it is characterized in that, the thickness of described first photoresistance and described second photoresistance is
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| CN101303525A (en) * | 2008-06-23 | 2008-11-12 | 上海集成电路研发中心有限公司 | Double-pattern exposure process |
| CN101446760A (en) * | 2007-11-30 | 2009-06-03 | 台湾积体电路制造股份有限公司 | Double patterning strategy for contact hole and trench |
| CN101471234A (en) * | 2007-12-28 | 2009-07-01 | 海力士半导体有限公司 | Method of forming a semiconductor device pattern |
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| CN101446760A (en) * | 2007-11-30 | 2009-06-03 | 台湾积体电路制造股份有限公司 | Double patterning strategy for contact hole and trench |
| CN101471234A (en) * | 2007-12-28 | 2009-07-01 | 海力士半导体有限公司 | Method of forming a semiconductor device pattern |
| CN101303525A (en) * | 2008-06-23 | 2008-11-12 | 上海集成电路研发中心有限公司 | Double-pattern exposure process |
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