CN103441066A - Grid electrode LELE dual graph forming method based on DARC mask structure - Google Patents
Grid electrode LELE dual graph forming method based on DARC mask structure Download PDFInfo
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Abstract
The invention relates to the technical field of microelectronics, in particular to a grid electrode LELE dual graph forming method based on a DARC mask structure. A medium anti-reflection layer hard mask structure based on an advanced graph film layer is formed through double exposure techniques, so that an APF is finally used as a mask for a polycrystalline silicon etching technique. In addition, in the second etching process of a dual graph forming technique, a DARC hard mask is used for replacing a traditional silicon oxide hard mask, a bottom layer structure ODL based on spin coating and a middle layer structure SHB, so that the technical process where the APF is used as the mask in a relatively mature 40nm technology node is continued. Therefore, cost is reduced, and the maturity and stability of a 22-namometer technology node technique and technology node techniques below 22 namometers are further improved at the same time.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of grid LELE double-pattern forming method based on the DARC mask structure.
Background technology
At present, on 32nm and following technology node thereof, be applied to the photoetching process of key level, because its required resolution index has surpassed the limit capacity of existing optical lithography platform, industry has adopted the multiple technologies scheme to solve this technical problem, and, according to shown in the ITRS route map, Dual graphing technology (Double Patterning Technology is called for short DPT), extreme ultraviolet line technology (EUV), electronics art are directly write technical schemes such as (EBL) and all by industry, have been expressed great expectations.
Wherein, Dual graphing technology (DPT) is had great expectations of in the volume production of line tail cutting technique of the photoetching process of following 22nm and 28nm, this DPT technology is by a set of highdensity circuitous pattern is decomposed and is split as two covers or overlaps the circuit diagram that closeness is lower more, then make respectively reticle, and successively completing corresponding exposure and etching technics, final merging forms the high density graph of initial demand.
Along with the mask aligner software and hardware technology is constantly progressive, Dual graphing technology based on immersed photoetching machine, limiting resolution and the technical life of 193nm immersion optical lithography platform further can be extended, thereby can fill up between immersed photoetching machine and EUV or even the blank of the photoetching technique of less technology node.
According to the technical investigation result, micro-shadow-etching-micro-shadow-etching (Litho-Etch-Litho-Etch, abbreviation LELE) technology is one of current several Dual graphing mainstream technology schemes, become targeted graphical by minute other photoetching of twice with the etching row, and this targeted graphical comprises two kinds of linear (line) and grooves (trench).
Fig. 1 a is the structural representation that in traditional double-pattern metallization processes, photoetching process forms for the first time, Fig. 1 b is the structural representation that in traditional double-pattern metallization processes, photoetching process forms for the second time, and Fig. 1 c carries out the structural representation that grid LELE double-pattern moulding process forms in traditional double-pattern metallization processes, as shown in Fig. 1 a-1c, as on 193nm immersion board (as NXT-1950i etc.), there is 38nm half pitch (Half Pitch, abbreviation HP) resolution, in order to meet the design requirement of 22/20nm technology node active layer and grid layer, first carry out the first photoetching process formation structure as shown in Figure 1a, carry out again photoetching process for the second time and form structure as shown in Figure 1 b, and then the structure (Exposure2) shown in the structure (Exposure1) shown in Fig. 1 a and Fig. 1 b is formed to the structure (Final contour) as shown in Fig. 1 c by gate line tail cutting technique, i.e. first formation repeats, the line of single direction/isolation (Line/Space) figure, then carry out gate line tail cutting (Line-End-Cut) technique.
Traditional, in the grid technology of 22/20nm, be mainly through chemical etching for the first time to polysilicon layer, the fabric ODL(Organic Under Layer of utilization based on spin coating (spin-on)) fill the bottom figure, and continue to adopt interlayer structure SHB(SiO-based Hard Mask) as the hard mask of etch process for the second time, finally prepare BARC(Bottom Anti-Reflective Coating) and PR(Photo Resist) structure of secondary photoetching completed, adopt silica as hard mask, carry out the etch process of polysilicon layer.
Wherein, when carrying out above-mentioned etching technics for the first time, general advanced figure film (the advanced patterning film that adopts, be called for short APF) as softmask (soft-mask), while carrying out for the second time etching technics, be to adopt ODL and SHB as softmask, the critical size of the structure formed after twice etching technique before and after making is divided into two different levels, make the control difficulty to key size evenness (CDU) strengthen, if defect appears in key size evenness, very easily cause the reduction of properties of product and yield.
In addition, ODL and SHB are new materials, and its process costs is higher, and in the technique of 40 nanometers and above technology node thereof and be of little use; So these above-mentioned new materials of introduction require a great deal of time and go assessment and application with energy in the photoetching process of 22 nanometers and following technology node thereof.
Chinese patent (CN102446703A) has been put down in writing a kind of method of Dual graphing, comprising: substrate is provided, is formed with successively the first mask layer and the second mask layer on described substrate; Described the first mask layer of anisotropic etching and the second mask layer form the first opening in described the first mask layer and the second mask layer, and described the first opening exposes substrate surface; Described the second mask layer of side direction partial etching; Form the 3rd mask layer on described substrate, described the 3rd mask layer covers the first mask layer, and makes the second mask layer expose; Remove described the second mask layer, form the second opening in the 3rd mask layer, described the second opening makes the first mask layer expose; The 3rd mask layer of take is mask, and the first mask layer of anisotropic etching the second opening below is until expose substrate; Remove described the 3rd mask layer.Double-patterning method of the present invention has been avoided the inhomogeneous problem of substrate etching, has effectively improved etching effect.
Chinese patent (CN102129968A) has been put down in writing a kind of Double-patterning method, comprising: deposition pattern layer and spin coating the first photoresist layer on substrate successively from bottom to top; Utilize ground floor litho pattern version photoetching the first photoresist layer, and first photoresist layer of take after photoetching is the mask etching graph layer; Remove the first photoresist layer, in the inter-pattern space that the surface of graph layer and graph layer etching form, deposit hard mask layer; Planarization is carried out on surface to hard mask layer; Flat surfaces at hard mask layer deposits the second photoresist layer; The second photoresist layer that utilizes second layer litho pattern version photoetching the second photoresist layer, take after photoetching is mask etching hard mask layer and graph layer; Remove the second photoresist layer and hard mask layer.Double-patterning method of the present invention has increased the evenness on surface, second layer photoetching process place, and then has increased the process window of second layer photoetching process, has improved second layer photoetching pattern control ability and etching technics window.
Summary of the invention
For above-mentioned technical problem, a kind of grid LELE double-pattern forming method based on the DARC mask structure of the application, by double exposure technique, form based at advanced figure film (Advanced Patterning Film, abbreviation APF) medium anti-reflecting layer (the Dielectric Anti-reflective Coating on layer, be called for short DARC) the hard mask structure, so that finally adopt the mask of APF as the polysilicon etch process; In addition, in the etching technics for the second time of double-pattern moulding process, by utilizing the DARC hard mask to replace traditional silica hard mask, fabric ODL and interlayer structure SHB based on spin coating (spin-on), make in comparatively ripe 40nm technology node and adopt APF to be continued as the technological process of mask, in the cost-effective while, also improved maturity and the stability of 22 nanometers and following technology node technique.
The present invention has put down in writing a kind of grid LELE double-pattern forming method (AMethod of double patterning technology based on single DARC mask layer for poly gate) based on the DARC mask structure, wherein, comprise the following steps:
Upper surface in semi-conductive substrate deposits grid oxide layer, polysilicon layer, silicon nitride layer, advanced figure rete and medium anti-reflecting layer successively;
The described medium anti-reflecting layer of etching, after forming the hard mask structure, the upper surface of described advanced figure rete is all covered by remaining medium anti-reflecting layer;
The described hard mask structure of take is mask, and the described remaining medium anti-reflecting layer of etching and described advanced figure rete, to the surface of described silicon nitride layer, form advanced figure film mask;
Take described advanced figure film mask as the described silicon nitride layer of mask etching successively, described polysilicon layer and described grid oxide layer to the upper surface of described Semiconductor substrate, form grid structure.
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the thickness of described polysilicon layer is
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the thickness of described silicon nitride layer is
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, while carrying out the described medium anti-reflecting layer of above-mentioned etched portions technique, etching stopping is in the inside of this medium anti-reflecting layer, and the distance between etching stopping position and described advanced figure rete upper surface is
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the thickness of medium anti-reflecting layer is
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the thickness of described advanced figure rete is
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the technique of the described medium anti-reflecting layer formation of above-mentioned etching hard mask structure comprises: the first grid photoetching process of carrying out successively, first grid etching technics, second grid photoetching process and second grid etching technics;
After preparing the first bottom anti-reflection layer in the surface of described medium anti-reflecting layer, adopt described first grid photoetching process to form the first photoresistance on described the first bottom anti-reflection layer, and to take this first photoresistance be mask, adopt described the first bottom anti-reflection layer of described first grid etching technics etching, and stop at the inside of described medium anti-reflecting layer, after removing described the first photoresistance and remaining the first bottom anti-reflection layer, form the first hard mask structure in remaining medium anti-reflecting layer;
Prepare the second bottom anti-reflection layer and cover described remaining described medium anti-reflecting layer, adopt described second grid photoetching process to prepare the second photoresistance in the surface of described the second bottom anti-reflection layer, and to take this second photoresistance be mask, adopt the second grid etching technics partly to remove described remaining medium anti-reflecting layer, after removing described the second photoresistance and remaining the second bottom anti-reflection layer, form the second hard mask structure in remaining medium anti-reflecting layer after etching again.
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, described hard mask structure comprises described the first hard mask structure and described the second hard mask structure.
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the thickness of described the first bottom anti-reflection layer and described the second bottom anti-reflection layer is
The above-mentioned grid LELE double-pattern forming method based on the DARC mask structure, wherein, the thickness of described the first photoresistance and described the second photoresistance is
In sum, owing to having adopted technique scheme, a kind of grid LELE double-pattern forming method based on the DARC mask structure of the present invention, by double exposure technique, form based at advanced figure film (Advanced Patterning Film, abbreviation APF) medium anti-reflecting layer (the Dielectric Anti-reflective Coating on layer, be called for short DARC) the hard mask structure, so that finally adopt the mask of APF as the polysilicon etch process; In addition, in the etching technics for the second time of double-pattern moulding process, by utilizing the DARC hard mask to replace traditional silica hard mask, fabric ODL and interlayer structure SHB based on spin coating (spin-on), make in comparatively ripe 40nm technology node and adopt APF to be continued as the technological process of mask, in the cost-effective while, also improved maturity and the stability of 22 nanometers and following technology node technique thereof.
The accompanying drawing explanation
Fig. 1 a is the structural representation that in traditional double-pattern metallization processes, photoetching process forms for the first time;
Fig. 1 b is the structural representation that in traditional double-pattern metallization processes, photoetching process forms for the second time;
Fig. 1 c carries out the structural representation that grid LELE double-pattern moulding process forms in traditional double-pattern metallization processes;
Fig. 2-8th, the present invention is based on the flowage structure schematic diagram of an embodiment in the grid LELE double-pattern forming method of DARC mask structure.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 2-8th, the present invention is based on the flowage structure schematic diagram of an embodiment in the grid LELE double-pattern forming method of DARC mask structure; As shown in Fig. 2-8, a kind of grid LELE double-pattern forming method based on the DARC mask structure, preferably be applied to 28/20 nanometer of carrying out on 193nm immersion optical lithography platform and the gate line tail cutting technique of following technology node thereof, above-mentioned method comprises:
At first, as shown in Figure 2, deposit successively grid oxide layer 2, polysilicon layer (poly) 3, silicon nitride layer (SiN) 4, advanced figure rete (APF) 5 and medium anti-reflecting layer (Dielectric Anti_Reflectivity Coating on a silicon substrate (Silicon) 1, be called for short DARC) 6, to form structure as shown in Figure 2; Wherein, grid oxide layer 2, polysilicon layer (poly) 3 and silicon nitride layer (SiN) 4 common formation one grid layers; with the preparation for the subsequent gate structure; medium anti-reflecting layer 6 is at the advanced figure rete 5 of the protection of etching technics (opening mask etching) for the second time; and as photoetching process for the first time and the anti-reflecting layer in photoetching process for the second time, to reduce the reflectivity of photoetching.
Preferably, the thickness of polysilicon layer 3 is
(as
or
deng), the thickness of silicon nitride layer 4 is
(as
or
deng), the thickness of advanced figure rete 5 is
(as
or
deng), the thickness of medium anti-reflecting layer 6 is
(as
or
deng).
Further, the thickness of medium anti-reflecting layer 6 is
the thickness of advanced figure rete 5 is
the thickness of silicon nitride layer 4 is
the thickness of polysilicon layer 3 is
Secondly, upper surface in medium anti-reflecting layer 6 applies antireflection material, form the first bottom anti-reflection layer (Bottom Anti_Reflectivity Coating is called for short BARC) 7 that covers medium anti-reflecting layer 6 upper surfaces after solidifying, and continue follow-up etching technics.
Concrete, above-mentioned etching technics comprises first grid photoetching process, first grid etching technics, second grid photoetching process and the second grid etching technics carried out successively; At the surperficial spin coating photoresist (PR) of the first above-mentioned bottom anti-reflection layer 7, after exposure, developing process, remove unnecessary photoresist, form the first photoresistance 8 with first hard mask structure plan, form structure as shown in Figure 3; Continuation be take this first photoresistance 8 and is carried out the first grid etching technics as mask, i.e. etching the first bottom anti-reflection layer 7, and stop at the inside of medium anti-reflecting layer 6, and the distance h between etching stopping position and advanced figure rete 5 upper surfaces is
(as
or
deng), after removing above-mentioned the first photoresistance 8 and remaining the first bottom anti-reflection layer, form the first hard mask structure 9 in remaining medium anti-reflecting layer 61, using for follow-up line tail grid etch technique as the mask of opening advanced figure rete 5, be i.e. structure as shown in Figure 4.
Shown in Figure 5, again apply antireflection material, form the second bottom anti-reflection layer 71 that is full of (groove structure formed in the etching technics of front) and covers above-mentioned remaining hard mask layer after solidifying, surperficial spin coating photoresist in the second above-mentioned bottom anti-reflection layer 71, carry out the second grid photoetching process,, after exposure, developing process, remove unnecessary photoresist, formation has the second photoresistance 81 of the second hard mask structure plan, forms structure as shown in Figure 5.
Continuation be take the second photoresistance 81 and is carried out etching technics for the second time as mask, i.e. etching the second bottom anti-reflection layer 71 stop at the inside of remaining medium anti-reflecting layer 61, and the distance between this etching stopping position and advanced figure rete 5 upper surfaces is also
(as
or
deng), and with stop position in above-mentioned first grid etching technics in the same horizontal line, after removing above-mentioned the second photoresistance 81 and remaining the second bottom anti-reflection layer, form the second hard mask structure 10 in remaining medium anti-reflecting layer 62 after etching again, this the second hard mask structure 10 be also for follow-up line tail cutting etching technics as the mask of opening advanced figure rete 5, i.e. structure as shown in Figure 6.
Further, the mode of because the hard mask structure (comprising the first hard mask structure 9 and the second hard mask structure 10) formed is the DARC hardmask structure of individual layer, common OES(optical emission spectroscopy) grabbing etching end point (endpoint) is difficult to realize, so, above-mentioned when darc layer is carried out to etching, utilize the forecast type endpoint Detection based on principle of interference to grab etching end point, as can be by utilizing the IEP(interferometric endpoint based on principle of interference on the 2300Kiyo EX board in LAM company) or LSR(Lam Spectral Reflectometer) the forecast type endpoint Detection grabs etching end point, so that etch process can stop at the h place of the advanced figure rete of medium anti-reflecting layer middle distance 5 upper surfaces accurately, effectively to avoid the advanced figure rete 5 that is arranged in below to sustain damage at above-mentioned etching technics.
In addition, the interface that traditional OES detecting etching end point will be used two kinds of different medium materials, utilize the signal strength signal intensity of specific wavelength to jump to judge terminal, IEP and LSR utilize same medium to work as layer and the catoptrical interference effect of bottom is judged terminal, so the application only forms with individual layer DARC, the hardmask structure can be applied IEP or LSR carries out the crawl of etching end point.
Afterwards, the hard mask structure (jointly consisting of the first hard mask structure 9 and the second hard mask structure 10) of take is mask, successively etching again after etching remaining medium anti-reflecting layer 62 and advanced figure rete 5 to the surface of silicon nitride layer 4, and remove remaining medium anti-reflecting layer, form the advanced figure film mask 51 that is positioned at silicon nitride layer 4 upper surfaces as shown in Figure 7.
Finally, the above-mentioned advanced figure film mask 51 of take is mask, etch silicon nitride layer 4, polysilicon layer (poly) 3 and grid oxide layer 2 are to the surface of silicon substrate 1 successively, and remove above-mentioned advanced figure film mask 51, form by remaining silicon nitride layer 41, remaining polysilicon layer (poly) 31 and the common grid structure 13 formed of remaining grid oxide layer 21.
Wherein, the first above-mentioned bottom anti-reflection layer 7 and the thickness of the second bottom anti-reflection layer 71 all exist
(as
or
deng).
Further, in above-mentioned the first photoetching process and the second photoetching process, adopt the ArF photoresist that wavelength is 193 nanometers to carry out the preparation of photoresistance, and its THICKNESS CONTROL exist
(as
900
or
deng).
Further, a kind of grid LELE double-pattern forming method based on the DARC mask structure of the present embodiment, on the technology platforms such as Logic, Memory, RF, HV, CIS, Flash or eFlash, can be applicable in the technique of 22nm and following technology node thereof.
Wherein, double-pattern metallization processes (Double patterning poly process) is for the technique of 22nm and following technology node thereof, by the employing technique that double exposes, solves the problem of photoetching resolution deficiency; Line-end-cut technique is the technique for 28nm and following technology node thereof, is used for cutting the poly line formed; And in this application, consider in line-end-cut technique that twice etching has overlapping part, so the thickness of the DARC of preparation or ONO structure is greater than the thickness of traditional structure.
To sum up, owing to having adopted technique scheme, the present invention proposes a kind of grid LELE double-pattern forming method based on the DARC mask structure, by double exposure technique, form based at advanced figure film (Advanced Patterning Film, abbreviation APF) medium anti-reflecting layer (the Dielectric Anti-reflective Coating on layer, be called for short DARC) the hard mask structure, so that finally adopt the mask of APF as the polysilicon etch process; In addition, in the etching technics for the second time of double-pattern moulding process, by utilizing the DARC hard mask to replace traditional silica hard mask, fabric ODL and interlayer structure SHB based on spin coating (spin-on), make in comparatively ripe 40nm technology node and adopt APF to be continued as the technological process of mask, in the cost-effective while, also improved maturity and the stability of 22 nanometers and following technology node technique.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on spirit of the present invention, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.In claims scope, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. the grid LELE double-pattern forming method based on the DARC mask structure, is characterized in that, comprises the following steps:
Upper surface in semi-conductive substrate deposits grid oxide layer, polysilicon layer, silicon nitride layer, advanced figure rete and medium anti-reflecting layer successively;
The described medium anti-reflecting layer of etching, after forming the hard mask structure, the upper surface of described advanced figure rete is all covered by remaining medium anti-reflecting layer;
The described hard mask structure of take is mask, and the described remaining medium anti-reflecting layer of etching and described advanced figure rete, to the surface of described silicon nitride layer, form advanced figure film mask;
Take described advanced figure film mask as the described silicon nitride layer of mask etching successively, described polysilicon layer and described grid oxide layer to the upper surface of described Semiconductor substrate, form grid structure.
2. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, the thickness of described polysilicon layer is
3. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, the thickness of described silicon nitride layer is
4. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 1, it is characterized in that, while carrying out the described medium anti-reflecting layer of above-mentioned etched portions technique, etching stopping is in the inside of this medium anti-reflecting layer, and the distance between etching stopping position and described advanced figure rete upper surface is
5. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, the thickness of medium anti-reflecting layer is
6. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 1, is characterized in that, the thickness of described advanced figure rete is
7. according to the described grid LELE double-pattern forming method based on the DARC mask structure of any one in claim 1-6, it is characterized in that, the technique that the described medium anti-reflecting layer of above-mentioned etching forms the hard mask structure comprises: the first grid photoetching process of carrying out successively, first grid etching technics, second grid photoetching process and second grid etching technics;
After preparing the first bottom anti-reflection layer in the surface of described medium anti-reflecting layer, adopt described first grid photoetching process to form the first photoresistance on described the first bottom anti-reflection layer, and to take this first photoresistance be mask, adopt described the first bottom anti-reflection layer of described first grid etching technics etching, and stop at the inside of described medium anti-reflecting layer, after removing described the first photoresistance and remaining the first bottom anti-reflection layer, form the first hard mask structure in remaining medium anti-reflecting layer;
Prepare the second bottom anti-reflection layer and cover described remaining described medium anti-reflecting layer, adopt described second grid photoetching process to prepare the second photoresistance in the surface of described the second bottom anti-reflection layer, and to take this second photoresistance be mask, adopt the second grid etching technics partly to remove described remaining medium anti-reflecting layer, after removing described the second photoresistance and remaining the second bottom anti-reflection layer, form the second hard mask structure in remaining medium anti-reflecting layer after etching again.
8. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 7, is characterized in that, described hard mask structure comprises described the first hard mask structure and described the second hard mask structure.
9. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 7, is characterized in that, the thickness of described the first bottom anti-reflection layer and described the second bottom anti-reflection layer is
10. the grid LELE double-pattern forming method based on the DARC mask structure according to claim 7, is characterized in that, the thickness of described the first photoresistance and described the second photoresistance is
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| CN103887224A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for forming shallow trench isolation |
| CN110896029A (en) * | 2019-10-25 | 2020-03-20 | 上海华力微电子有限公司 | Etching method and method for manufacturing semiconductor device |
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