CN103871846B - The application of autoregistration multiple patterning methods and silicon substrate hard mask compositions - Google Patents
The application of autoregistration multiple patterning methods and silicon substrate hard mask compositions Download PDFInfo
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- CN103871846B CN103871846B CN201210553343.1A CN201210553343A CN103871846B CN 103871846 B CN103871846 B CN 103871846B CN 201210553343 A CN201210553343 A CN 201210553343A CN 103871846 B CN103871846 B CN 103871846B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
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Abstract
The invention discloses the application of a kind of autoregistration multiple patterning methods and silicon substrate hard mask compositions, it is used as RELACS material the process employs the silicon substrate hard mask compositions, on a semiconductor substrate after formation photoetching offset plate figure, this siliceous RELACS material is covered on photoetching offset plate figure, then mixing baking is carried out, so as to form cross-linked layer on the surface of photoetching offset plate figure, side wall is formed followed by the cross-linked layer, in subsequent process steps can with side wall be mask transferring the graphic in Semiconductor substrate, the figure that formation intentionally gets.Compared with the self-alignment duplex pattern method realized using existing RELACS material, it is not high that the present invention can solve the verticality of side wall that existing self-alignment duplex pattern method obtains figure, and bottom antireflective coating can be by excessive etching, so that the problem that the Semiconductor substrate below bottom antireflective coating may sustain damage in existing self-alignment duplex pattern method.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of silicon substrate hard mask compositions are used as RELACS material
Application, and the method for realizing autoregistration multiple graphical using the silicon substrate hard mask compositions.
Background technology
With the continuous diminution of dimensions of semiconductor devices, lithographic feature size is moved closer to and has been even more than optical lithography
Physics limit, thus to semiconductor fabrication, especially photoetching technique proposes more acute challenge.Extreme ultraviolet（EUV）
Photoetching technique possesses smaller photoetching resolution, but can not realize the diminution of lithographic feature size for various reasons, therefore needs
Continue to expand photoetching technique.By means of more extreme RET（RET）, such as powerful phase shifting mask（PSM）Skill
Art, various lighting engineering and optical approach effect amendment（OPC）Technology etc., can further expand photoetching technique.In addition, submergence
Formula photoetching technique then by filling certain liquid between projection objective and photoresist, effectively increases the numerical value of etching system
Aperture（NA）, it is achieved thereby that smaller lithographic feature size, promotes the development of photoetching technique.
In addition, double-pattern（Double patterning, abbreviation DP）Technology is set not changing existing photoetching basis
On the premise of applying, the development of photoetching technique is also promoted as a kind of technology for effectively improving photoetching resolution.The base of the technology
This thought is that mask graph is divided into two, and the unobtainable lithographic feature size of single exposure is obtained by double exposure
The limit, while also greatly extending the service life of existing lithographic equipment, therefore is widely used.Double-pattern skill
The basic implementation method of art includes LELE（Litho-Etch-Litho-Etch, exposure-etching-exposure-etching）Double-pattern side
Method, LFLE（Litho-Freeze-Litho-Etch, exposure-solidification-exposure-etching）Double-patterning method and autoregistration are double
Weight is graphical（Self-aligned Double patterning, abbreviation SADP）Method.Wherein, self-alignment duplex pattern side
Method forms side wall by preformed litho pattern both sides（spacer）, the light needle drawing for then being formed before etching removal
Shape, and side wall figure is transferred to subsurface material, the figure smaller so as to obtain characteristic size, and the pattern density for obtaining is it
The twice of preceding litho pattern density.
In the disclosure of on May 7th, 2002, Publication No. US6383952B1, entitled " RELACS processto double
The United States Patent (USP) of the frequency or pitch of small feature formation " discloses a kind of autoregistration
Double-patterning method, is briefly described with reference to Fig. 1 to Fig. 5 to this method：
As shown in Figure 1, there is provided Semiconductor substrate 1, photoresist layer is formed on semiconductor substrate 1（It is not shown）, to described
Photoresist layer is exposed, develops, and forms multiple（At least two, in figure as a example by four）The photoetching of parallel, spaced-apart distribution
Glue pattern 3.In order to reduce the reflection in exposed photoresist layer, before the photoresist layer is formed on semiconductor substrate 1 first
Form bottom antireflective coating（BARC）2, can so cause the sidewall profile of photoetching offset plate figure 3 more preferably.
As shown in Fig. 2 forming RELACS on bottom antireflective coating 2 and photoetching offset plate figure 3（resolution
Enhancement lithography assisted by chemical shrink, chemical shrinkage-assisted analysis enhancing）Material
Layer 4, RELACS material layer 4 covers the surface of photoetching offset plate figure 3, the i.e. top of photoetching offset plate figure 3 and side wall.
The RELACS material is Clariant（Clariant）One kind that company develops can be applicable to semiconductor manufacturing
Organic material in field, for example, magazine《Semiconductor is international》（《Semiconductor International》）In 1999
September discloses an author for Laura J.Peters, entitled " Resists Join the Sub-Lambda
The article of Revolution ", this paper describe a kind of semiconductor technology proposed by Mitsubishi, and the technique is graphical
For after the KrF photoresist layers for defining lead to the hole site, by forming the RELACS material, baking（bake）, cleaning
（rinse）Processing step the size of through hole is reduced to 0.1 μm by 0.2 μm.In addition, IEEE
（IEEE）An author is disclosed for T.Toyoshima et al., entitled " 0.1um Level in September, 1998
Contact Hole Pattern Formation with KrF Lithography by Chemical Shrink
（RELACS）" article, this article also describes the usual occupation mode of the RELACS material.
As shown in figure 3, after forming the RELACS material layer 4 shown in Fig. 2, carrying out mixing baking（mixing bake）,
The surface of photoetching offset plate figure 3 forms cross-linked layer 4a, i.e. cross-linked layer 4a and is covered on the top of photoetching offset plate figure 3 and side wall.
Contain light acid molecule in photoresist layer, after photoresist layer is through overexposure, developing procedure, due to the developer solution meeting of alkalescence
Light acid molecule with the edge of photoetching offset plate figure 3 produces neutralization so that under the light acid molecule concentration at the edge of photoetching offset plate figure 3
Drop, is carried out after mixing baking to RELACS material layer 4, and the light acid molecule remained in photoetching offset plate figure 3 is produced because of being heated
Raw diffusion motion, can simultaneously produce new light acid molecule during diffusion, and these light acid molecules can diffuse into RELACS
In material layer 4, and then the cross-linking reaction of RELACS material is catalyzed, the cross-linking reaction causes that the surface of photoetching offset plate figure 3 is formed
Width of the thickness of cross-linked layer 4a, cross-linked layer 4a less than photoetching offset plate figure 3.
Carry out after mixing baking, removal does not crosslink the RELACS material layer of reaction, obtains knot as shown in Figure 4
Structure.
As shown in figure 5, carrying out back carving to the cross-linked layer 4a shown in Fig. 4（etch back）, until expose photoetching offset plate figure 3,
The remaining cross-linked layer positioned at the both sides of photoetching offset plate figure 3 forms side wall 5.
As shown in fig. 6, the photoetching offset plate figure 3 shown in removal Fig. 5, the side wall 5 on bottom antireflective coating 2（At least four
It is individual, in figure as a example by eight）There is interval each other.Compare Fig. 1 and Fig. 6 to understand, using self-alignment duplex pattern method
The density of formed figure is the twice of the density that photoetching offset plate figure 3 is formed using photoetching process, and utilizes autoregistration dual
The characteristic size that graphic method forms figure is less than the characteristic size that photoetching offset plate figure 3 is formed using photoetching process.
Formed side wall 5 after, can with side wall 5 be mask to the corresponding conductive layer in Semiconductor substrate 1, semiconductor layer or absolutely
Edge layer is performed etching, to form the figure for intentionally getting, such as polysilicon gate（poly gage）Deng.
The Etching profile of etched features be weigh etching effect one of important parameter, so-called Etching profile refer to by
The sidewall shape of etched features, for the making of small line width figure submicron component, obtains anisotropic etching degree high
Etched features it is extremely important.Therefore, etched features are the Etching profile of side wall 5（The sidewall shape of side wall 5）Can directly affect
The Etching profile for obtaining figure is performed etching to equivalent layer in Semiconductor substrate 1 by mask with side wall 5.
As can be seen here, obtain verticality of side wall side wall 5 high extremely important, but, in practical semiconductor processing procedure due to
The influence of many factors, the side wall of side wall 5 is not fully vertical, using sweep electron microscope（FE-SEM）To using above-mentioned
Self-alignment duplex pattern method obtain the i.e. side wall 5 of figure sidewall profile detected after find, the sidewall profile of side wall 5
As shown in fig. 7, as seen from the figure, the perpendicularity of side wall 5 is unsatisfactory.
In addition, finding the lower section of side wall 5 afterwards to form side wall 5 as shown in figure 5, to cross-linked layer 4a shown in Fig. 4 carve
Bottom antireflective coating 2 also can by excessive etching, therefore, it is two neighboring when the thinner thickness of bottom antireflective coating 2
Bottom antireflective coating 2 between side wall 5 may be cut through, and cause the Semiconductor substrate 1 of the lower section of bottom antireflective coating 2 to be received
To damage.
The content of the invention
The problem to be solved in the present invention is that existing self-alignment duplex pattern method obtains the verticality of side wall of figure not
It is high.
To solve the above problems, the invention provides a kind of autoregistration multiple patterning methods, it includes：
Semiconductor substrate is provided, a photoetching offset plate figure is at least formed on the semiconductor substrate；
Siliceous RELACS material layer is formed in the Semiconductor substrate and photoetching offset plate figure；
Mixing baking is carried out, the siliceous RELACS material layer contacted with the photoetching offset plate figure crosslinks reaction, and
Cross-linked layer is formed on the photoetching offset plate figure surface；
Remove the cross-linked layer on photoetching offset plate figure top, do not crosslink reaction siliceous RELACS material layer and
Photoetching offset plate figure, remaining cross-linked layer forms side wall.
Alternatively, the photoetching offset plate figure is made of using positive photoresist.
Alternatively, the siliceous RELACS material layer is formed using the method for spin coating.
Alternatively, the temperature that the mixing is bakeed is 60 DEG C -300 DEG C, and the time is 30s-300s.
Alternatively, remove the cross-linked layer on the photoetching offset plate figure top, do not crosslink the siliceous RELACS of reaction
The step of material layer and photoetching offset plate figure, includes：
Removal does not crosslink the siliceous RELACS material layer of reaction, to expose the cross-linked layer；
The cross-linked layer carve up to exposing the photoetching offset plate figure, it is remaining positioned at the photoetching offset plate figure two
The cross-linked layer of side forms side wall；
Remove the photoetching offset plate figure.
Alternatively, the siliceous RELACS material layer of reaction is not crosslinked using developer solution removal.
Alternatively, the developer solution is the TMAH aqueous solution.
Alternatively, carving used etching gas described time at least includes CO2、O2、N2、H2、CF4、Cl2In one kind.
Alternatively, the photoetching offset plate figure is removed using developer solution.
Alternatively, the developer solution is the TMAH aqueous solution.
Alternatively, before the photoetching offset plate figure being formed on the semiconductor substrate, shape on the semiconductor substrate
Into bottom antireflective coating.
Alternatively, also include after the formation side wall：The bottom antireflective coating is entered by mask of the side wall
Row etching, forms bottom antireflective coating figure.
Alternatively, remove the cross-linked layer on the photoetching offset plate figure top, do not crosslink the siliceous RELACS of reaction
The step of material layer and photoetching offset plate figure, includes：
Siliceous RELACS material layer and cross-linked layer to not crosslinking reaction carve, until exposing the photoetching
Glue pattern, the remaining cross-linked layer positioned at the photoetching offset plate figure both sides forms side wall；
Removal does not crosslink the siliceous RELACS material layer and the photoetching offset plate figure of reaction.
Alternatively, carving used etching gas described time at least includes CO2、O2、N2、H2、CF4、Cl2In one kind.
Alternatively, the siliceous RELACS material layer and the photoresist figure of reaction is not crosslinked using developer solution removal
Shape.
Alternatively, the developer solution is the TMAH aqueous solution.
Alternatively, before the photoetching offset plate figure being formed on the semiconductor substrate, shape on the semiconductor substrate
Into bottom antireflective coating.
Alternatively, also include after the formation side wall：The bottom antireflective coating is entered by mask of the side wall
Row etching, forms bottom antireflective coating figure.
Alternatively, also include after formation bottom antireflective coating figure：
The side wall is removed, amorphous carbon layer is formed in the Semiconductor substrate and bottom antireflective coating figure；
The amorphous carbon layer is carried out back to carve, it is remaining positioned at the amorphous of the bottom antireflective coating figure both sides
Carbon-coating forms side wall；
Remove the bottom antireflective coating figure.
In addition, present invention also offers a kind of silicon substrate hard mask compositions as RELACS material application.
Compared with prior art, the present invention has advantages below：
Autoregistration multiple patterning methods provided by the present invention employ a kind of silicon substrate hard mask compositions and are used as
RELACS material, is formed after photoetching offset plate figure on a semiconductor substrate, and this siliceous RELACS material is covered in into photoetching
On glue pattern, then carry out mixing baking, mix bakee in the presence of promote to be contacted with photoetching offset plate figure it is siliceous
RELACS material crosslinks reaction, so as to form cross-linked layer on the surface of photoetching offset plate figure, then removes photoetching offset plate figure top
The cross-linked layer in portion, the siliceous RELACS material and photoetching offset plate figure for not crosslinking reaction, remaining cross-linked layer form side wall,
In subsequent process steps can with side wall be mask transferring the graphic in Semiconductor substrate, the figure that formation intentionally gets.
Compared with the self-alignment duplex pattern method realized using existing RELACS material, the present invention utilizes this siliceous RELACS
The autoregistration multiple patterning methods that material layer is realized can solve existing self-alignment duplex pattern method and obtain figure
Verticality of side wall problem not high.
Further, when photoetching offset plate figure bottom antireflective coating formed below, the present invention is using this siliceous
The autoregistration multiple patterning methods that RELACS material layer is realized can solve existing self-alignment duplex pattern method midsole
Portion's ARC can be by excessive etching, so that what the Semiconductor substrate below bottom antireflective coating may sustain damage
Problem.
Further, after the rectangular side wall in top is formed using cross-linked layer, can with side wall as mask aligning in
Bottom antireflective coating below is performed etching, to transfer the graphic on bottom antireflective coating, after removal side wall,
One layer of amorphous carbon layer is formed in Semiconductor substrate and bottom antireflective coating figure, after to the amorphous carbon layer carve
Side wall can be formed in the both sides of bottom antireflective coating figure, the side wall density being made up of amorphous carbon layer is photoetching offset plate figure
Three times of density, it is thus achieved that the triple graphic methods of autoregistration, it is achieved thereby that smaller lithographic feature size, promotes
The development of photoetching technique.
Brief description of the drawings
Fig. 1 to Fig. 6 is that the making for forming figure on a semiconductor substrate using existing self-alignment duplex pattern method is shown
It is intended to；
Fig. 7 is the enlarged drawing that figure is obtained using existing self-alignment duplex pattern method；
Fig. 8 is the Making programme figure of autoregistration multiple patterning methods in embodiments of the present invention one；
Fig. 9 to Figure 16 be in embodiments of the present invention one using autoregistration multiple patterning methods on a semiconductor substrate
The making schematic diagram of figure is formed, wherein, Figure 14 is that existing self-alignment duplex pattern method forms side wall with the present invention certainly
Alignment multiple patterning methods form the verticality of side wall comparison schematic diagram of side wall；
Figure 17 to Figure 22 is in Semiconductor substrate in embodiments of the present invention two using autoregistration multiple patterning methods
The upper making schematic diagram for forming figure；
Figure 23 to Figure 25 is in Semiconductor substrate in embodiments of the present invention three using autoregistration multiple patterning methods
The upper making schematic diagram for forming figure.
Specific embodiment
Below in conjunction with the accompanying drawings, by specific embodiment, clear, complete description is carried out to technical scheme, is shown
So, described embodiment is only a part for embodiment of the invention, rather than its whole.According to these implementations
Example, one of ordinary skill in the art's obtainable all other implementation method on the premise of without creative work all belongs to
In protection scope of the present invention.
In the disclosure of on November 4th, 2010, Publication No. US20100279509A1, entitled " silicon-based
hardmask composition and process of producing semiconductor integrated
The United States Patent (USP) of circuit device using the same " discloses a kind of silicon substrate hard mask compositions（silicon-
based hardmask composition）, and one kind the integrated electricity of semiconductor is made using the silicon substrate hard mask compositions
The process on road.Mention the silicon substrate hard mask compositions in that patent and have that surface hydrophilicity is high, antireflective property strong,
The advantages of storage endurance ability is good, therefore propose one kind on this basis and make semiconductor collection using the silicon substrate hard mask compositions
Into the process of circuit, the method sequentially forms carbon-based hard mask from the bottom to top on a semiconductor substrate（carbon-based
hardmask）, the silicon substrate hard mask that is made using silicon substrate hard mask compositions（silicon-based hardmask）, photoresist
Layer, is then exposed to photoresist layer, develops, and forms photoetching offset plate figure, is transferred the graphic to by mask of photoetching offset plate figure
In silicon substrate hard mask, then transfer the graphic in carbon-based hard mask, finally transfer the graphic in Semiconductor substrate.By profit
The photoetching offset plate figure of very thin thickness can be successfully transferred in Semiconductor substrate with silicon substrate hard mask compositions.
Inventor has found that the silicon substrate hard mask compositions in above-mentioned patent, will except can be used to be made silicon substrate hard mask
Outside the photoetching offset plate figure of very thin thickness is successfully transferred in Semiconductor substrate, the silicon substrate hard mask compositions are further substituted
The existing RELACS material being previously mentioned in foregoing Background is utilized this siliceous as a kind of new RELACS material
The autoregistration multiple patterning methods that RELACS material layer is realized can solve existing self-alignment duplex pattern method and be obtained
The verticality of side wall for obtaining figure is not high, and bottom antireflective coating can be excessive in existing self-alignment duplex pattern method
Etching, so that the problem that the Semiconductor substrate below bottom antireflective coating may sustain damage, below by three kinds of implementations
Mode is described in detail to technical scheme.
Implementation method one
Fig. 8 is the Making programme figure of autoregistration multiple patterning methods in embodiments of the present invention one, as shown in figure 8,
The method includes：
Step S1：Semiconductor substrate is provided, photoetching offset plate figure is formed on a semiconductor substrate.
Step S2：Siliceous RELACS material layer is formed in Semiconductor substrate and photoetching offset plate figure.
Step S3：Mixing baking is carried out, cross-linked layer is formed on photoetching offset plate figure surface.
Step S4：Removal does not crosslink the siliceous RELACS material layer of reaction, to expose cross-linked layer.
Step S5：Cross-linked layer is carried out back to carve until exposing photoetching offset plate figure.
Step S6：Removal photoetching offset plate figure, remaining cross-linked layer forms side wall.
Fig. 9 to Figure 15 be in embodiments of the present invention one using autoregistration multiple patterning methods on a semiconductor substrate
The making schematic diagram of figure is formed, the technical scheme of embodiment of the present invention one is carried out specifically with reference to Fig. 8 to Figure 15
It is bright.
As shown in Figure 9, there is provided Semiconductor substrate 10, a photoetching offset plate figure 30 is at least formed over the semiconductor substrate 10,
In figure by taking four photoetching offset plate figures 30 as an example.Specifically, photoresist layer can over the semiconductor substrate 10 be formed（It is not shown）, then
The photoresist layer is exposed, is developed, to form photoetching offset plate figure 30 over the semiconductor substrate 10.Due to positive photoresist
With preferable analytic ability, the less figure of critical size, in one embodiment, photoresist can be formed on photoresist layer
Figure 30 is made using positive photoresist.Semiconductor substrate 10 is included by autoregistration multiple patterning methods energy shape of the invention
Into the equivalent layer for wishing figure, the equivalent layer can be conductive layer, semiconductor layer or insulating barrier, as one of example,
Semiconductor substrate 10 includes polysilicon layer, and figure can be carried out to the polysilicon layer using autoregistration multiple patterning methods of the invention
Shapeization treatment, to form polysilicon gate.
In one embodiment, when being exposed to the photoresist layer, in order to reduce in exposed photoresist layer
Reflection, bottom antireflective coating is initially formed before the photoresist layer is formed over the semiconductor substrate 10（BARC）20, so may be used
With cause photoetching offset plate figure 30 sidewall profile more preferably.
As shown in Figure 10, one layer of siliceous RELACS material layer is formed in Semiconductor substrate 10 and photoetching offset plate figure 30
40, siliceous RELACS material layer 40 covers the surface of photoetching offset plate figure 30.Siliceous RELACS material layer 40 is to utilize
The disclosed above number silicon substrate hard mask compositions disclosed in the United States Patent (USP) of US20100279509A1 are made.As a tool
The embodiment of body, siliceous RELACS material layer 40 is formed using spin-coating method.Resist when bottom is formed with Semiconductor substrate 10
During reflectance coating 20, siliceous RELACS material layer 40 is covered on bottom antireflective coating 20 and photoetching offset plate figure 30.
As shown in figure 11, mixing baking is carried out（mixing bake）, in the presence of baking is mixed, remain in photoresist
Light acid molecule in figure 30 produces diffusion motion because of being heated, and new light acid point can be simultaneously produced during diffusion
Son, these light acid molecules can be diffused into the siliceous RELACS material layer 40 contacted with photoetching offset plate figure 30, and then are catalyzed
The cross-linking reaction of the siliceous RELACS material layer 40 contacted with photoetching offset plate figure 30, the cross-linking reaction causes photoetching offset plate figure
30 surface forms cross-linked layer 41, in other words, cross-linked layer 41 is all covered with the top of photoetching offset plate figure 30 and side wall.By in figure
Understand, the width w of the thickness h less than photoetching offset plate figure 30 of cross-linked layer 41.The thickness h of cross-linked layer 41 has with the temperature for mixing baking
Close, when the temperature that mixing is bakeed is higher, the thickness h of cross-linked layer 41 is bigger.Used as a specific embodiment, the mixing is dried
The temperature of roasting is 60 DEG C -300 DEG C, and the time for mixing baking is 30s-300s.
As shown in figure 12, the siliceous RELACS material layer 40 of reaction is not crosslinked in removal Figure 11, to expose crosslinking
Layer 41.In one embodiment, using the siliceous RELACS material layer 40 that reaction is not crosslinked described in developer solution removal, so
Afterwards, bakeed, to remove moisture removal.Used as a specific embodiment, the developer solution can be TMAH（Tetramethyl hydroxide
Ammonium）The aqueous solution, its concentration can be 2.38%（Percent by volume）.
With reference to shown in Figure 12 and Figure 13, cross-linked layer 41 is carried out back to carve, until expose photoetching offset plate figure 30, it is remaining to be located at
The cross-linked layer 41 of the both sides of photoetching offset plate figure 30 forms side wall 42.It can be seen from the etching principle carved is returned, the shape at the top of side wall 42
Similar to arch.As a specific embodiment, carve used etching gas and at least include CO for described time2、O2、N2、H2、
CF4、Cl2In one kind.
Figure 14 is that existing self-alignment duplex pattern method forms side wall and autoregistration multiple patterning methods of the present invention
The verticality of side wall comparison schematic diagram of formed side wall, as shown in figure 14, dotted portion is represented on photoetching offset plate figure surface in figure
Cross-linked layer, double dot dash line part represents that existing self-alignment duplex pattern method forms side wall in figure, bold portion in figure
Represent that autoregistration multiple patterning methods of the present invention form side wall.Inventor is by using sweep electron microscope（FE-
SEM）Sidewall profile to obtaining figure using autoregistration multiple patterning methods of the present invention finds after detecting, and existing
Self-alignment duplex pattern method forms side wall and compares, and the verticality of side wall that the present invention forms side wall is higher, according to invention
The ability domain-dependent knowledge that people is grasped, inventor analyzes its reason should include various, such as siliceous RELACS material layers
Polymer is being carved when selection, the etching of selected etching gas, etching parameters when etch rate, the etching of formed cross-linked layer
The factor such as density distribution uniformity of produced plasma can influence side wall when losing the stackeding speed in pattern side wall, etching
Perpendicularity, wherein, it is as follows that siliceous RELACS material layer forms influence of the etch rate of cross-linked layer to side wall perpendicularity：
To cross-linked layer（Dotted portion in figure）When carve, etching is stopped when photoetching offset plate figure 30 is exposed, and carved in identical
Under the conditions of erosion, the speed ratio that is etched of the cross-linked layer in the present invention produced by the siliceous crosslinked reaction of RELACS material is existing
Cross-linked layer produced by the crosslinked reaction of RELACS material is etched speed faster, in other words, siliceous RELACS material warp
Cross-linked layer produced by cross-linking reaction is big with the etching selection ratio of the cross-linked layer produced by the crosslinked reaction of existing RELACS material
In 1, therefore, when the cross-linked layer thickness on photoetching offset plate figure 30 is equal, present invention etch period ratio required in this step
Etch period needed for existing is shorter, therefore the amount of being removed in the present invention at the top of side wall is less than being removed at the top of existing side wall
Amount, thus the verticality of side wall of side wall of the present invention is higher than the verticality of side wall of existing side wall.
In addition, when bottom antireflective coating 20 is formed with Semiconductor substrate 10, due to siliceous in the present invention
The crosslinked reaction of the existing RELACS material of the speed ratio that is etched of the cross-linked layer produced by the crosslinked reaction of RELACS material is produced
Raw cross-linked layer is etched speed faster, therefore, the friendship in the present invention produced by siliceous RELACS material crosslinked reaction
The etching selection ratio of connection layer and bottom antireflective coating 20, more than the cross-linked layer produced by the crosslinked reaction of existing RELACS material
With the etching selection ratio of bottom antireflective coating, therefore, as shown in figure 13, return form side wall 42 at quarter when, the present invention in bottom
The amount of being etched of ARC 20 is less, therefore the possibility that bottom antireflective coating 20 is cut through is smaller, reduces and half-and-half leads
Body substrate 10 causes the probability for damaging.
As shown in figure 15, the photoetching offset plate figure 30 shown in removal Figure 13, the multiple side walls 42 in Semiconductor substrate 10（In figure
As a example by 8）There is interval each other.In one embodiment, photoetching offset plate figure 30 is removed using developer solution.As one
Specific embodiment, the developer solution is the aqueous solution of TMAH.Compare Figure 15 and Fig. 9 and understand that the density of side wall 42 is photoresist
The twice of the density of figure 30, the spacing being smaller than between two neighboring photoetching offset plate figure 30 between two neighboring side wall 42.
Formed side wall 42 after, can directly with side wall 42 for mask is performed etching to the equivalent layer in Semiconductor substrate 10,
To form the figure for intentionally getting, such as polysilicon gate.When bottom antireflective coating 20 is formed with Semiconductor substrate 10, knot
Close shown in Figure 15 and Figure 16, first with side wall 42 for mask is performed etching to bottom antireflective coating 20, form multiple（With 8 in figure
As a example by individual）Bottom antireflective coating figure 21, then can with bottom antireflective coating figure 21 be mask to Semiconductor substrate 10
On equivalent layer perform etching, to form the figure that intentionally gets（It is not shown）.
From the foregoing, the autoregistration multiple patterning methods in above-mentioned implementation method one are essentially autoregistration double picture
Shape method.
Implementation method two
Figure 17 to Figure 22 is in Semiconductor substrate in embodiments of the present invention two using autoregistration multiple patterning methods
The upper making schematic diagram for forming figure, is carried out in detail with reference to Figure 17 to Figure 22 to the technical scheme of embodiment of the present invention two
Explanation.
As shown in figure 17, there is provided the ＇ of Semiconductor substrate 10, a photoetching offset plate figure is at least formed on the ＇ of Semiconductor substrate 10
30 ＇, in figure by taking four ＇ of photoetching offset plate figure 30 as an example.Specifically, photoresist layer can be formed on the ＇ of Semiconductor substrate 10（Do not scheme
Show）, then the photoresist layer is exposed, is developed, to form the ＇ of photoetching offset plate figure 30 on the ＇ of Semiconductor substrate 10.One
In individual embodiment, the ＇ of photoetching offset plate figure 30 is made using positive photoresist.
In one embodiment, when being exposed to the photoresist layer, in order to reduce in exposed photoresist layer
Reflection, bottom antireflective coating is initially formed before forming the photoresist layer on the ＇ of Semiconductor substrate 10（BARC）20 ＇, so
The sidewall profile of the ＇ of photoetching offset plate figure 30 can be caused more preferably.
As shown in figure 18, one layer of siliceous RELACS material layer is formed on the ＇ of Semiconductor substrate 10 and the ＇ of photoetching offset plate figure 30
40 ＇, siliceous 40 ＇ of RELACS material layer cover the surface of the ＇ of photoetching offset plate figure 30.40 ＇ of siliceous RELACS material layer are
It is made using the disclosed above number silicon substrate hard mask compositions disclosed in the United States Patent (USP) of US20100279509A1.As one
Individual specific embodiment, siliceous 40 ＇ of RELACS material layer are formed using spin-coating method.It is formed with when on the ＇ of Semiconductor substrate 10
During 20 ＇ of bottom antireflective coating, siliceous 40 ＇ of RELACS material layer are covered in the ＇ of bottom antireflective coating 20 and photoetching offset plate figure
On 30 ＇.
As shown in figure 19, mixing baking is carried out（mixing bake）, in the presence of baking is mixed, remain in photoresist
Light acid molecule in the ＇ of figure 30 produces diffusion motion because of being heated, and new light acid point can be simultaneously produced during diffusion
Son, these light acid molecules can be diffused into siliceous 40 ＇ of RELACS material layer contacted with the ＇ of photoetching offset plate figure 30, and then are urged
The cross-linking reaction of siliceous 40 ＇ of RELACS material layer that change is contacted with the ＇ of photoetching offset plate figure 30, the cross-linking reaction causes photoresist
The surface of the ＇ of figure 30 forms the ＇ of cross-linked layer 41, in other words, cross-linked layer is all covered with the top of the ＇ of photoetching offset plate figure 30 and side wall
41 ＇.The thickness h ＇ of the ＇ of cross-linked layer 41 is relevant with the temperature that mixing is bakeed, when the temperature that mixing is bakeed is higher, the ＇'s of cross-linked layer 41
Thickness h ＇ is bigger.Used as a specific embodiment, the temperature that the mixing is bakeed is 60 DEG C -300 DEG C, mixes the time for bakeing
It is 30s-300s.
As shown in figure 20, the RELACS material layer 40 ＇ and ＇ of cross-linked layer 41 shown in Figure 19 carve, until exposing light
The ＇ of photoresist figure 30.After carve, the ＇ of cross-linked layer 41 at the top of the ＇ of photoetching offset plate figure 30 is removed, remaining positioned at photoresist
The ＇ of cross-linked layer 41 of the ＇ both sides of figure 30 forms the ＇ of side wall 42, the ＇ of two neighboring side wall 42（This two side walls are respectively formed at does not share the same light
On the side wall of the ＇ of photoresist figure 30）Between filled with do not crosslink reaction RELACS material layer 40 ＇.It is specific as one
Embodiment, returns and carves used etching gas at least including CO2、O2、N2、H2、CF4、Cl2In one kind.
With reference to shown in Figure 20 and Figure 21, remove the ＇ of photoetching offset plate figure 30 and do not crosslink the RELACS material layer of reaction
, there is interval between multiple ＇ of side wall 42 on the ＇ of Semiconductor substrate 10 in 40 ＇.In one embodiment, removed using developer solution
The ＇ of photoetching offset plate figure 30 and do not crosslink reaction RELACS material layer 40 ＇.As a specific embodiment, the development
Liquid is the aqueous solution of TMAH.
Compare Figure 21 and Figure 17 to understand, due to the forming method of the ＇ of side wall 42 in present embodiment and side in implementation method one
The forming method of wall 42 is simultaneously differed, and causes the shape and side wall 42 in implementation method one of the ＇ of side wall 42 in present embodiment（Control
Shown in Figure 15）Shape it is otherwise varied：The top of side wall 42 is arched in implementation method one, and the ＇ of side wall 42 in present embodiment
Top will not be etched, therefore rectangular, reason is as follows：When to the RELACS material layer 40 ＇ and ＇ of cross-linked layer 41 carve,
Stop etching when 30 ＇ of photoetching offset plate figure is exposed, and the ＇ of cross-linked layer 41 of the ＇ of photoetching offset plate figure 30 is higher by during etching stopping same
Time is etched, therefore the end of the ＇ of side wall 42 will not be etched, therefore the end of the ＇ of side wall 42 is rectangular.
In addition, the ＇ thickness of cross-linked layer 41 that crosslinked reaction is formed is uniform（When the baking of 40 ＇ of RELACS material layer
Between it is more long as 30s-300s when may insure that the ＇ thickness of cross-linked layer 41 is uniform）, therefore the perpendicularity of the ＇ of side wall 42 is very high, thus
Compared with existing self-alignment duplex pattern method forms side wall, the side wall that embodiment of the present invention two forms side wall is vertical
Du Genggao.
Further, inventor utilizes sweep electron microscope（FE-SEM）To being carried using embodiment of the present invention two
It is provided from being directed at multiple patterning methods and obtains the sidewall profile of the i.e. ＇ of side wall 42 of figure and detected that testing result is also demonstrated that
The perpendicularity of the ＇ of side wall 42 is higher.
When 20 ＇ of bottom antireflective coating is formed with the ＇ of Semiconductor substrate 10, as shown in figure 20, side wall is formed at quarter returning
Because the ＇ of bottom antireflective coating 20 is covered by 40 ＇ of RELACS material layer during 42 ＇, therefore bottom antireflective coating in the present invention
20 ＇ will not be etched, thus the ＇ of Semiconductor substrate 10 will not be caused to damage.
Compare Figure 21 and Figure 17 and understand that the density of the ＇ of side wall 42 is the twice of the ＇ density of photoetching offset plate figure 30, two neighboring side
The spacing being smaller than between the ＇ of two neighboring photoetching offset plate figure 30 between the ＇ of wall 42.
Formed after the ＇ of side wall 42, the equivalent layer on the ＇ of Semiconductor substrate 10 can be carved by mask of the ＇ of side wall 42 directly
Erosion, to form the figure for intentionally getting, such as polysilicon gate.
When 20 ＇ of bottom antireflective coating is formed with the ＇ of Semiconductor substrate 10, with reference to shown in Figure 21 and Figure 22, first with side
The ＇ of wall 42 is performed etching for mask to the ＇ of bottom antireflective coating 20, forms multiple（In figure as a example by 8）Bottom antireflective coating
The ＇ of figure 21, then can perform etching by mask of the ＇ of bottom antireflective coating figure 21 to the equivalent layer on the ＇ of Semiconductor substrate 10,
To form the figure for intentionally getting（It is not shown）.
As shown in the above, the autoregistration multiple patterning methods in above-mentioned implementation method two are essentially autoregistration pair
Weight graphic method.
Implementation method three
When being formed with the ＇ of bottom antireflective coating 20 on the ＇ of Semiconductor substrate 10, and it is formed with multiple bottom antireflective coating figures
During 21 ＇ of shape, on the basis of implementation method two, as shown in figure 23, the ＇ of side wall 42 shown in removal Figure 22 continues in semiconductor lining
Amorphous carbon is formed on the ＇ of bottom 10 and the ＇ of bottom antireflective coating figure 21（amorpous carbon）Layer 50, amorphous carbon layer 50
The top of the ＇ of bottom antireflective coating figure 21 and side wall are covered.
As shown in figure 24, the amorphous carbon layer 50 shown in Figure 23 is carried out back carving, until exposing bottom antireflective coating figure
The ＇ of shape 21, the remaining amorphous carbon layer 50 positioned at the ＇ both sides of bottom antireflective coating figure 21 constitutes side wall 51.
As shown in figure 25, the ＇ of bottom antireflective coating figure 21 shown in removal Figure 24, multiple side walls 51 exist each other
Interval.
Compare Figure 25 and understand that the density of side wall 51 is the two of the ＇ density of side wall 42 on the ＇ of Semiconductor substrate 10 with Figure 21, Figure 17
Times, the density of side wall 51 is three times of the ＇ of photoetching offset plate figure 30.Thus, the autoregistration multiple patterning methods in present embodiment
It is essentially autoregistration triple graphical（Self-aligned Triple Double Patterning, abbreviation SATP）Method.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to more fully understand the present invention, and can
Reproduce and use the present invention.Those skilled in the art according to principle specifically described herein can not depart from it is of the invention
To above-described embodiment as various changes and modifications it is obvious in the case of spirit and scope.Therefore, the present invention should not be by
It is interpreted as being limited to above-described embodiment shown in this article, its protection domain should be defined by appending claims.
Claims (14)
1. a kind of autoregistration multiple patterning methods, it is characterised in that including：
Semiconductor substrate is provided, bottom antireflective coating is formed on the semiconductor substrate；
A photoetching offset plate figure is at least formed on the semiconductor substrate；
Siliceous RELACS material layer, the siliceous RELACS material are formed in the Semiconductor substrate and photoetching offset plate figure
Layer is silicon substrate hard mask compositions, and the silicon substrate hard mask compositions include organosilane polymer and solvent, the organosilicon
Alkane polymer is expressed as { (SiO1.5-Y-SiO1.5)x(R3SiO1.5)y(XSiO1.5)z}(OH)e(OR6)f；
Mixing baking is carried out, the siliceous RELACS material layer contacted with the photoetching offset plate figure crosslinks reaction, and in institute
State photoetching offset plate figure surface and form cross-linked layer, the temperature that the mixing is bakeed is 60 DEG C -300 DEG C, and the time is 30s-300s；
Remove the cross-linked layer on photoetching offset plate figure top, do not crosslink reaction siliceous RELACS material layer and photoetching
Glue pattern, remaining cross-linked layer forms side wall；
The bottom antireflective coating is performed etching by mask of the side wall, forms bottom antireflective coating figure.
2. autoregistration multiple patterning methods according to claim 1, it is characterised in that the photoetching offset plate figure is to utilize
Positive photoresist is made.
3. autoregistration multiple patterning methods according to claim 1, it is characterised in that form institute using the method for spin coating
State siliceous RELACS material layer.
4. autoregistration multiple patterning methods according to claim 1, it is characterised in that the removal photoetching offset plate figure top
Cross-linked layer in portion, include the step of do not crosslink siliceous the RELACS material layer and photoetching offset plate figure of reaction：
Removal does not crosslink the siliceous RELACS material layer of reaction, to expose the cross-linked layer；
The cross-linked layer carve until expose the photoetching offset plate figure, it is remaining positioned at the photoetching offset plate figure both sides
Cross-linked layer forms side wall；
Remove the photoetching offset plate figure.
5. autoregistration multiple patterning methods according to claim 4, it is characterised in that do not occur using developer solution removal
The siliceous RELACS material layer of cross-linking reaction.
6. autoregistration multiple patterning methods according to claim 5, it is characterised in that the developer solution is that TMAH is water-soluble
Liquid.
7. autoregistration multiple patterning methods according to claim 4, it is characterised in that carve used etching described time
Gas at least includes CO2、O2、N2、H2、CF4、Cl2In one kind.
8. autoregistration multiple patterning methods according to claim 4, it is characterised in that remove the light using developer solution
Photoresist figure.
9. autoregistration multiple patterning methods according to claim 8, it is characterised in that the developer solution is that TMAH is water-soluble
Liquid.
10. autoregistration multiple patterning methods according to claim 1, it is characterised in that the removal photoetching offset plate figure
Cross-linked layer on top, include the step of do not crosslink siliceous the RELACS material layer and photoetching offset plate figure of reaction：
Siliceous RELACS material layer and cross-linked layer to not crosslinking reaction carve, until exposing the photoresist figure
Shape, the remaining cross-linked layer positioned at the photoetching offset plate figure both sides forms side wall；
Removal does not crosslink the siliceous RELACS material layer and the photoetching offset plate figure of reaction.
11. autoregistration multiple patterning methods according to claim 10, it is characterised in that carve used quarter described time
Erosion gas at least includes CO2、O2、N2、H2、CF4、Cl2In one kind.
12. autoregistration multiple patterning methods according to claim 10, it is characterised in that do not sent out using developer solution removal
The siliceous RELACS material layer and the photoetching offset plate figure of raw cross-linking reaction.
13. autoregistration multiple patterning methods according to claim 12, it is characterised in that the developer solution is TMAH water
Solution.
14. autoregistration multiple patterning methods according to claim 10, it is characterised in that form bottom antireflective coating
Also include after figure：
The side wall is removed, amorphous carbon layer is formed in the Semiconductor substrate and bottom antireflective coating figure；
The amorphous carbon layer is carried out back to carve, the remaining amorphous carbon layer positioned at the bottom antireflective coating figure both sides
Form side wall；
Remove the bottom antireflective coating figure.
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| CN103871846B (en) * | 2012-12-18 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The application of autoregistration multiple patterning methods and silicon substrate hard mask compositions |
| CN105988284B (en) * | 2015-02-04 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Double patterned methods of exposure mask autoregistration |
| KR102564551B1 (en) * | 2016-01-26 | 2023-08-04 | 삼성전자주식회사 | Method for manufacturing the semiconductor device |
| CN107785242B (en) * | 2016-08-31 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | Triple patterning method |
| CN112462580A (en) * | 2019-09-09 | 2021-03-09 | 芯恩（青岛）集成电路有限公司 | Method for manufacturing quadruple pattern |
| CN112951719B (en) * | 2019-11-26 | 2024-07-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113314400A (en) | 2020-02-27 | 2021-08-27 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113327842A (en) * | 2020-02-28 | 2021-08-31 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116504610B (en) * | 2023-06-21 | 2023-11-17 | 长鑫存储技术有限公司 | Mask structure, pattern forming method and preparation method of semiconductor structure |
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| US6383952B1 (en) * | 2001-02-28 | 2002-05-07 | Advanced Micro Devices, Inc. | RELACS process to double the frequency or pitch of small feature formation |
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| CN101226335A (en) * | 2006-08-17 | 2008-07-23 | 富士通株式会社 | Method for forming resist pattern, semiconductor device and production method thereof |
| CN103871846A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Self-alignment multiple patterning method and application of silicon-based hard mask composition |
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| US6383952B1 (en) * | 2001-02-28 | 2002-05-07 | Advanced Micro Devices, Inc. | RELACS process to double the frequency or pitch of small feature formation |
| CN1802606A (en) * | 2001-08-10 | 2006-07-12 | 富士通株式会社 | Resist pattern swelling material, and method for patterning using same |
| CN101226335A (en) * | 2006-08-17 | 2008-07-23 | 富士通株式会社 | Method for forming resist pattern, semiconductor device and production method thereof |
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