CN103871846A - Self-alignment multiple patterning method and application of silicon-based hard mask composition - Google Patents
Self-alignment multiple patterning method and application of silicon-based hard mask composition Download PDFInfo
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- CN103871846A CN103871846A CN201210553343.1A CN201210553343A CN103871846A CN 103871846 A CN103871846 A CN 103871846A CN 201210553343 A CN201210553343 A CN 201210553343A CN 103871846 A CN103871846 A CN 103871846A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
Abstract
The invention discloses a self-alignment multiple patterning method and an application of a silicon-based hard mask composition. The method adopts the silicon-based hard mask composition as an RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) material; after a photoresist pattern is formed on a semiconductor substrate, the RELACS material containing silicon covers the photoresist pattern and then is mixed and baked, so that a cross-linking layer is formed on the surface of the photoresist pattern; then a side wall is formed by using the cross-linking layer; in a follow-up technical step, the side wall can be used as a mask to transfer the pattern on the semiconductor substrate, so as to form an expected pattern. Compared with an existing self-alignment double patterning method using the RELACS material, the problems that the perpendicularity of the side wall of the pattern obtained by the existing self-alignment double patterning method is not high, a bottom anti-reflection coating in the existing self-alignment double patterning method is excessively corroded, and the semiconductor substrate below the bottom anti-reflection coating may be damaged can be solved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the application of a kind of silica-based hard mask compositions as RELACS material, and utilize this silica-based hard mask compositions to realize the method for autoregistration multiple graphics.
Background technology
Along with constantly dwindling of dimensions of semiconductor devices, lithographic feature size moves closer to the physics limit that has even exceeded optical lithography, has proposed stern challenge more thus to semiconductor fabrication especially photoetching technique.Extreme ultraviolet (EUV) photoetching technique possesses less photoetching resolution, but can not realize dwindling of lithographic feature size for various reasons, therefore needs to continue to expand photoetching technique.By means of more extreme resolution enhance technology (RET), as powerful phase shifting mask (PSM) technology, various lighting technology and optical approach effect correction (OPC) technology etc., can further expand photoetching technique.In addition, immersion lithography, by fill certain liquid between projection objective and photoresist, has effectively increased the numerical aperture (NA) of etching system, thereby has realized less lithographic feature size, has promoted the development of photoetching technique.
In addition, double-pattern (double patterning is called for short DP) technology, not changing under the prerequisite of existing photoetching infrastructure, has also promoted the development of photoetching technique as a kind of technology of effective raising photoetching resolution.The basic thought of this technology is that mask graph is divided into two, and obtains the not obtainable lithographic feature size limit of single exposure by double exposure, has also extended greatly the useful life of existing lithographic equipment simultaneously, is therefore widely used.The basic implementation method of double-pattern technology comprises LELE(Litho-Etch-Litho-Etch, exposure-etching-exposure-etching) double-pattern method, LFLE(Litho-Freeze-Litho-Etch, expose-solidify-exposure-etching) Double-patterning method and autoregistration Dual graphing (Self-aligned Double patterning is called for short SADP) method.Wherein, autoregistration Double-patterning method is by forming side wall (spacer) in preformed litho pattern both sides, then the litho pattern that etching forms before removing, and by side wall graph transfer printing to subsurface material, thereby obtain the figure that characteristic size is less, and the pattern density obtaining be before the twice of litho pattern density.
, publication number open on May 7th, 2002 is that the United States Patent (USP) that US6383952B1, name are called " RELACS processto double the frequency or pitch of small feature formation " discloses a kind of autoregistration Double-patterning method, below in conjunction with Fig. 1 to Fig. 5, this method is briefly described:
As shown in Figure 1, provide Semiconductor substrate 1, in Semiconductor substrate 1, form photoresist layer (not shown), described photoresist layer is exposed, developed, form multiple (be at least two, in figure taking four as example) photoetching offset plate figure 3 parallel and spaced apart.In order to reduce the reflection when the exposed photoresist layer, first form bottom antireflective coating (BARC) 2 form described photoresist layer in Semiconductor substrate 1 before, can make like this sidewall pattern of photoetching offset plate figure 3 better.
As shown in Figure 2, on bottom antireflective coating 2 and photoetching offset plate figure 3, form RELACS(resolution enhancement lithography assisted by chemical shrink, chemical shrinkage-assisted analysis strengthens) material layer 4, RELACS material layer 4 is by the surface of photoetching offset plate figure 3, and the top of photoetching offset plate figure 3 and sidewall all cover.
Described RELACS material is a kind of organic material can be applicable in field of semiconductor manufacture that Clariant (Clariant) company develops, for example, it is Laura J.Peters that magazine " the semiconductor world " (" Semiconductor International ") discloses one section of author in September, 1999, exercise question is the article of " Resists Join the Sub-Lambda Revolution ", this article has been described a kind of semiconductor technology being proposed by Mitsubishi, this technique graphical for after defining the KrF photoresist layer of lead to the hole site, by forming described RELACS material, cure (bake), the processing step that cleans (rinse) is reduced to 0.1 μ m by the size of through hole by 0.2 μ m.In addition, IEEE (IEEE) discloses in September, 1998 article that one section of author is " 0.1um Level Contact Hole Pattern Formation with KrF Lithography by Chemical Shrink(RELACS) " for T.Toyoshima et al., exercise question, and this article has also been introduced the usual occupation mode of described RELACS material.
As shown in Figure 3, after forming the RELACS material layer 4 shown in Fig. 2, mix and cure (mixing bake), form cross-linked layer 4a on the surface of photoetching offset plate figure 3, cross-linked layer 4a covers on the top and sidewall of photoetching offset plate figure 3.
In photoresist layer, contain light acid molecule, photoresist layer is through overexposure, after developing procedure, because alkaline developer solution can produce neutralization with the light acid molecule at photoetching offset plate figure 3 edges, the light acid molecule concentration at photoetching offset plate figure 3 edges is declined, after RELACS material layer 4 is mixed and is cured, remain in the light acid molecule in photoetching offset plate figure 3 and produce diffusion motion because be heated, in the process of diffusion, can produce new light acid molecule simultaneously, these light acid molecules can diffuse in RELACS material layer 4, and then the cross-linking reaction of catalysis RELACS material, described cross-linking reaction makes the surface of photoetching offset plate figure 3 form cross-linked layer 4a, the thickness of cross-linked layer 4a is less than the width of photoetching offset plate figure 3.
After mixing and curing, remove the RELACS material layer that cross-linking reaction does not occur, obtain structure as shown in Figure 4.
As shown in Figure 5, the cross-linked layer 4a shown in Fig. 4 is returned to quarter (etch back), until expose photoetching offset plate figure 3, the remaining cross-linked layer that is positioned at photoetching offset plate figure 3 both sides forms side wall 5.
As shown in Figure 6, remove the photoetching offset plate figure 3 shown in Fig. 5, the side wall 5(on bottom antireflective coating 2 is at least four, in figure taking eight as example) there is each other interval.Comparison diagram 1 is known with Fig. 6, the density of utilizing autoregistration figure that Double-patterning method forms is to utilize the twice of the density of photoetching offset plate figure that photoetching process forms 3, and utilizes the characteristic size of autoregistration figure that Double-patterning method forms to be less than the characteristic size of utilizing photoetching offset plate figure that photoetching process forms 3.
Form after side wall 5, can carry out etching for mask to corresponding conductive layer, semiconductor layer or insulating barrier in Semiconductor substrate 1 by side wall 5, the figure obtaining to form hope, as polysilicon gate (poly gage) etc.
The Etching profile of etching figure is one of them important parameter of weighing etching effect, so-called Etching profile refers to the sidewall shape of the figure that is etched, for the making of little live width figure submicron component, obtain the etching figure that anisotropic etching degree is high extremely important.Therefore, etching figure be side wall 5 Etching profile (sidewall shape of side wall 5) directly impact equivalent layer in Semiconductor substrate 1 is carried out to the Etching profile of figure that etching is obtained with side wall 5 for mask.
As can be seen here, obtain the side wall 5 that verticality of side wall is high extremely important, but, in practical semiconductor processing procedure due to the impact of many factors, the sidewall of side wall 5 is also not exclusively vertical, utilizes sweep electron microscope (FE-SEM) to utilizing the sidewall pattern that above-mentioned autoregistration figure that Double-patterning method obtains is side wall 5 to detect rear discovery, and the sidewall pattern of side wall 5 as shown in Figure 7, as seen from the figure, the perpendicularity of side wall 5 is unsatisfactory.
In addition, as shown in Figure 5, the 4a of cross-linked layer shown in Fig. 4 is returned to carve after forming side wall 5 and find that the bottom antireflective coating 2 of side wall 5 belows also can be by too much etching, therefore, in the time of the thinner thickness of bottom antireflective coating 2, bottom antireflective coating 2 between adjacent two side walls 5 may be worn by quarter, caused the Semiconductor substrate 1 of bottom antireflective coating 2 belows to sustain damage.
Summary of the invention
The problem to be solved in the present invention is that the verticality of side wall of existing autoregistration figure that Double-patterning method obtains is not high.
For addressing the above problem, the invention provides a kind of autoregistration multiple patterning methods, it comprises:
Semiconductor substrate is provided, in described Semiconductor substrate, at least forms a photoetching offset plate figure;
On described Semiconductor substrate and photoetching offset plate figure, form siliceous RELACS material layer;
Mix and cure, the siliceous RELACS material layer generation cross-linking reaction contacting with described photoetching offset plate figure, and form cross-linked layer on described photoetching offset plate figure surface;
Remove cross-linked layer on described photoetching offset plate figure top, siliceous RELACS material layer and the photoetching offset plate figure of cross-linking reaction do not occur, remaining cross-linked layer forms side wall.
Alternatively, described photoetching offset plate figure is to utilize positive photoresist to make.
Alternatively, utilize the method for spin coating to form described siliceous RELACS material layer.
Alternatively, the temperature that described mixing is cured is 60 DEG C-300 DEG C, and the time is 30s-300s.
Alternatively, remove cross-linked layer on described photoetching offset plate figure top, the siliceous RELACS material layer of cross-linking reaction do not occur and the step of photoetching offset plate figure comprises:
Remove the siliceous RELACS material layer that cross-linking reaction does not occur, to expose described cross-linked layer;
Described cross-linked layer is returned and carved until expose described photoetching offset plate figure, the remaining cross-linked layer formation side wall that is positioned at described photoetching offset plate figure both sides;
Remove described photoetching offset plate figure.
Alternatively, utilize developer solution to remove the siliceous RELACS material layer that cross-linking reaction does not occur.
Alternatively, described developer solution is the TMAH aqueous solution.
Alternatively, carve the etching gas adopting for described time and at least comprise CO
2, O
2, N
2, H
2, CF
4, Cl
2in one.
Alternatively, utilize developer solution to remove described photoetching offset plate figure.
Alternatively, described developer solution is the TMAH aqueous solution.
Alternatively, form described photoetching offset plate figure in described Semiconductor substrate before, in described Semiconductor substrate, form bottom antireflective coating.
Alternatively, form described side wall and also comprise afterwards: taking described side wall as mask, described bottom antireflective coating is carried out to etching, form bottom antireflective coating figure.
Alternatively, remove cross-linked layer on described photoetching offset plate figure top, the siliceous RELACS material layer of cross-linking reaction do not occur and the step of photoetching offset plate figure comprises:
Siliceous RELACS material layer and cross-linked layer that cross-linking reaction does not occur are returned to quarter, until expose described photoetching offset plate figure, the remaining cross-linked layer that is positioned at described photoetching offset plate figure both sides forms side wall;
Remove siliceous RELACS material layer and described photoetching offset plate figure that cross-linking reaction does not occur.
Alternatively, carve the etching gas adopting for described time and at least comprise CO
2, O
2, N
2, H
2, CF
4, Cl
2in one.
Alternatively, utilize developer solution to remove siliceous RELACS material layer and described photoetching offset plate figure that cross-linking reaction does not occur.
Alternatively, described developer solution is the TMAH aqueous solution.
Alternatively, form described photoetching offset plate figure in described Semiconductor substrate before, in described Semiconductor substrate, form bottom antireflective coating.
Alternatively, form described side wall and also comprise afterwards: taking described side wall as mask, described bottom antireflective coating is carried out to etching, form bottom antireflective coating figure.
Alternatively, forming bottom antireflective coating figure also comprises afterwards:
Remove described side wall, on described Semiconductor substrate and bottom antireflective coating figure, form amorphous carbon layer;
Described amorphous carbon layer is returned to quarter, and the remaining amorphous carbon layer that is positioned at described bottom antireflective coating figure both sides forms side wall;
Remove described bottom antireflective coating figure.
In addition, the present invention also provides the application of a kind of silica-based hard mask compositions as RELACS material.
Compared with prior art, the present invention has the following advantages:
Autoregistration multiple patterning methods provided by the present invention has adopted a kind of silica-based hard mask compositions to be used as RELACS material, form photoetching offset plate figure in Semiconductor substrate after, this siliceous RELACS material is covered on photoetching offset plate figure, then mix and cure, under the effect of curing in mixing, impel the siliceous RELACS material generation cross-linking reaction contacting with photoetching offset plate figure, thereby the surface at photoetching offset plate figure forms cross-linked layer, then remove the cross-linked layer at photoetching offset plate figure top, there is not siliceous RELACS material and the photoetching offset plate figure of cross-linking reaction, remaining cross-linked layer forms side wall, can side wall in subsequent process steps be mask with by graph transfer printing on Semiconductor substrate, form the figure that hope obtains.Compared with the autoregistration Double-patterning method that utilizes existing RELACS material to realize, the autoregistration multiple patterning methods that the present invention utilizes this siliceous RELACS material layer to realize can solve the not high problem of verticality of side wall of existing autoregistration figure that Double-patterning method obtains.
Further, in the time that photoetching offset plate figure below is formed with bottom antireflective coating, the autoregistration multiple patterning methods that the present invention utilizes this siliceous RELACS material layer to realize can solve in existing autoregistration Double-patterning method bottom antireflective coating can be by too much etching, so that the Semiconductor substrate of the bottom antireflective coating below problem that may sustain damage.
Further, after utilizing the rectangular side wall in cross-linked layer formation top, can also side wall be that mask aligning carries out etching in the bottom antireflective coating of its below, with by graph transfer printing to bottom antireflective coating, after removing side wall, on Semiconductor substrate and bottom antireflective coating figure, form one deck amorphous carbon layer, this amorphous carbon layer is returned and carves afterwards and can form side wall in the both sides of bottom antireflective coating figure, the side wall density being made up of amorphous carbon layer is three times of photoetching offset plate figure density, thereby the triple graphic methods of autoregistration are realized, thereby realize less lithographic feature size, promote the development of photoetching technique.
Brief description of the drawings
Fig. 1 to Fig. 6 utilizes existing autoregistration Double-patterning method in Semiconductor substrate, to form the making schematic diagram of figure;
Fig. 7 is the enlarged drawing that utilizes existing autoregistration figure that Double-patterning method obtains;
Fig. 8 is the making flow chart of autoregistration multiple patterning methods in embodiments of the present invention one;
Fig. 9 to Figure 16 utilizes autoregistration multiple patterning methods in Semiconductor substrate, to form the making schematic diagram of figure in embodiments of the present invention one, wherein, Figure 14 is the relatively schematic diagram of verticality of side wall of existing autoregistration side wall that Double-patterning method forms and autoregistration side wall that multiple patterning methods forms of the present invention;
Figure 17 to Figure 22 utilizes autoregistration multiple patterning methods in Semiconductor substrate, to form the making schematic diagram of figure in embodiments of the present invention two;
Figure 23 to Figure 25 utilizes autoregistration multiple patterning methods in Semiconductor substrate, to form the making schematic diagram of figure in embodiments of the present invention three.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, technical scheme of the present invention is carried out to clear, complete description, obviously, described embodiment is only a part for embodiment of the present invention, instead of they are whole.According to these embodiment, those of ordinary skill in the art is obtainable all other execution modes under the prerequisite without creative work, all belong to protection scope of the present invention.
, publication number open on November 4th, 2010 is that the United States Patent (USP) that US20100279509A1, name are called " silicon-based hardmask composition and process of producing semiconductor integrated circuit device using the same " discloses a kind of silica-based hard mask compositions (silicon-based hardmask composition), and a kind of process of utilizing this silica-based hard mask compositions to make semiconductor integrated circuit.In this patent, mentioning described silica-based hard mask compositions, to have surface hydrophilicity high, antireflective property is strong, the advantages such as storage endurance ability is good, therefore proposed on this basis a kind of process of utilizing this silica-based hard mask compositions to make semiconductor integrated circuit, the method forms successively from the bottom to top carbon-based hard mask (carbon-based hardmask) in Semiconductor substrate, the silica-based hard mask (silicon-based hardmask) that utilizes silica-based hard mask compositions to make, photoresist layer, then photoresist layer is exposed, develop, form photoetching offset plate figure, taking photoetching offset plate figure as mask by graph transfer printing to silica-based hard mask, then by graph transfer printing on carbon-based hard mask, finally by graph transfer printing on Semiconductor substrate.By utilizing silica-based hard mask compositions the photoetching offset plate figure of very thin thickness successfully can be transferred in Semiconductor substrate.
Inventor finds, silica-based hard mask compositions in above-mentioned patent is except can be used to make silica-based hard mask, outside the photoetching offset plate figure of very thin thickness is successfully transferred in Semiconductor substrate, described silica-based hard mask compositions also can replace the existing RELACS material of mentioning in background technology above as a kind of new RELACS material, and the verticality of side wall that the autoregistration multiple patterning methods that utilizes this siliceous RELACS material layer to realize can solve existing autoregistration figure that Double-patterning method obtains is not high, and in existing autoregistration Double-patterning method, bottom antireflective coating can be by too much etching, so that the problem that the Semiconductor substrate of bottom antireflective coating below may sustain damage, below by three kinds of execution modes, technical scheme of the present invention is elaborated.
Execution mode one
Fig. 8 is the making flow chart of autoregistration multiple patterning methods in embodiments of the present invention one, and as shown in Figure 8, the method comprises:
Step S1: Semiconductor substrate is provided, forms photoetching offset plate figure in Semiconductor substrate.
Step S2: form siliceous RELACS material layer on Semiconductor substrate and photoetching offset plate figure.
Step S3: mix and cure, form cross-linked layer on photoetching offset plate figure surface.
Step S4: remove the siliceous RELACS material layer that cross-linking reaction does not occur, to expose cross-linked layer.
Step S5: cross-linked layer is returned and carved until expose photoetching offset plate figure.
Step S6: remove photoetching offset plate figure, remaining cross-linked layer forms side wall.
Fig. 9 to Figure 15 utilizes autoregistration multiple patterning methods in Semiconductor substrate, to form the making schematic diagram of figure in embodiments of the present invention one, below in conjunction with Fig. 8 to Figure 15, the technical scheme of embodiment of the present invention one is elaborated.
As shown in Figure 9, provide Semiconductor substrate 10, in Semiconductor substrate 10, at least form a photoetching offset plate figure 30, in figure taking four photoetching offset plate figures 30 as example.Particularly, can in Semiconductor substrate 10, form photoresist layer (not shown), then described photoresist layer be exposed, developed, to form photoetching offset plate figure 30 in Semiconductor substrate 10.Because positive photoresist has good analytic ability, can on photoresist layer, form the figure that critical size is less, in one embodiment, photoetching offset plate figure 30 utilizes positive photoresist to make.Semiconductor substrate 10 comprises by autoregistration multiple patterning methods of the present invention can form the equivalent layer of wishing figure, described equivalent layer can be conductive layer, semiconductor layer or insulating barrier, as one of them example, Semiconductor substrate 10 comprises polysilicon layer, utilize autoregistration multiple patterning methods of the present invention to carry out graphical treatment to this polysilicon layer, to form polysilicon gate.
In one embodiment, in the time that described photoresist layer is exposed, in order to reduce the reflection when the exposed photoresist layer, form described photoresist layer in Semiconductor substrate 10 before, first form bottom antireflective coating (BARC) 20, can make like this sidewall pattern of photoetching offset plate figure 30 better.
As shown in figure 10, form the siliceous RELACS material layer 40 of one deck on Semiconductor substrate 10 and photoetching offset plate figure 30, siliceous RELACS material layer 40 is lived the surface coverage of photoetching offset plate figure 30.Siliceous RELACS material layer 40 is that the disclosed silica-based hard mask compositions of United States Patent (USP) that utilizes above-mentioned publication number to be US20100279509A1 is made.As a specific embodiment, can utilize spin-coating method to form siliceous RELACS material layer 40.In the time being formed with bottom antireflective coating 20 in Semiconductor substrate 10, siliceous RELACS material layer 40 covers on bottom antireflective coating 20 and photoetching offset plate figure 30.
As shown in figure 11, mix and cure (mixing bake), under the effect of curing in mixing, remain in the light acid molecule in photoetching offset plate figure 30 and produce diffusion motion because be heated, in the process of diffusion, can produce new light acid molecule simultaneously, these light acid molecules can diffuse in the siliceous RELACS material layer 40 contacting with photoetching offset plate figure 30, and then the cross-linking reaction of the siliceous RELACS material layer 40 that contacts with photoetching offset plate figure 30 of catalysis, described cross-linking reaction makes the surface of photoetching offset plate figure 30 form cross-linked layer 41, in other words, on the top of photoetching offset plate figure 30 and sidewall, be all coated with cross-linked layer 41.In figure, the thickness h of cross-linked layer 41 is less than the width w of photoetching offset plate figure 30.The thickness h of cross-linked layer 41 is with to mix the temperature of curing relevant, and when the temperature of curing when mixing is higher, the thickness h of cross-linked layer 41 is larger.As a specific embodiment, the temperature that described mixing is cured is 60 DEG C-300 DEG C, and mixing the time of curing is 30s-300s.
As shown in figure 12, remove the siliceous RELACS material layer 40 that cross-linking reaction does not occur in Figure 11, to expose cross-linked layer 41.In one embodiment, utilize developer solution the siliceous RELACS material layer 40 of cross-linking reaction not to occur described in removing, then, cure, to remove moisture.As a specific embodiment, described developer solution can be TMAH(Tetramethylammonium hydroxide) aqueous solution, its concentration can be 2.38%(percent by volume).
Shown in Figure 12 and Figure 13, cross-linked layer 41 is returned to quarter, until expose photoetching offset plate figure 30, the remaining cross-linked layer 41 that is positioned at photoetching offset plate figure 30 both sides forms side wall 42.According to returning, the etching principle of carving is known, and the shape at side wall 42 tops is similar to arc.As a specific embodiment, carve the etching gas adopting described time and at least comprise CO
2, O
2, N
2, H
2, CF
4, Cl
2in one.
Figure 14 is the relatively schematic diagram of verticality of side wall of existing autoregistration side wall that Double-patterning method forms and autoregistration side wall that multiple patterning methods forms of the present invention, as shown in figure 14, in figure, dotted portion represents the lip-deep cross-linked layer of photoetching offset plate figure, in figure, double dot dash line part represents existing autoregistration side wall that Double-patterning method forms, and in figure, solid line part represents autoregistration side wall that multiple patterning methods forms of the present invention.Inventor is by utilizing sweep electron microscope (FE-SEM) to detect rear discovery to the sidewall pattern that utilizes autoregistration figure that multiple patterning methods obtains of the present invention, compared with existing autoregistration side wall that Double-patterning method forms, the verticality of side wall of side wall that the present invention forms is higher, this area relevant knowledge of grasping according to inventor, inventor analyzes its reason and should comprise multiple, the for example etch rate of siliceous RELACS cross-linked layer that material layer forms, selected etching gas when etching, the selection of etching parameters, the stackeding speed of polymer in etching pattern side wall when etching, when etching, the factor such as density distribution uniformity of the plasma that produces all can affect the perpendicularity of side wall, wherein, the etch rate of siliceous RELACS cross-linked layer that material layer forms is as follows on the impact of side wall perpendicularity: in the time cross-linked layer (dotted portion in figure) being returned to quarter, in the time exposing photoetching offset plate figure 30, stop etching, and under identical etching condition, the speed that is etched of the cross-linked layer that the existing RELACS material of the speed ratio that is etched of the cross-linked layer that in the present invention, siliceous RELACS material produces through cross-linking reaction produces through cross-linking reaction is faster, in other words, the etching selection ratio of the cross-linked layer that the cross-linked layer that siliceous RELACS material produces through cross-linking reaction and existing RELACS material produce through cross-linking reaction is greater than 1, therefore, in the time that the cross-linked layer thickness on photoetching offset plate figure 30 equates, the present invention's required etch period in this step is shorter than existing required etch period, therefore the amount of being removed at side wall top is less than the amount of being removed at existing side wall top in the present invention, thereby the verticality of side wall of side wall of the present invention is higher than the verticality of side wall of existing side wall.
In addition, in the time being formed with bottom antireflective coating 20 in Semiconductor substrate 10, the speed that is etched of the cross-linked layer that the existing RELACS material of the speed ratio that is etched of the cross-linked layer producing through cross-linking reaction due to RELACS material siliceous in the present invention produces through cross-linking reaction is faster, therefore, the cross-linked layer that in the present invention, siliceous RELACS material produces through cross-linking reaction and the etching selection ratio of bottom antireflective coating 20, be greater than cross-linked layer that existing RELACS material produces through cross-linking reaction and the etching selection ratio of bottom antireflective coating, therefore, as shown in figure 13, in the time returning formation at quarter side wall 42, in the present invention, the amount of being etched of bottom antireflective coating 20 still less, therefore the possibility that bottom antireflective coating 20 was worn by quarter is less, reduce the probability that Semiconductor substrate 10 is caused to damage.
As shown in figure 15, remove the photoetching offset plate figure 30 shown in Figure 13, in the multiple side wall 42(figure in Semiconductor substrate 10 taking 8 as example) there is each other interval.In one embodiment, utilize developer solution to remove photoetching offset plate figure 30.As a specific embodiment, the aqueous solution that described developer solution is TMAH.Relatively Figure 15 and Fig. 9 are known, and the density of side wall 42 is twices of photoetching offset plate figure 30 density, and the spacing between adjacent two side walls 42 is less than the spacing between adjacent two photoetching offset plate figures 30.
After forming side wall 42, can directly carry out etching taking side wall 42 as mask to the equivalent layer in Semiconductor substrate 10, the figure obtaining to form hope, as polysilicon gate.In the time being formed with bottom antireflective coating 20 in Semiconductor substrate 10, shown in Figure 15 and Figure 16, first taking side wall 42 as mask, bottom antireflective coating 20 is carried out to etching, form multiple (in figure taking 8 as example) bottom antireflective coating figure 21, then can carry out etching for mask to the equivalent layer in Semiconductor substrate 10 by bottom antireflective coating figure 21, the figure (not shown) obtaining to form hope.
From the above, the autoregistration multiple patterning methods in above-mentioned execution mode one is essentially autoregistration Double-patterning method.
Execution mode two
Figure 17 to Figure 22 utilizes autoregistration multiple patterning methods in Semiconductor substrate, to form the making schematic diagram of figure in embodiments of the present invention two, below in conjunction with Figure 17 to Figure 22, the technical scheme of embodiment of the present invention two is elaborated.
As shown in figure 17, provide Semiconductor substrate 10 ＇, on Semiconductor substrate 10 ＇, at least form photoetching offset plate figure 30 ＇, in figure taking four photoetching offset plate figure 30 ＇ as example.Particularly, can on Semiconductor substrate 10 ＇, form photoresist layer (not shown), then described photoresist layer be exposed, developed, to form photoetching offset plate figure 30 ＇ on Semiconductor substrate 10 ＇.In one embodiment, photoetching offset plate figure 30 ＇ utilize positive photoresist to make.
In one embodiment, in the time that described photoresist layer is exposed, in order to reduce the reflection when the exposed photoresist layer, form described photoresist layer on Semiconductor substrate 10 ＇ before, first form bottom antireflective coating (BARC) 20 ＇, can make like this sidewall pattern of photoetching offset plate figure 30 ＇ better.
As shown in figure 18, form siliceous RELACS material layer 40 ＇ of one deck on Semiconductor substrate 10 ＇ and photoetching offset plate figure 30 ＇, siliceous RELACS material layer 40 ＇ live the surface coverage of photoetching offset plate figure 30 ＇.Siliceous RELACS material layer 40 ＇ are that the disclosed silica-based hard mask compositions of United States Patent (USP) that utilizes above-mentioned publication number to be US20100279509A1 is made.As a specific embodiment, can utilize spin-coating method to form siliceous RELACS material layer 40 ＇.In the time being formed with bottom antireflective coating 20 ＇ on Semiconductor substrate 10 ＇, siliceous RELACS material layer 40 ＇ cover on bottom antireflective coating 20 ＇ and photoetching offset plate figure 30 ＇.
As shown in figure 19, mix and cure (mixing bake), under the effect of curing in mixing, remain in the light acid molecule in photoetching offset plate figure 30 ＇ and produce diffusion motion because be heated, in the process of diffusion, can produce new light acid molecule simultaneously, these light acid molecules can diffuse in siliceous RELACS material layer 40 ＇ that contact with photoetching offset plate figure 30 ＇, and then the cross-linking reaction of siliceous RELACS material layer 40 ＇ that contact with photoetching offset plate figure 30 ＇ of catalysis, described cross-linking reaction makes the surface of photoetching offset plate figure 30 ＇ form cross-linked layer 41 ＇, in other words, on the top of photoetching offset plate figure 30 ＇ and sidewall, be all coated with cross-linked layer 41 ＇.The thickness h ＇ of cross-linked layer 41 ＇ is with to mix the temperature of curing relevant, and when the temperature of curing when mixing is higher, the thickness h ＇ of cross-linked layer 41 ＇ is larger.As a specific embodiment, the temperature that described mixing is cured is 60 DEG C-300 DEG C, and mixing the time of curing is 30s-300s.
As shown in figure 20, RELACS material layer 40 ＇ shown in Figure 19 and cross-linked layer 41 ＇ are returned to quarter, until expose photoetching offset plate figure 30 ＇.After returning quarter, cross-linked layer 41 ＇ at photoetching offset plate figure 30 ＇ tops are removed, remaining cross-linked layer 41 ＇ that are positioned at photoetching offset plate figure 30 ＇ both sides form side wall 42 ＇, between adjacent two side wall 42 ＇ (these two side walls are respectively formed on the sidewall of different photoetching offset plate figure 30 ＇), are filled with RELACS material layer 40 ＇ that cross-linking reaction does not occur.As a specific embodiment, return the etching gas adopting quarter and at least comprise CO
2, O
2, N
2, H
2, CF
4, Cl
2in one.
Shown in Figure 20 and Figure 21, remove photoetching offset plate figure 30 ＇ and RELACS material layer 40 ＇ of cross-linking reaction do not occur, there is each other interval in upper multiple side wall 42 ＇ of Semiconductor substrate 10 ＇.In one embodiment, utilize developer solution remove photoetching offset plate figure 30 ＇ and RELACS material layer 40 ＇ of cross-linking reaction do not occur.As a specific embodiment, described developer solution is the aqueous solution of TMAH.
Relatively Figure 21 and Figure 17 are known, because the formation method of 42 ＇ of side wall in present embodiment is not identical with the formation method of side wall 42 in execution mode one, cause the shape of side wall 42 ＇ in present embodiment to contrast shown in Figure 15 with side wall 42(in execution mode one) shape distinguish to some extent: in execution mode one, the top of side wall 42 is arc, and the top of side wall 42 ＇ can not be etched in present embodiment, therefore rectangular, the reasons are as follows: RELACS material layer 40 ＇ and cross-linked layer 41 ＇ being returned while carving, in the time exposing photoetching offset plate figure 30 ＇, stop etching, and cross-linked layer 41 ＇ that exceed photoetching offset plate figure 30 ＇ when etching stopping are etched at one time, therefore the end of side wall 42 ＇ can not be etched, therefore the end of side wall 42 ＇ is rectangular.
In addition, the cross-linked layer 41 ＇ thickness that form through cross-linking reaction are (when length is as 30s-300s, can guarantee that cross-linked layer 41 ＇ thickness are uniform when the time of curing of RELACS material layer 40 ＇) uniformly, therefore the perpendicularity of side wall 42 ＇ is very high, thereby compared with existing autoregistration side wall that Double-patterning method forms, the verticality of side wall of embodiment of the present invention two side wall that forms is higher.
Further, it is that the sidewall pattern of side wall 42 ＇ detects to the embodiment of the present invention two autoregistration figure that multiple patterning methods obtains that provides is provided that inventor utilizes sweep electron microscope (FE-SEM), and testing result also proves that the perpendicularity of side wall 42 ＇ is higher.
In the time being formed with bottom antireflective coating 20 ＇ on Semiconductor substrate 10 ＇, as shown in figure 20, carve while forming side wall 42 ＇ because bottom antireflective coating 20 ＇ are covered by RELACS material layer 40 ＇ returning, therefore in the present invention, bottom antireflective coating 20 ＇ can not be etched, thereby can not cause damage to Semiconductor substrate 10 ＇.
Relatively Figure 21 and Figure 17 are known, and the density of side wall 42 ＇ is the twice of photoetching offset plate figure 30 ＇ density, and the spacing between adjacent two side wall 42 ＇ is less than the spacing between adjacent two photoetching offset plate figure 30 ＇.
After forming side wall 42 ＇, can directly carry out etching taking side wall 42 ＇ as mask to the equivalent layer on Semiconductor substrate 10 ＇, the figure obtaining to form hope, as polysilicon gate.
In the time being formed with bottom antireflective coating 20 ＇ on Semiconductor substrate 10 ＇, shown in Figure 21 and Figure 22, first taking side wall 42 ＇ as mask, bottom antireflective coating 20 ＇ are carried out to etching, form multiple (in figure taking 8 as example) bottom antireflective coating figure 21 ＇, then can bottom antireflective coating figure 21 ＇ be that mask carries out etching to the equivalent layer on Semiconductor substrate 10 ＇, the figure (not shown) obtaining to form hope.
As shown in the above, the autoregistration multiple patterning methods in above-mentioned execution mode two is essentially autoregistration Double-patterning method.
Execution mode three
When being formed with bottom antireflective coating 20 ＇ on Semiconductor substrate 10 ＇, and while being formed with multiple bottom antireflective coating figure 21 ＇, on the basis of execution mode two, as shown in figure 23, remove side wall 42 ＇ shown in Figure 22, continue to form amorphous carbon (amorpous carbon) layer 50 on Semiconductor substrate 10 ＇ and bottom antireflective coating figure 21 ＇, amorphous carbon layer 50 covers top and the sidewall of bottom antireflective coating figure 21 ＇.
As shown in figure 24, the amorphous carbon layer 50 shown in Figure 23 is returned to quarter, until expose bottom antireflective coating figure 21 ＇, the remaining amorphous carbon layer 50 that is positioned at bottom antireflective coating figure 21 ＇ both sides forms side wall 51.
As shown in figure 25, removing bottom antireflective coating figure 21 ＇ shown in Figure 24, there is interval in multiple side walls 51 each other.
Relatively Figure 25 and Figure 21, Figure 17 are known, and the density of the upper side wall 51 of Semiconductor substrate 10 ＇ is twices of side wall 42 ＇ density, and the density of side wall 51 is three times of photoetching offset plate figure 30 ＇.Thereby the autoregistration multiple patterning methods in present embodiment is essentially triple graphical (Self-aligned Triple Double Patterning, the abbreviate SAT P) methods of autoregistration.
Above-mentioned by the explanation of embodiment, should be able to make professional and technical personnel in the field understand better the present invention, and can reproduce and use the present invention.Those skilled in the art can do not depart from the spirit and scope of the invention in the situation that to above-described embodiment do various changes according to described principle herein and amendment is apparent.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (20)
1. an autoregistration multiple patterning methods, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, at least forms a photoetching offset plate figure;
On described Semiconductor substrate and photoetching offset plate figure, form siliceous RELACS material layer;
Mix and cure, the siliceous RELACS material layer generation cross-linking reaction contacting with described photoetching offset plate figure, and form cross-linked layer on described photoetching offset plate figure surface;
Remove cross-linked layer on described photoetching offset plate figure top, siliceous RELACS material layer and the photoetching offset plate figure of cross-linking reaction do not occur, remaining cross-linked layer forms side wall.
2. autoregistration multiple patterning methods according to claim 1, is characterized in that, described photoetching offset plate figure is to utilize positive photoresist to make.
3. autoregistration multiple patterning methods according to claim 1, is characterized in that, utilizes the method for spin coating to form described siliceous RELACS material layer.
4. autoregistration multiple patterning methods according to claim 1, is characterized in that, the temperature that described mixing is cured is 60 DEG C-300 DEG C, and the time is 30s-300s.
5. autoregistration multiple patterning methods according to claim 1, is characterized in that, removes cross-linked layer on described photoetching offset plate figure top, the siliceous RELACS material layer of cross-linking reaction does not occur and the step of photoetching offset plate figure comprises:
Remove the siliceous RELACS material layer that cross-linking reaction does not occur, to expose described cross-linked layer;
Described cross-linked layer is returned and carved until expose described photoetching offset plate figure, the remaining cross-linked layer formation side wall that is positioned at described photoetching offset plate figure both sides;
Remove described photoetching offset plate figure.
6. autoregistration multiple patterning methods according to claim 5, is characterized in that, utilizes developer solution to remove the siliceous RELACS material layer that cross-linking reaction does not occur.
7. autoregistration multiple patterning methods according to claim 6, is characterized in that, described developer solution is the TMAH aqueous solution.
8. autoregistration multiple patterning methods according to claim 5, is characterized in that, carves the etching gas adopting described time and at least comprises CO
2, O
2, N
2, H
2, CF
4, Cl
2in one.
9. autoregistration multiple patterning methods according to claim 5, is characterized in that, utilizes developer solution to remove described photoetching offset plate figure.
10. autoregistration multiple patterning methods according to claim 9, is characterized in that, described developer solution is the TMAH aqueous solution.
11. autoregistration multiple patterning methods according to claim 5, is characterized in that, before forming described photoetching offset plate figure, in described Semiconductor substrate, form bottom antireflective coating in described Semiconductor substrate.
12. autoregistration multiple patterning methods according to claim 11, is characterized in that, form described side wall and also comprise afterwards: taking described side wall as mask, described bottom antireflective coating is carried out to etching, form bottom antireflective coating figure.
13. autoregistration multiple patterning methods according to claim 1, is characterized in that, remove cross-linked layer on described photoetching offset plate figure top, the siliceous RELACS material layer of cross-linking reaction occur and the step of photoetching offset plate figure comprises:
Siliceous RELACS material layer and cross-linked layer that cross-linking reaction does not occur are returned to quarter, until expose described photoetching offset plate figure, the remaining cross-linked layer that is positioned at described photoetching offset plate figure both sides forms side wall;
Remove siliceous RELACS material layer and described photoetching offset plate figure that cross-linking reaction does not occur.
14. autoregistration multiple patterning methods according to claim 13, is characterized in that, carve the etching gas adopting described time and at least comprise CO
2, O
2, N
2, H
2, CF
4, Cl
2in one.
15. autoregistration multiple patterning methods according to claim 13, is characterized in that, utilize developer solution to remove siliceous RELACS material layer and described photoetching offset plate figure that cross-linking reaction does not occur.
16. autoregistration multiple patterning methods according to claim 15, is characterized in that, described developer solution is the TMAH aqueous solution.
17. autoregistration multiple patterning methods according to claim 13, is characterized in that, before forming described photoetching offset plate figure, in described Semiconductor substrate, form bottom antireflective coating in described Semiconductor substrate.
18. autoregistration multiple patterning methods according to claim 17, is characterized in that, form described side wall and also comprise afterwards: taking described side wall as mask, described bottom antireflective coating is carried out to etching, form bottom antireflective coating figure.
19. autoregistration multiple patterning methods according to claim 18, is characterized in that, form bottom antireflective coating figure and also comprise afterwards:
Remove described side wall, on described Semiconductor substrate and bottom antireflective coating figure, form amorphous carbon layer;
Described amorphous carbon layer is returned to quarter, and the remaining amorphous carbon layer that is positioned at described bottom antireflective coating figure both sides forms side wall;
Remove described bottom antireflective coating figure.
20. silica-based hard mask compositions are as the application of RELACS material.
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