TWI485772B - Method of forming via hole - Google Patents

Description

Method of forming a via hole

The present invention relates to a method of forming a contact hole, and more particularly to a method of forming a contact hole using a barrier layer.

Lithography is an indispensable key process technology in integrated circuit manufacturing. With the lithography process, semiconductor manufacturers can smoothly transfer the integrated circuit layout pattern to the semiconductor wafer accurately and clearly. However, with the increasing complexity and integration of integrated circuits, the conventional lithography process also faces many difficulties.

For example, when forming a via hole, the aperture size of the via hole and the distance between each via hole are limited by the resolution limit of the photomask. In the prior art, the method of forming the via hole is to use the photoresist layer as an etch mask for etching the underlying dielectric layer, and in the process of 22 nm (nm), the pitch of the via hole etching (pitch, ie, two adjacent The distance between the center points of the vias must be less than 90 nm, and the after development inspect critical dimension (ADICD) must be approximately 35 to 50 nm. As far as the current yellow light machine technology is concerned, it is impossible to complete contact holes with a pitch of less than 90 nm in one exposure process. Therefore, it is common practice in the industry to use two masks to expose the photoresist layer twice. An etching is performed again to pattern the contact holes. In this way, a small aperture array of holes can be obtained.

However, by the above-mentioned double exposure process, a regularly arranged array of via holes can be formed, which is suitable for the formation of a memory array, but such a technique cannot be applied to an existing integrated circuit layout, for example, including an irregular arrangement. The integrated circuit layout of the via hole.

Therefore, the present invention provides a method of fabricating a via hole, which can form a via hole having a small aperture by using the above-described secondary mask, and can be applied to a conventional integrated circuit layout.

In accordance with a preferred embodiment of the present invention, the present invention provides a method of forming a via. First, a substrate is provided with a plurality of first regions defined on the substrate. A dielectric layer and a barrier layer are then formed on the substrate. A patterned photoresist layer is then formed on the barrier layer, wherein the patterned photoresist layer has an array of apertures, and the area of the aperture array is larger than the area of the first region. The patterned photoresist layer is then masked to remove the barrier layer located in the first region. Finally, the dielectric layer is patterned to form at least one via in the dielectric layer in the first region.

In the present invention, since the patterned barrier layer is used before the etching step of forming the via hole, the via hole can be formed only in the region to be formed (ie, the first region), and is not formed in other regions. . Therefore, in one aspect, the present invention can utilize a double exposure process to form a via hole having a smaller aperture, and on the other hand, can be applied to an integrated circuit layout having irregularly arranged via holes.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 12 , which are schematic diagrams showing the steps of the method for forming a via hole according to the present invention. Please refer to Fig. 1 and Fig. 2 first, and Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1. As shown in Figures 1 and 2, a substrate 300 is first provided. The substrate 300 can be a germanium substrate, or the substrate 300 can comprise a germanium substrate (not shown) and a dielectric layer or protective layer (not shown) disposed on one or more layers of the germanium substrate. As shown in FIG. 1, at least one first region 400 is defined on the substrate 300 as a region for subsequently forming a via hole.

A dielectric layer 302 is then formed on the substrate 300 by, for example, plasma enhanced chemical vapor deposition (PECVD) or high density plasma CVD or spin. Coating method, etc., but not limited to this. The dielectric layer 302 may comprise one or more layers of dielectric materials such as cerium oxide (SiO ₂ ), cerium nitride (SiN), tantalum carbide (SiC), cerium oxynitride (SiON), and USG (undoped silicate glass). , BPSG (borophosphosilicate glass), FSG (fluorine-doped silicate glass), HSQ (hydrogen silsesquioxane) (SiO:H), MSQ (methyl silsesquioxane) (SiO:CH ₃ ), HOSP, H-PSSQ (hydrio polysilsesquioxane), M -PSSQ (methyl polysilsesquioxane), P-PSSQ (phenyl polysilsesquioxane) or porous gel (porous sol-gel) or any combination thereof, but not limited thereto.

A barrier layer 304 is then formed over the dielectric layer 302 by, for example, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, or spin coating. The material of the barrier layer 304 comprises an organic material, such as a Si-contect bottom anti-reflective coating (Si-content BARC).

Next, as shown in FIG. 3, the barrier layer 304 is patterned to remove the barrier layer 304 located within the first region 400 to form a patterned barrier layer 306. For example, a photoresist layer (not shown) is formed on the barrier layer 304, followed by a lithography process to remove the photoresist layer located in the first region 400, and using the patterned photoresist layer as a mask. An etching process removes the barrier layer 304 in the first region 400 and finally removes the photoresist layer. Under the selected etchant or etch atmosphere, the etch rate of the barrier layer 304 should be much higher than the etch rate of the dielectric layer 302 to smoothly pattern the barrier layer 304 without damaging the dielectric layer 302 under the barrier layer 304.

Next, as shown in FIG. 4, a first photoresist layer 308 is formed on the patterned barrier layer 306. In an embodiment of the invention, the photoresist layer 308 comprises a positive photoresist material. Next, a first mask (not shown) is used to perform a first exposure step on the first photoresist layer 308, wherein the first mask has a plurality of first strip patterns 402. Please refer to FIG. 5, which illustrates the relative position of the first elongated strip pattern 402 and the lower first photoresist layer 308 when the first exposure step is performed using the first mask. The first elongated strip patterns 402 are parallel to each other and arranged in a lateral direction. It can be understood that the area where the first photoresist layer 308 overlaps with the first elongated patterns 402 is not exposed in the first exposure step, and other areas are exposed. A first development process is then performed to remove the first photoresist layer 308 that is not covered by the first strip 402 pattern.

Next, as shown in FIG. 6, a second photoresist layer 309 is formed on the patterned first photoresist layer 308, and then a planarization process is performed to form a first photoresist layer 308 and a second photoresist layer 309. Interlaced graphics as shown in Figure 6. In this embodiment, the second photoresist layer 309 includes a positive photoresist material, and the first photoresist layer 308 and the second photoresist layer 309 are incompatible with each other.

Next, as shown in FIG. 7, a second exposure step is performed on the second photoresist layer 309 using a second mask (not shown), wherein the second mask has a plurality of second strip patterns 404 parallel to each other. Arranged vertically. In one embodiment of the present invention, each of the first elongated patterns 402 intersects each of the second elongated patterns 404 to intersect at a 45 degree or 60 degrees, for example. In the preferred embodiment of the present invention, each of the first elongated patterns 402 intersects each of the second elongated patterns 404 at 90 degrees. The area that is not covered by the first strip pattern 402 and the second strip pattern 404 is referred to as a region D. Since the light source used in the second exposure step only acts on the two photoresist layer 309 without affecting the first photoresist layer 308, only the second photoresist layer 309 in the region D is exposed. .

Next, please refer to Fig. 8 and Fig. 9, and Fig. 9 is a schematic diagram of a tangent along AA' in Fig. 8. As shown in FIGS. 8 and 9, a second development process is performed to remove the photoresist layer 309 in the region D to obtain a patterned photoresist layer 310, wherein the patterned photoresist layer 310 is formed. The first photoresist layer 308 and the second photoresist layer 309 are included. The patterned photoresist layer 310 has a plurality of apertures 312 arranged in a regular array. It is worth noting that only the opening 312 in the first region 400 extends at its bottom to expose the underlying dielectric layer 302. The opening 312 outside the first region 400 does not extend into the dielectric layer 302 because its bottom is blocked by the barrier layer 306.

In addition, the patterned photoresist layer 310 is formed by using two layers of mutually incompatible first photoresist layer 308 and the second photoresist layer 309 in two exposures and two developments, but in another aspect of the present invention. In an embodiment, a photoresist layer may be used in combination with double exposure and one development, or directly in a third mask (not shown) having a first strip pattern 402 and a second strip pattern 404. By performing an exposure process, a patterned photoresist layer 310 having an array arrangement shape can be obtained. Alternatively, the patterned photoresist layer 310 of the present invention may be formed in other manners, and any method of forming a patterned photoresist layer 310 having a regular array arrangement is within the scope of the present invention.

Next, as shown in FIG. 10, with the patterned photoresist layer 310 as a mask, an etching step is performed to form a plurality of via holes 314 in the dielectric layer 302 in the first region 400. The patterned photoresist layer 310 is then removed. Next, please refer to FIG. 11 and FIG. 12, and FIG. 12 is a schematic view taken along line AA' in FIG. Finally, the barrier layer 306 is removed to obtain a dielectric layer 302 having a plurality of vias 314, and the locations of the vias 314 are only located in the first region 400.

In summary, the present invention uses a patterned barrier layer before the etching step of forming the via hole, so that the via hole can be formed only in the region to be formed (ie, the first region) without Will be formed in other areas. Therefore, in one aspect, the present invention can utilize a double exposure process to form a via hole having a smaller aperture, and on the other hand, can be applied to an integrated circuit layout having irregularly arranged via holes.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300. . . Base

302. . . Dielectric layer

304. . . Barrier layer

306. . . Patterned barrier

308. . . First photoresist layer

309. . . Second photoresist layer

310. . . Patterned photoresist layer

312. . . Opening

314. . . Via hole

400. . . First area

402. . . First long strip pattern

404. . . Second long strip pattern

1 to 12 are schematic views showing the steps of a method of forming a via hole according to the present invention.

300. . . Base

302. . . Dielectric layer

306. . . Patterned barrier

310. . . Patterned photoresist layer

312. . . Opening

400. . . First area

Claims (10)

A method of forming a via hole, comprising: providing a substrate having a plurality of first regions defined thereon; forming a dielectric layer and a barrier layer on the substrate; removing the barrier in the first regions Forming a patterned photoresist layer on the barrier layer, wherein the patterned photoresist layer has an aperture array, wherein an area of the aperture array is larger than an area of the first regions, and the blocking a sidewall of the layer is completely covered by the patterned photoresist layer; and the dielectric layer is patterned with the patterned photoresist layer as a mask to form at least one via hole in the dielectric layer in the first region . The method of forming a via hole according to claim 1, wherein the barrier layer comprises an organic layer. The method of forming a via hole according to claim 2, wherein the organic layer comprises a ruthenium-containing antireflection underlayer. The method for forming a via hole according to claim 1, wherein the step of forming the patterned photoresist layer comprises: forming a first photoresist layer on the barrier layer; and performing the first photoresist layer on the barrier layer a first exposure process is performed by a first development process to form a patterned first photoresist layer; and a second photoresist layer is formed on the patterned first photoresist layer; Performing a second exposure process and a second development process on the second photoresist layer to form a patterned second photoresist layer, wherein the patterned first photoresist layer and the patterned second light The resist layer constitutes the patterned photoresist layer. The method for forming a via hole according to the fourth aspect of the invention, wherein the material of the first photoresist layer is different from the material of the second photoresist layer. The method of forming a via hole according to claim 4, wherein the second exposure process only acts on the second photoresist layer. The method of forming a via hole according to claim 4, wherein the first exposing process comprises using a first photomask having a plurality of first strip patterns, and the second exposing process comprises using one A second reticle having a plurality of second elongated strip patterns. The method of forming a via hole according to claim 7, wherein each of the first elongated strip patterns is substantially perpendicular to each of the second elongated strip patterns. The method of forming a via hole according to claim 1, wherein the patterning of the dielectric layer further comprises removing the barrier layer. The method of forming a via hole according to claim 1, wherein the via hole is located only in the dielectric layer in the first region.