201227825 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種形成接觸洞的方法’特別是一種利用一阻拷 層來形成接觸洞的方法。 【先前技術】 微影製程(lithography)是積體電路製程中不可或缺的關鍵製程 技術。藉由微影製程，半導體製造者才能夠順利的將積體電路佈局 圖案精確且清晰地轉移至半導體晶片上。但隨著積體的複雜度 與積集度(integration)的不斷提昇，習知的微影製程也面臨到許多困 難。 舉例來說，在形成介層洞(一3110丨6)時，介層洞的孔徑大小以及 各介層洞之間的距離，會受限於光罩的解析度極限(resown H_。先前技術t製作介層洞的作法，係彻光阻層作祕刻下方 介電層的钮刻遮罩，而在22奈米㈣賴程下，介層洞侧的間距 (pitch，即兩鄰近介層洞中心點間之距離)必須小於如奈米，而且顯 ρ後關鍵尺寸(after development inspect critical dimension，ADICD)則 必須大約35至50奈米。就現行的黃光機台技術而言，其無法於一 次曝光製財完觸則、於9G奈麵接麻，所以目前業界常見的 作法是利用兩個光罩對光阻屢進行兩次曝光後，再進行一次餘刻， 以圖案化接觸孔。如此一來，即可得到一較小孔徑的介層洞陣列 201227825 (array) 〇 ^而，藉由前述的二次曝光製程，可以製作出規則排列的介層 洞陣列’適合記贿__成，但這樣的技術卻無法顧在現有 的積體電路佈局中’例如含有不規則排列介層洞的積體電路佈局中。 【發明内容】 因此本發明提出—種製作介層洞的方法，其可以利用前述二 次光罩的方絲形成孔徑較小之介層洞，且可簡祕現有積體電 路佈局中。201227825 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming a contact hole, particularly a method of forming a contact hole using a resistive layer. [Prior Art] Lithography is a key process technology that is indispensable in the process of integrated circuits. With the lithography process, semiconductor manufacturers can smoothly transfer the integrated circuit layout pattern to the semiconductor wafer accurately and clearly. However, with the increasing complexity and integration of the integrated body, the conventional lithography process also faces many difficulties. For example, when forming a via (a 3110丨6), the pore size of the via and the distance between the vias are limited by the resolution limit of the mask (resown H_. Prior art t The method of making the via hole is to make the photoresist layer as the button mask of the lower dielectric layer, and under the 22 nm (four) process, the pitch of the via hole (the pitch, that is, the two adjacent via holes) The distance between the center points must be less than, for example, nanometer, and the after development inspect critical dimension (ADICD) must be about 35 to 50 nm. As far as the current yellow machine technology is concerned, it cannot After one exposure and making money, it is connected to the 9G Nai surface. Therefore, it is common practice in the industry to use two masks to repeatedly expose the photoresist after two exposures, and then perform a residual moment to pattern the contact holes. In one way, a small aperture hole array 201227825 (array) can be obtained, and by the above-mentioned double exposure process, a regular array of via holes can be produced, which is suitable for recording bribes. But such technology can't take into account the existing integrated circuit layout. For example, in the integrated circuit layout including the irregularly arranged via holes, the present invention proposes a method for fabricating via holes, which can form a small aperture by using the square wires of the secondary mask. Layer holes, and can be used in the existing integrated circuit layout.
、，根據本發明較佳實施例，本發明提供一種形成介層洞的方法。 首先，提供-基底，基底上定義有複數個第_區域。接著於基底上 形成-介電層以及-阻擔層。織於阻擔層上形成—圖案化光阻 層，其中_化絲層具有-開孔陣列，簡孔_之面積大於第 -區域之面積。接著以圖案化光阻層為遮罩，以移除位於第一區域 内之輯層。最後圖案化介電層，以在第—區域内之介電層中形成 形 洞 本發明由於在形成介層洞之侧步驟前，使用了___ 層，因此可將介層洞僅形成於所欲戦的區域(即第—^_，/ 不會形成於其他區域。故本㈣一方面可_二次曝光的製程來 成較小孔_介制，另-转亦可助在具有不規卿列介層 201227825 的積體電路佈局上。 【實施方式】 為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本 發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳 細說明本發明的構成内容及所欲達成之功效。 請參考第1圖至第12圖，所繪示為本發明形成介層洞的方法之 步驟示意圖。請先參考第1圖與第2圖’第2圖為第1圖中沿著AA， 切線之剖面圖。如第i圖與第2圖所示，首先提供一基底3〇〇〇基 底300可為一矽基底，或者基底300可包含一矽基底(圖未明示)以 及設置於石夕基底上之一層或多層之介電層或保護層（圖未明示）。如 第1圖所示，基底300上定義有至少一第一區域4〇〇 ,係作為後續 形成介層洞之區域。 接著於基底300上形成一介電層302，形成的方法例如使用電 襞加強化學氣相沈積(plasma enhanced chemical vapor deposition, PECVD)或V%密度電紫化學氣相沈積(high density plasma CVD)或旋 塗法專，但並不以此為限。介電層302可以包含一層或多層的介電 材質’例如是二氧化矽(Si02)、氮化矽(SiN)、碳化矽(SiC)、氮氧化 石夕(SiON)、USG (undoped silicate glass)、BPSG (borophosphosilicate glass) ' FSG (fluorine-doped silicate glass) ' HSQ (hydrogen silsesquioxane) (SiO:H)、MSQ (methyl silsesquioxane)(SiO:CH3)、 201227825 HOSP、H-PSSQ (hydrio polysilsesquioxane)、M-PSSQ (methyl polysilsesquioxane)、P-PSSQ (phenyl p〇lySilsesqui〇xane)或多孔性凝 膠(porous s〇l-gel)或其任意組合，但並不以此為限。 接著於介電層302上形成一阻擋層304，形成的方法例如使用 電襞加強化學IU目沈積、高密度㈣化學氣相沈積或㈣塗佈的方 式。阻擋層304的材質包含有機材質，例如是一含矽抗反射底層 (Si-contect bottom anti-reflective coating，Si-eontent BARC)。 接著如第3圖所示’圖案化阻擋層3G4，以移除位於第一區域 400内的阻騎3G4’而形成-圖案化之阻擔層鄕。例如先於阻撐 層=上形成-光阻_未示），接著進行—微影製程以移除位於田 第^區域400内的光阻層，並利用圖案化的光阻層為遮罩進行一触 刻製程，移除第一區域彻内的阻擔層3〇4，最後再去除光阻芦。 在選定的_劑錢刻氛圍下，阻擋層3G4的_率應遠高於 ^ 304 304下方的介電層302。 接著如第4圖所示，於圖案化之阻擔層3Q6上形成 °於本發明之—實施例中’光阻層·包含正 ^驟—第一光罩(圖未示)來對第一光阻層3⑽進行-第曝 圖纽、帛光罩具有複數個第一長條狀圖案術。請參考第 圖’….示了使用第-光罩進行第—曝先麵時，第—長條^ 201227825 402與下方第一光阻層3〇8之相對位 0 第一長條狀圖案402彼此 十仃且呈k向排列。可以理解的是，第一 第先阻層308與這些第一長 條狀圖案402重疊之區域並不會在第— ru 釋㊉曝先步驟中被曝光，而其他 &域則會被曝光。然後進行―第—顯影: Αω ^ 杈u將未被第一長條狀 402圖案覆盍之第一光阻層308移除。 接著如第6圖所示，於圖案化之第一光阻層·上形成一第二 先阻層309，接著進行一平坦化製程使得第—光阻層通與第二光 阻層309形成—如第6圖所示之交錯_ 1本實施射，第二光 阻層309係包含正型光阻材質，且第一光阻層通和第二光阻層, 互不相溶。 接著如第7圖所示，使用―第二光細未示)對第二光阻層309 進行一第二曝光步驟，其中第二光罩具有複數個第二長條狀圖案 彼此平行呈縱向湖。於本發明之—實施财，各第一長條狀 圖案402相交於各第二長紐圖案4〇4例如呈一 μ度相交或6〇度 父而於本發明車父佳實施例中，各第一長條狀圖案搬與各第二 長條狀圖案撕呈9G度相交。而未被第一長條圖案402以及第二長 條圖案404覆蓋的_稱為區仙。由於第二曝光步驟所使用之光 源僅會對二光阻層3〇9產生作用，而不會對第—光阻層產生作 用’因此僅有區域D中的第二光阻層3〇9才會被曝光。 接著請參考第8 ®與第9圖，第9圖為第8圖中沿著μ，切線 201227825 之^、圖。如第8圖與第9騎示，接著進行—第二顯影製程，移 矛、品或t的光阻層309，而得到一圖案化之光阻層31〇，其中此 圖案化之光阻層31〇係包含第一光阻層3〇8以及第二光阻層猶。 圖案化之光阻層31〇上具有複數個成規則陣列㈣^排列之開孔 312值传左思的是，僅有在第一區域内的開孔祀，其底部會 延伸而暴露出下方的介電層3〇2。第一區域彻以外的開孔阳，由 於其底部被阻播層306阻隔，因此不會延伸至介電層3〇2中。 Φ 此外，前述圖案化光阻層31〇係利用兩層互不相容之第一光阻 層308與第二光阻層3〇9搭配兩次曝光與兩次顯影的方式來形成， 但於本發明另—實施射，亦可使用—光阻層搭配兩次曝光與一文 顯影的方式，或者直接以具有第一長條圖案4〇2加上第二長條圖案 之第三光罩(圖未示)直接進行曝光製程，皆可得到具有陣列排列 形狀的圖案化之光阻層310。或者，本發明的圖案化之光阻層训 亦可以以其他方式形成，凡可以形成具有規則陣列排列的圖案化之 •光阻層310之方法，應皆屬本發明的範嘴。 、 接著，如第ίο圖所示，以圖案化之光阻層31〇為遮罩，進行一 蝕刻步驟’以在第-區域4〇〇内的介電層3〇2中形成複數個介層洞 314。然後，移除圖案化之光阻層則。接著請參考第u圖與第a 圖所示’第12圖為第u圖中沿著从，切線之示意圖。最後，、移除 阻擔層306,而得到-具有複數個介層洞叫之介電層3〇2，且這些 介層洞314的位置僅會位於第一區域4〇〇中。 。 201227825 表丁、上所述，本發明由於在形成介層洞之姓刻步驟前，使用了圖 案化的阻擋層，因此可將介層洞僅形成於所欲形成的區域(即第一區 域)内’而不會形成於其他區域。故本發明—方面可_二次曝光的 製程來形成較小孔徑的介層洞H面亦可細在具有不規則排 列介層洞的積體電路佈局上。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 圖至第I2圖綠示了本發明形成介層洞的方法之步驟示意圖。 3〇〇 302 304 306 308 309 【主要元件符號說明】 基底 介電層 阻擋層 圖案化之阻擋層 第一光阻層 第二光阻層 310 圖案化之光阻層 312 開孔 314 介層洞 400 第一區域 402 第一長條狀圖案 404 第二長條狀圖案According to a preferred embodiment of the invention, the invention provides a method of forming a via. First, a substrate is provided with a plurality of _ regions defined on the substrate. A dielectric layer and a resist layer are then formed on the substrate. A patterned photoresist layer is formed on the resist layer, wherein the _ filament layer has an array of openings, and the area of the slab _ is larger than the area of the first region. The patterned photoresist layer is then masked to remove the layers located in the first region. Finally, the dielectric layer is patterned to form a hole in the dielectric layer in the first region. The present invention uses the ___ layer before the step of forming the via hole, so that the via hole can be formed only in the The area to be smashed (ie, the first ^^, / will not be formed in other areas. Therefore, on the one hand, the process of _ double exposure can be made into a smaller hole, and the other can also be used in irregular The present invention will be further understood by those skilled in the art to which the present invention pertains, and several preferred embodiments of the present invention are exemplified below. The present invention will be described in detail with reference to Fig. 1 to Fig. 12, which are schematic diagrams showing the steps of the method for forming a via hole according to the present invention. Figure 2 and Figure 2' Figure 2 is a cross-sectional view along the line AA in Fig. 1. As shown in Figures i and 2, a substrate 3 is first provided, and the substrate 300 can be a substrate. Or the substrate 300 may include a substrate (not shown) and a substrate disposed on the stone One or more layers of dielectric layers or protective layers (not shown). As shown in FIG. 1, at least one first region 4 定义 is defined on the substrate 300 as a region for subsequently forming a via hole. A dielectric layer 302 is formed on the substrate 300 by, for example, using plasma enhanced chemical vapor deposition (PECVD) or V% density electro-violet plasma CVD or spin coating. The method is not limited thereto. The dielectric layer 302 may comprise one or more layers of dielectric materials 'for example, cerium oxide (SiO 2 ), cerium nitride (SiN), tantalum carbide (SiC), oxynitride. (SiON), USG (undoped silicate glass), BPSG (borophosphosilicate glass) 'FSG (fluorine-doped silicate glass) ' HSQ (hydrogen silsesquioxane) (SiO:H), MSQ (methyl silsesquioxane) (SiO:CH3), 201227825 HOSP, H-PSSQ (hydrio polysilsesquioxane), M-PSSQ (methyl polysilsesquioxane), P-PSSQ (phenyl p〇lySilsesqui〇xane) or porous gel (porous s〇l-gel) or any combination thereof, but not Limited to this. Next to the dielectric layer 302 Forming a barrier layer 304, for example, a method of forming an electric fold reinforcing mesh IU chemical deposition, high density chemical vapor deposition (iv) (iv) or coating manner. The material of the barrier layer 304 comprises an organic material, such as a Si-contect bottom anti-reflective coating (Si-eontent BARC). Next, as shown in Fig. 3, the barrier layer 3G4 is patterned to remove the resist 3G4' located in the first region 400 to form a patterned resist layer. For example, prior to the barrier layer = upper formation - photoresist - not shown, followed by a lithography process to remove the photoresist layer located in the field region 400, and using the patterned photoresist layer as a mask In a one-touch process, the resist layer 3〇4 in the first region is removed, and finally the photoresist is removed. The barrier layer 3G4 should have a much higher _ rate than the dielectric layer 302 under the ^304 304 under the selected atmosphere. Next, as shown in FIG. 4, on the patterned resistive layer 3Q6, in the embodiment of the present invention, the 'photoresist layer includes the first photomask (not shown) for the first The photoresist layer 3 (10) is subjected to a first exposure pattern, and the reticle has a plurality of first strip patterns. Please refer to the figure '.... when the first mask is used to perform the first exposure, the first strip ^ 201227825 402 and the lower first photoresist layer 3 8 are opposite to each other. The first strip pattern 402 They are ten and ten in each other. It can be understood that the area where the first first resist layer 308 overlaps with the first strip patterns 402 is not exposed in the first step, and the other & fields are exposed. Then, a "first development" is performed: Α ω ^ 杈 u removes the first photoresist layer 308 which is not covered by the first strip 402 pattern. Next, as shown in FIG. 6, a second first resist layer 309 is formed on the patterned first photoresist layer, and then a planarization process is performed to form the first photoresist layer and the second photoresist layer 309. As shown in FIG. 6 , the second photoresist layer 309 includes a positive photoresist material, and the first photoresist layer and the second photoresist layer are incompatible with each other. Next, as shown in FIG. 7, the second photoresist step 309 is subjected to a second exposure step using a second photo-shade layer 309, wherein the second photomask has a plurality of second strip-like patterns parallel to each other in a longitudinal lake. . In the present invention, each of the first strip patterns 402 intersects each of the second long line patterns 4〇4, for example, at a degree of intersection or 6 degrees, in the embodiment of the present invention. The first elongated strip pattern is intersected with each of the second strip patterns to intersect at 9G degrees. The _ which is not covered by the first strip pattern 402 and the second strip pattern 404 is called a zone fairy. Since the light source used in the second exposure step only acts on the two photoresist layers 3〇9 without acting on the first photoresist layer, so only the second photoresist layer 3〇9 in the region D is Will be exposed. Next, please refer to the 8th and 9th, and the 9th is the diagram along the μ, tangent line 201227825 in Figure 8. As shown in FIG. 8 and the ninth riding, a second developing process is performed, and the photoresist layer 309 of the spear, article or t is transferred to obtain a patterned photoresist layer 31, wherein the patterned photoresist layer is formed. The 31 lanthanide layer includes a first photoresist layer 3 〇 8 and a second photoresist layer. The patterned photoresist layer 31 has a plurality of regular arrays (four) arranged in an aperture 312. It is said that only the apertures in the first region will extend at the bottom to expose the lower interface. The electrical layer is 3〇2. The opening hole other than the first region is blocked by the blocking layer 306 at the bottom thereof, and thus does not extend into the dielectric layer 3〇2. Φ In addition, the patterned photoresist layer 31 is formed by using two layers of mutually incompatible first photoresist layer 308 and second photoresist layer 3〇9 in two exposures and two developments, but In another aspect of the present invention, the light-emitting layer can be used in combination with double exposure and one-image development, or directly in the third light mask having the first long pattern 4〇2 plus the second long pattern (Fig. A patterned photoresist layer 310 having an array arrangement shape can be obtained by directly performing an exposure process. Alternatively, the patterned photoresist layer of the present invention may be formed in other manners, and any method of forming a patterned photoresist layer 310 having a regular array arrangement should be a mode of the present invention. Then, as shown in FIG. 00, the patterned photoresist layer 31 is used as a mask, and an etching step is performed to form a plurality of via layers in the dielectric layer 3〇2 in the first region 4〇〇. Hole 314. Then, the patterned photoresist layer is removed. Next, please refer to the u-th and a-th diagrams. Figure 12 is a schematic diagram of the tangential line along the line in the u-th image. Finally, the resist layer 306 is removed to obtain a dielectric layer 3〇2 having a plurality of via holes, and the locations of the via holes 314 are only located in the first region 4〇〇. . 201227825 In the above description, the present invention uses a patterned barrier layer before the step of forming a via hole, so that the via hole can be formed only in the region to be formed (ie, the first region). 'Inside' and not formed in other areas. Therefore, the present invention can be formed by a process of double exposure to form a via hole having a smaller aperture. The H-face can also be finely arranged on an integrated circuit layout having irregularly arranged via holes. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 2 are green diagrams showing the steps of the method for forming a via hole according to the present invention. 3〇〇302 304 306 308 309 [Description of main component symbols] Base dielectric barrier layer patterned barrier layer First photoresist layer Second photoresist layer 310 Patterned photoresist layer 312 Opening 314 Via hole 400 First region 402 first strip pattern 404 second strip pattern