JPH0466097B2 - - Google Patents
Info
- Publication number
- JPH0466097B2 JPH0466097B2 JP60117103A JP11710385A JPH0466097B2 JP H0466097 B2 JPH0466097 B2 JP H0466097B2 JP 60117103 A JP60117103 A JP 60117103A JP 11710385 A JP11710385 A JP 11710385A JP H0466097 B2 JPH0466097 B2 JP H0466097B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- layer
- film
- heat treatment
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229920003986 novolac Polymers 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000006096 absorbing agent Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に
多層レジスト法において、下層レジストの平坦化
と、上層レジストのパターニング時における下地
膜の反射の影響を防止できるレジストパターンの
形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a multilayer resist method, the flattening of a lower resist layer and the influence of reflection of a base film during patterning of an upper resist layer. The present invention relates to a method for forming a resist pattern that can prevent the above.
従来、この種の多層レジスト法は、下層レジス
トを平坦にするために、段差の３倍以上の膜厚を
塗布しなければならず、また、下地膜の光の反射
の影響をなくすため、反射防止膜や吸光剤を添加
する必要がある。
Conventionally, in this type of multilayer resist method, in order to flatten the lower layer resist, it was necessary to apply a film three times or more thicker than the difference in level. It is necessary to add a protective film or light absorbing agent.
上述した従来の方法は、下層レジストの平坦性
が悪いため、一般に段差の３倍以上も厚く塗布し
なければならず、微細パターンの形成がむずかし
くなり、また、下地膜や段差の影響で上層レジス
トのパターン形成においてくひれ等の発生を防止
するため、段差を有する基板にあらかじめ反射防
止膜の塗布するとか、又は下層レジストに吸光剤
の添加が必要であるなどの欠点を有していた。
In the conventional method described above, the flatness of the lower layer resist is poor, so the coating must be applied thicker than three times as thick as the level difference, making it difficult to form a fine pattern. In order to prevent the occurrence of fins and the like during pattern formation, it is necessary to apply an antireflection film to a substrate having steps in advance, or to add a light absorbing agent to the lower resist layer.
本発明は、上述した欠点を除去し、下層レジス
トの膜厚を極端に厚くすることなく、また下層レ
ジスト膜に吸光剤を添加することもなく、また反
射防止膜の塗布工程も必要もなく、多層レジスト
法で微細レジストパターンが形成できる半導体装
置の製造方法を提供することを目的とする。 The present invention eliminates the above-mentioned drawbacks, eliminates the need to make the lower resist film extremely thick, does not require the addition of a light absorbing agent to the lower resist film, and eliminates the need for an anti-reflection film coating process. An object of the present invention is to provide a method for manufacturing a semiconductor device in which a fine resist pattern can be formed using a multilayer resist method.
本発明の半導体装置の製造方法は、多層レジス
ト法を用いて微細なレジストパターンを形成する
半導体装置の製造方法において、下層レジストと
してノボラツク樹脂系のレジストを塗布する工程
と、350nm〜450nmの波長の光を照射する工程
と、その後熱処理をほどこす工程とを含んで構成
される。
The method of manufacturing a semiconductor device of the present invention includes a step of applying a novolak resin-based resist as a lower layer resist, and a step of applying a novolak resin resist with a wavelength of 350 nm to 450 nm. The method includes a step of irradiating light and then a step of applying heat treatment.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図ａ〜ｆは、本発明の一実施例の縦断面図
である。 1a to 1f are longitudinal sectional views of an embodiment of the present invention.
まず、第１図ａに示す段差を有する半導体基板
１上に第１図ｂに示すように、1μm〜2μm厚のノ
ボラツク樹脂系の下層レジスト２を塗布し、
350nm〜450nmの波長のUV照射３を行い、その
後150℃〜200℃の熱処理を行うと、第１図ｃの様
に平坦な下層レジスト４ができる。 First, as shown in FIG. 1b, a novolak resin-based lower resist 2 having a thickness of 1 μm to 2 μm is applied onto a semiconductor substrate 1 having a step shown in FIG. 1a, and
When UV irradiation 3 with a wavelength of 350 nm to 450 nm is performed, and then heat treatment is performed at 150° C. to 200° C., a flat lower resist layer 4 is formed as shown in FIG. 1c.
次に第１図ｄに示すように中間層（SiO2等）
５を形成し、その上に0.5μm以下の厚さの上層レ
ジスト６を塗布し、第１図ｅに示すように、パタ
ーニングを行う。次いで、そのレジストパターン
６をマスクとして、中間層５をエツチングする。 Next, as shown in Figure 1d, an intermediate layer (SiO 2 etc.) is added.
5 is formed, an upper resist layer 6 having a thickness of 0.5 μm or less is applied thereon, and patterning is performed as shown in FIG. 1e. Next, the intermediate layer 5 is etched using the resist pattern 6 as a mask.
次に、上層レジスト６と中間層をマスクとし
て、下層レジスト４をO2RIEを用いてエツチング
すると、第１図ｆに示すような微細なパターンを
段差上に形成することができる。 Next, by etching the lower resist 4 using O 2 RIE using the upper resist 6 and the intermediate layer as masks, a fine pattern as shown in FIG. 1f can be formed on the step.
以上の工程において、ノボラツク樹脂系の樹脂
は塗布後UV照射を行うとレジストの結合に変化
を来し次の熱処理で動き易くなる。このUV照射
後の熱処理により膜厚は薄くても移動により平坦
化され、それに加えて光の透過率をさげることが
出来、上層レジストのパターン化に際し、下地膜
や段差の影響を防止できる。 In the above process, when the novolak resin is exposed to UV irradiation after coating, the bonding of the resist changes, making it easier to move during the next heat treatment. This heat treatment after UV irradiation allows the film to be moved and flattened even if it is thin, and in addition to this, it is possible to reduce the light transmittance and prevent the effects of the base film and steps when patterning the upper resist layer.
以上説明したように本発明は、下層レジストに
ノボラツク樹脂系のレジストを使用し、350nm〜
450nmの波長のUV照射を行い、熱処理をするこ
とにより、膜が薄くても下層レジストの平坦化が
容易であり、かつ、上層レジストをパターニング
する上での下地膜や段差の影響を防止でき、微細
パターンの形成が正確でかつ容易となるという効
果が得られる。
As explained above, the present invention uses a novolak resin resist for the lower layer resist, and
By performing UV irradiation with a wavelength of 450 nm and heat treatment, it is easy to flatten the lower resist layer even if the film is thin, and it is possible to prevent the effects of the base film and steps when patterning the upper resist layer. The effect is that the formation of fine patterns becomes accurate and easy.
第１図ａ〜ｆは本発明の一実施例の縦断面図で
ある。
１……半導体基板、２……塗布後の下層レジス
ト、３……UV照射、４……熱処理後の下層レジ
スト、５……中間層（SiO2）、６……上層レジス
ト。
FIGS. 1a to 1f are longitudinal sectional views of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Lower layer resist after coating, 3... UV irradiation, 4... Lower layer resist after heat treatment, 5... Intermediate layer (SiO 2 ), 6... Upper layer resist.
Claims (1)
ターンを形成する半導体装置の製造方法におい
て、下層レジストとしてノボラツク樹脂系のレジ
ストを塗布する工程と、350nm〜450nmの波長の
光を照射する工程と、その後熱処理をほどこす工
程とを含むことを特徴とする半導体装置の製造方
法。1. A method for manufacturing a semiconductor device that uses a multilayer resist method to form a fine resist pattern, which includes a step of applying a novolak resin-based resist as a lower layer resist, a step of irradiating light with a wavelength of 350 nm to 450 nm, and thereafter. 1. A method of manufacturing a semiconductor device, comprising the step of applying heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117103A JPS61276221A (en) | 1985-05-30 | 1985-05-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117103A JPS61276221A (en) | 1985-05-30 | 1985-05-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61276221A JPS61276221A (en) | 1986-12-06 |
| JPH0466097B2 true JPH0466097B2 (en) | 1992-10-22 |
Family
ID=14703474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60117103A Granted JPS61276221A (en) | 1985-05-30 | 1985-05-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61276221A (en) |
-
1985
- 1985-05-30 JP JP60117103A patent/JPS61276221A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61276221A (en) | 1986-12-06 |
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