JPH0828318B2 - Pattern formation method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a pattern forming method for a large scale integrated circuit.

[Prior Art] FIG. 2 is a side sectional view showing a conventional pattern forming method of this type, in which (1) is a stepped substrate.
(2) is a lower resist layer coated and baked so that the upper surface of the stepped substrate (1) is flat, and contains a dye that absorbs exposure light in order to prevent reflection from the stepped substrate (1). . (4) is SOG on the lower resist layer (2)
An intermediate layer obtained by applying and baking (spin-on-glass), and (5) is an upper resist layer thinly applied and baked on the intermediate layer (4).

A method of processing a resist having such an arrangement is given as follows.

After forming the step substrate (1) to the upper resist layer (5) as shown in FIG. 2 (a), the upper resist layer (5) is exposed and developed as shown in (b) to form a pattern. . Next, as shown in (c), using the upper resist layer (5) as a mask, a gas containing CF ₄ as a main component is used to form the intermediate layer (4).
Anisotropic plasma etching. Further, as shown in (d), the lower resist layer (2) is anisotropically etched with a gas containing O ₂ as a main component using the intermediate layer (4) as a mask. Finally, as shown in (e), the stepped substrate (1) is etched using the lower resist layer (2) as a mask.

[Problems to be Solved by the Invention] In the conventional pattern forming method as described above, in order to increase the etching selection ratio with respect to the stepped substrate (1),
Only the material containing a novolac resin as a main component was used for the lower resist layer (2). Therefore, O ₂ shown in (d)
In the anisotropic etching process using a gas, the etching rate becomes small, and thus the process (d) becomes a main cause of reducing the overall throughput, which makes it difficult to put the pattern forming method into practical use.

The present invention has been made in order to solve such a problem, and a pattern capable of increasing the etching rate for the lower resist layer without impairing the etching selection ratio at the time of etching with a stepped substrate and improving the throughput The purpose is to obtain a forming method.

[Means for Solving the Problem] A pattern forming method according to the present invention includes a step of applying a first resist layer containing PMMA having a large etching rate by anisotropic plasma as a main component on a substrate to be processed and baking the same. A baking step of applying a second resist layer containing a novolac resin as a main component, which has anisotropic plasma etching resistance and large absorption of exposure wavelength, on the first resist layer; and baking on the second resist layer. Spin-on graph) coating and baking, and the third main component of the SOG is a novolac resin as the main component and a high resolution.
A step of applying a resist layer and baking, a step of patterning the third resist layer by exposure and development, a step of processing SOG by anisotropic plasma etching using the patterned third resist layer as a mask, It comprises a step of processing the second resist layer and the first resist layer by anisotropic plasma etching using the SOG as a mask, and a step of processing the substrate to be processed using the processed first resist layer and the second resist layer as a mask. It is a thing.

[Operation] In the present invention, the lower layer resist is divided into two layers, and
PMMA is applied to the layer and then baked, and the second layer is applied with a resist containing a novolac resin as a main component containing a conventional dye that absorbs an exposure wavelength and baked. At this time, the planarization and etching rate are increased by using PMMA for the first lower layer.

[Embodiment] FIG. 1 is a side sectional view showing an embodiment of a pattern forming method according to the present invention, and (1) is the same as the above. (2 ') is a first resist layer mainly composed of PMMA, which is applied on the stepped substrate (1) and is baked and has a large etching rate in anisotropic plasma etching.
(3 ') is a second resist layer coated on the first resist layer (2') and having a small etching rate in baking anisotropic plasma etching, and contains a dye that absorbs the exposure wavelength. (4 ') is applied on the second resist layer (3') and baked on SOG (spin on glass), and (5 ') is applied on the SOG (4') thinly and baked on high resolution. It is a resist having properties.

 The method of coating these resists is as follows.

First, a first resist layer (2 ') containing PMMA having a large etching rate of anisotropic plasma etching as a main component is applied on the stepped substrate (1) until the upper surface of the resist is flat, and then baking is performed. Next, a second resist layer (3 ') containing a dye absorbing an exposure wavelength and having a small etching rate in anisotropic plasma etching is formed on the first resist layer (2'). ) Is applied until the combined thickness has a mask property for etching the step substrate (1), and then baking is performed. Furthermore, SO
After G (4 ') is applied, baking is performed, and a resist (5') having high resolution is thinly applied thereon and baking is performed.

Thus, first, as shown in FIG. 1B, the resist (5 ′) is exposed and developed to form a pattern on the resist applied as shown in FIG. 1A. Then, using the patterned resist (5 ') as a mask, plasma etching is performed on the SOG (4') with a gas containing CF ₄ gas as a main component as shown in (c). Further, using the etched SOG (4 ') as a mask, O ₂ is applied to the first and second resist layers (2') and (3 ') as shown in (d).
Anisotropic etching is performed with a gas containing as a main component. Finally, each etched resist layer (2 '),
Etching is performed on the stepped substrate (1) as shown in (e) using (3 ′) as a mask.

[Effects of the Invention] As described above, the present invention comprises a step of coating and baking a first resist layer containing PMMA having a large etching rate by anisotropic plasma as a main component on a substrate to be processed,
The step of applying a second resist layer containing a novolak resin as a main component, which has anisotropic plasma etching resistance and has large absorption for an exposure wavelength, is provided on the first resist layer, so that the first resist layer is flattened. And an increase in etching rate can be realized, and the masking property of the substrate etching can be obtained by the second resist layer.
There is an effect that a pattern can be formed with high throughput.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an embodiment of the present invention, and FIG. 2 is a side sectional view showing a conventional pattern forming method. In the figure, (1) is a stepped substrate (substrate to be processed),
(2 ') is a first resist layer, (3') is a second resist layer, (4 ') is SOG, and (5') is a resist. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/302 HJ

Claims (1)

[Claims] 1. A step of coating and baking a first resist layer containing PMMA, which has a large etching rate by anisotropic plasma, as a main component on a substrate to be processed and baking, and anisotropic plasma etching resistance on the first resist layer. Having a novolac resin as a main component, which has a large absorption of the exposure wavelength
A step of applying a resist layer and baking, a step of applying and baking SOG (spin-on-glass) on the second resist layer, and a third resist layer containing novolac resin as a main component on the SOG and having a high resolution. Is applied and baked, the third resist layer is patterned by exposure and development, the SOG is processed by anisotropic plasma etching using the patterned third resist layer as a mask, and the processed A step of processing the second resist layer and the first resist layer by anisotropic plasma etching using the SOG as a mask, and a step of processing the substrate to be processed using the processed first resist layer and the second resist layer as a mask And a pattern forming method comprising: