JPH03104113A - Formation of resist pattern - Google Patents
Formation of resist patternInfo
- Publication number
- JPH03104113A JPH03104113A JP1241313A JP24131389A JPH03104113A JP H03104113 A JPH03104113 A JP H03104113A JP 1241313 A JP1241313 A JP 1241313A JP 24131389 A JP24131389 A JP 24131389A JP H03104113 A JPH03104113 A JP H03104113A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- resist film
- intermediate layer
- film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims description 8
- 239000010408 film Substances 0.000 abstract description 35
- 239000010409 thin film Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
く産業上の利用分野〉
本発明は段差を有する基板（例えばＳｉ）へのパターン
形成方法に関し，安定，確実なパターニングにより精度
向上をはかったレジストパターンの形成方法に関する．
〈従来の技術〉
段差のある基板へのレジストパターンの形成は多層レジ
スト法を用いて行われる．この多層レジスト法には３層
レジスト法，２層レジスト法，ＰＣ Ｍ （ Ｐｏｒｔ
ａｂｌｅ Ｃｏｎｆｏｒｎａｂｌｅ Ｈａｓｋｉｎｇ）
法等が知られている。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming a pattern on a substrate (for example, Si) having steps, and more particularly, to a method for forming a resist pattern that improves accuracy through stable and reliable patterning. <Conventional technology> A multilayer resist method is used to form a resist pattern on a substrate with steps. This multi-layer resist method includes three-layer resist method, two-layer resist method, PCM (Port
Conformable Hasking)
The law is known.
第２図（ａ）〜（ｆ）は３層レジスト法を示す概略工程
図である．工程に従って説明する．（ａ）段差を有する
基板１上に第１のレジスト膜２を形成する工程．
（ｂ）前記第１のレジスト膜２上にＳｉ０２などの中間
層３を形成する工程．
（ｃ）前記中間層３の上に第２のレジスト膜４を形成す
る工程．
（ｄ）前記第２のレジスト膜４を露光・現像によりパタ
ーニングし前記中間層３を露出させる工程．（ｅ）前記
第２のレジスト膜４をマスクとして前記中間層３をフロ
ロカーボン（ＣＦ４）系ＲＩＥ（反応性イオンエッチン
グ）により除去し前記第１のレジスト膜２を露出させる
工程．
（ｆ）前記第２のレジスト１１！４および中間層３をマ
スクとして０２系ＲＩＥにより前記第１のレジスト膜２
を除去し前記基板１を露出させる工程．第３図（ａ）〜
（ｄ）は２層レジスト法を示す概略工程図である．工程
に従って説明する．（ａ）段差を有する基板１上に第１
のレジスト膜２を形成する工程．
（ｂ）前記第１のレジスト膜２上に第２のレジストＭ４
を形成する工程。FIGS. 2(a) to 2(f) are schematic process diagrams showing the three-layer resist method. I will explain the process step by step. (a) Step of forming a first resist film 2 on a substrate 1 having a step. (b) Step of forming an intermediate layer 3 such as Si02 on the first resist film 2. (c) Step of forming a second resist film 4 on the intermediate layer 3. (d) A step of patterning the second resist film 4 by exposure and development to expose the intermediate layer 3. (e) Using the second resist film 4 as a mask, the intermediate layer 3 is removed by fluorocarbon (CF4)-based RIE (reactive ion etching) to expose the first resist film 2. (f) The first resist film 2 is formed by 02-based RIE using the second resist 11!4 and the intermediate layer 3 as a mask.
a step of removing and exposing the substrate 1. Figure 3(a)~
(d) is a schematic process diagram showing the two-layer resist method. I will explain the process step by step. (a) A first plate is placed on a substrate 1 having steps.
Step of forming resist film 2. (b) A second resist M4 is formed on the first resist film 2.
The process of forming.
（ｃ）前記第２のレジスト膜４を露光・現像によりバタ
ーニングし前記第１のレジスト膜２を露出させる工程。(c) A step of patterning the second resist film 4 by exposure and development to expose the first resist film 2.
（ｄ）前記第２のレジスト膜４をマスクとして０２系Ｒ
ＩＥにより前記第１のレジスト膜２を除去し前記基板１
を露出させる工程．
第４図（ａ）〜（ｄ）はＰＣＭ法を示す概略工程図であ
る．この工程は２層レジスト法と同様であるが，第１の
レジストｆｔｌＡ２としてＤＵＶ（ＤｅｅｐＵｌｔｒａ
Ｖｉｏｌｅｔ）系レジストを用いる点が異なってお
り，工程（Ｃ）で第２のレジスト膜４を露光・現像によ
りバターニングした後，工程（ｄ）ではＤＵＶ光を全面
照射した後現像によって第１のレジスト膜を除去する，
く発明が解決しようとする課題〉
しかしながら．上記従来のパターン形成方法においては
次のような問題があった．
■３層．２層レジスト法においては第１のレジストを除
去する際に０２ＲＩＥを用いるが．このとき０２イオン
により叩き出されたレジストのボリマーがマスクとして
残る第１のレジスト３の測面や露出した基板に付着する
。これは次の工程で基板にスバッタや蒸着などを行うよ
うな場合の障害となる．
■また，ＰＣＭ法においては第１，第２のレジスト層が
混合する恐れがあり，精密なパターン形成には問題があ
る．
本発明は上記従来技術の問題点にに鑑みて成されたもの
で，安定，確実なパターニングにより精度向上をはかっ
たレジストパターンの形或方法を実現する事を目的とす
る．
〈課題を解決するための手段〉
上記課題を解決するための本発明の構成は，レジストパ
ターンの形成方法において，
段差を有する基板上に表面が平らな第１のレジスト膜を
形成する工程と．前記第１のレジスト膜上に露光光を反
射または吸収する中間層を形成する工程と，前記中間層
上に第２のレジスト膜を形成する工程と，前記第２のレ
ジスト膜をパターニングして前記中間層を露出させる工
程と，前記第２のレジストパターンをマスクとして前記
中間層を除去する工程と，前記中間層をマスクとして前
記第１のレジスト膜を全面露光・現像を行うことにより
除去する工程を含んで形成された事を特徴とするもので
ある．
く作用〉
第１のレジストと第２のレジストの間に光を反射または
吸収する中間層を設けたので．第１のレジストを除去す
る際も露光・現像を用いる事が出来る．
〈実施例〉
以下．本発明のレジストパターンの形成方法について図
面を参照して説明する．第１図（ａ）〜（ｆ）は本発明
の一実施例の構成を示す概略製作工程図である．工程に
従って説明する。(d) 02 series R using the second resist film 4 as a mask
The first resist film 2 is removed by IE and the substrate 1 is removed.
The process of exposing Figures 4(a) to 4(d) are schematic process diagrams showing the PCM method. This process is similar to the two-layer resist method, but DUV (Deep Ultra) is used as the first resist ftlA2.
The difference is that a Violet-based resist is used, and after the second resist film 4 is patterned by exposure and development in step (C), the first resist film 4 is patterned by irradiating the entire surface with DUV light and then developed in step (d). Problems that the invention attempts to solve by removing the resist film However,. The conventional pattern forming method described above had the following problems. ■3 layers. In the two-layer resist method, 02RIE is used to remove the first resist. At this time, the polymer of the resist ejected by the 02 ions adheres to the surface of the first resist 3 remaining as a mask and to the exposed substrate. This becomes an obstacle when sputtering or vapor deposition is performed on the substrate in the next process. ■Also, in the PCM method, there is a risk that the first and second resist layers may mix, which poses a problem in forming precise patterns. The present invention was made in view of the problems of the prior art described above, and aims to realize a resist pattern shape or method that improves accuracy through stable and reliable patterning. <Means for Solving the Problems> The structure of the present invention for solving the above problems is as follows: A method for forming a resist pattern includes a step of forming a first resist film with a flat surface on a substrate having a step. forming an intermediate layer that reflects or absorbs exposure light on the first resist film; forming a second resist film on the intermediate layer; patterning the second resist film to a step of exposing the intermediate layer; a step of removing the intermediate layer using the second resist pattern as a mask; and a step of removing the first resist film by exposing and developing the entire surface using the intermediate layer as a mask. It is characterized by being formed by including. Effect> An intermediate layer that reflects or absorbs light is provided between the first resist and the second resist. Exposure and development can also be used to remove the first resist. <Example> Below. A method for forming a resist pattern according to the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(f) are schematic manufacturing process diagrams showing the configuration of an embodiment of the present invention. The process will be explained step by step.
工程（ａ）
段差を有するシリコン基板１の表面にスビナを用いて３
μｍ程度の厚さに第１のレジスト２を塗布して表面を平
滑にする．
工程（ｂ）
第１のレジスト膜２上にスパッタや蒸着等より光を反射
する中間層３ａとしてＡｌ薄膜を０．１μｍ程度の厚さ
に形成する．
■程（ｃ）
そのＡ／薄膜３ａの上に厚さ１μｍ程度の第２のレジス
ト膜４を形成する．
工程（ｄ）
第２のレジスト膜４を通常のフォトリソ工程を用いて露
光・現像し，レジストパターン領域５を形成してＡ１薄
膜３ａを露出させる．
工程（ｅ）
第２のレジスト膜４をマスクとしてＡ ｌ 薄１１ａ
３ａをエッチングにより除去する。Step (a) Using a subina on the surface of the silicon substrate 1 having steps, 3
The first resist 2 is applied to a thickness of about μm to make the surface smooth. Step (b) A thin Al film with a thickness of about 0.1 μm is formed as a light-reflecting intermediate layer 3a on the first resist film 2 by sputtering, vapor deposition, or the like. (c) A second resist film 4 with a thickness of about 1 μm is formed on the A/thin film 3a. Step (d) The second resist film 4 is exposed and developed using a normal photolithography process to form a resist pattern region 5 and expose the A1 thin film 3a. Step (e) Al thin layer 11a using the second resist film 4 as a mask
3a is removed by etching.
工程（ｆ）
Ａｌ薄膜３ａをマスクとして露光・現ｉＩＡｔｅ行い第
１のレジスト１２を除去する。Step (f) Using the Al thin film 3a as a mask, exposure and development are performed to remove the first resist 12.
なお，本実施例においては中間層としてＡＩ薄膜を用い
たが，Ａｌ薄膜に限ることなく光を反射または吸収する
部材であれば良い．
〈発明の効果〉
以上，実施例とともに具体的に説明したように本発明の
レジストのパターニング方法によれば，第１のレジスト
と第２のレジストの間に光を反射または吸収する中間層
を設けたので，第１のレジストを除去する際も露光・現
像を用いる事が出来安定．ｉ実に精度の良いパターンを
形成する事が出来る。Although an AI thin film was used as the intermediate layer in this example, it is not limited to an Al thin film, and any material that reflects or absorbs light may be used. <Effects of the Invention> As specifically explained above in conjunction with the examples, according to the resist patterning method of the present invention, an intermediate layer that reflects or absorbs light is provided between the first resist and the second resist. Therefore, exposure and development can be used to remove the first resist and it is stable. It is possible to form patterns with very high precision.
第１図は本発明のレジストパターンの形成方法の一実施
例を示す概略工程図，第２図〜第４図は従来のバターニ
ング方法の概略工程を示す図である．
１・・・シリコン基板，２・・・第１のレジスト膜，３
・・・中間層，４・・・第２のレジスト膜，５・・・パ
ターン第 １ 図
泰２図
第３図FIG. 1 is a schematic process diagram showing an embodiment of the resist pattern forming method of the present invention, and FIGS. 2 to 4 are diagrams showing schematic steps of a conventional patterning method. 1... Silicon substrate, 2... First resist film, 3
...Intermediate layer, 4...Second resist film, 5...Pattern Fig. 1 Fig. 2 Fig. 3
Claims (1)
膜を形成する工程と、 ２）前記第１のレジスト膜上に露光光を反射または吸収
する中間層を形成する工程と、 ３）前記中間層上に第２のレジスト膜を形成する工程と
、 ４）前記第２のレジスト膜をパターニングして前記中間
層を露出させる工程と、 ５）前記第２のレジストパターンをマスクとして前記中
間層を除去する工程と、 ６）前記中間層をマスクとして前記第１のレジスト膜を
全面露光・現像を行うことにより除去する工程。[Claims] A method for forming a resist pattern including the following steps. 1) forming a first resist film with a flat surface on a substrate having steps; 2) forming an intermediate layer that reflects or absorbs exposure light on the first resist film; 3) forming a second resist film on the intermediate layer; 4) patterning the second resist film to expose the intermediate layer; 5) using the second resist pattern as a mask to expose the intermediate layer; 6) removing the first resist film by exposing and developing the entire surface of the first resist film using the intermediate layer as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1241313A JPH03104113A (en) | 1989-09-18 | 1989-09-18 | Formation of resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1241313A JPH03104113A (en) | 1989-09-18 | 1989-09-18 | Formation of resist pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104113A true JPH03104113A (en) | 1991-05-01 |
Family
ID=17072436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1241313A Pending JPH03104113A (en) | 1989-09-18 | 1989-09-18 | Formation of resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104113A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0792688A (en) * | 1990-02-26 | 1995-04-07 | Applied Materials Inc | Method of multilayer photoresist etching |
| US7354699B2 (en) | 2001-11-06 | 2008-04-08 | Hitachi Metals, Ltd. | Method for producing alignment mark |
-
1989
- 1989-09-18 JP JP1241313A patent/JPH03104113A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0792688A (en) * | 1990-02-26 | 1995-04-07 | Applied Materials Inc | Method of multilayer photoresist etching |
| US7354699B2 (en) | 2001-11-06 | 2008-04-08 | Hitachi Metals, Ltd. | Method for producing alignment mark |
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