JPS59163828A - Formation of fine pattern - Google Patents
Formation of fine patternInfo
- Publication number
- JPS59163828A JPS59163828A JP3848683A JP3848683A JPS59163828A JP S59163828 A JPS59163828 A JP S59163828A JP 3848683 A JP3848683 A JP 3848683A JP 3848683 A JP3848683 A JP 3848683A JP S59163828 A JPS59163828 A JP S59163828A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- intermediate layer
- forming
- fine pattern
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000004793 Polystyrene Substances 0.000 claims abstract description 3
- 229920002223 polystyrene Polymers 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000005416 organic matter Substances 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、微細ノ９ターンの形成方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for forming nine fine turns.
従来の微細パターンの形成方法は、凹凸の表面を有する
半導体基板上に、所望の微細パターンを形成する場合、
次のようにして行われている。先ず、第１図（４）に示
す如く、凹凸部１を有する半導体基板２の表面に、レゾ
スト膜３を十分に厚肉に形成して表面を平坦化する。レ
ジスト膜３の平坦な表面上に中間層として例えばシリコ
ン酸化膜４を形成する。次いで、シリコン酸化膜４上に
再びレジスト膜５を形成する。このレゾスト膜５に周知
の写真蝕刻法にて・母ターニングを施す。In the conventional method of forming a fine pattern, when forming a desired fine pattern on a semiconductor substrate having an uneven surface,
This is done as follows. First, as shown in FIG. 1(4), a sufficiently thick resist film 3 is formed on the surface of the semiconductor substrate 2 having the uneven portion 1 to flatten the surface. For example, a silicon oxide film 4 is formed as an intermediate layer on the flat surface of the resist film 3. Next, a resist film 5 is formed again on the silicon oxide film 4. This resist film 5 is subjected to main turning using a well-known photolithography method.
次に、パターニングされたレジスト膜５′をマスクにし
てシリコン酸化膜４をパターニングする。更に、このパ
ターニングされたシリコン酸化膜４′をマスクにして、
その直下のレジスト膜３′が残存するように、第１図（
Ｂ）に示す如くパターニングを施し、微細パターンを得
る。Next, the silicon oxide film 4 is patterned using the patterned resist film 5' as a mask. Furthermore, using this patterned silicon oxide film 4' as a mask,
As shown in Fig. 1 (
Patterning is performed as shown in B) to obtain a fine pattern.
このように従来の微細パターンの形成方法では、中間層
であるシリコン酸化膜４の形成後に、その上方に形成し
たレジスト膜５をパターニングするためのマスク合せ作
業を必要とする。このため、中間層をシリコン酸化膜４
や９化膜の如く、透明か部材で形成する必要がある。そ
の結果、中間層の材質が制限されるので、製造が困難で
あると共に、製造コストを高くする。また、有機膜であ
るレジスト膜３上に、酸化膜や窒化膜を形成するのが困
難であり、作業性を低下する。As described above, the conventional method for forming fine patterns requires a mask alignment operation for patterning the resist film 5 formed above the silicon oxide film 4, which is an intermediate layer, after the silicon oxide film 4 is formed. For this reason, the intermediate layer is made of silicon oxide film 4.
It is necessary to use a transparent material such as a 9-layer film or a 9-oxide film. As a result, the material of the intermediate layer is limited, making it difficult to manufacture and increasing the manufacturing cost. Furthermore, it is difficult to form an oxide film or a nitride film on the resist film 3, which is an organic film, which reduces workability.
本発明は、中間層に不透明な膜の使用を可能にして、製
造を容易にすると共に製造コストの低減を達成した微細
パターンの形成方法を提供することをその目的とするも
のである。An object of the present invention is to provide a method for forming a fine pattern that allows the use of an opaque film as an intermediate layer, facilitates manufacturing, and reduces manufacturing costs.
本発明は、レジスト膜の形成後に中間層を形成し、その
パターニングを行うことにより、中間層に不透明な膜の
使用を可能にして、製造を容易にすると共に製造コスト
の低減を達成した微細パターンの形成方法である。By forming an intermediate layer after forming a resist film and patterning the intermediate layer, the present invention enables the use of an opaque film for the intermediate layer, thereby facilitating manufacturing and reducing manufacturing costs. This is the formation method.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
先ず、第２図（Ａ）に示す如く、表面に多数の凸部１１
を有する半導体基板１２を用意する。この半導体基板１
２の表面に、例えばポリスチレンを主成分とする有機物
を回転塗布法で厚さ約１．５μｍ塗布し、表面の平坦な
下地層１３を形成する。First, as shown in FIG. 2(A), a large number of convex portions 11 are formed on the surface.
A semiconductor substrate 12 is prepared. This semiconductor substrate 1
2, an organic material containing polystyrene as a main component is applied to a thickness of about 1.5 μm by a spin coating method to form a base layer 13 with a flat surface.
次いで、下地層１３を乾燥させた後、その表面にレゾス
トを回転塗布法で厚さ１μｍ塗布してレジスト膜１４を
形成する。このレジスト膜１４に感光、現像等を行い同
図（Ｂ）に示す如く、パターニング処理を施す。Next, after drying the base layer 13, a resist film 14 is formed by coating the surface of the base layer 13 with a thickness of 1 μm using a spin coating method. This resist film 14 is exposed to light, developed, and subjected to a patterning process as shown in FIG. 3(B).
次いで、同図（Ｃ）に示す如く、パターニングされたレ
ジスト膜１４の表面及び露出した下地層１３上に、例え
ばアルミニウムを真空蒸着法またはスパッタリング法に
て厚さ約３０００１堆積し、中間層１５ａ、１５ｂとす
る。ここで、半導体基板１２に向って飛来して来るアル
ミニウム粒子は、可能彦限シ基板面に対して垂直に飛来
するように設定する。また、中間層１５ａが形成される
下地膜Ｊ３と、半導体基板１２は冷却しておくのが望ま
しい。このような操作によって、堆積するアルミニウム
粒子のステップカパレイジを極端に悪くし、下地膜１３
上の中間層１５ｈとレジスト膜１４上の中間層１５ｂと
を分離するものである。Next, as shown in FIG. 2C, aluminum is deposited to a thickness of about 30,000 mm on the surface of the patterned resist film 14 and the exposed base layer 13 by vacuum evaporation or sputtering to form an intermediate layer 15a, 15b. Here, the aluminum particles flying toward the semiconductor substrate 12 are set to fly perpendicularly to the substrate surface within the maximum possible range. Further, it is desirable that the base film J3 on which the intermediate layer 15a is formed and the semiconductor substrate 12 be cooled. Such an operation makes the step coverage of the deposited aluminum particles extremely bad, and the base film 13
This is to separate the upper intermediate layer 15h from the intermediate layer 15b on the resist film 14.
次に、レジスト膜１４を所定の除去液で除去し、その上
に載置した中間層１５ｂをリフトオフによシ同時に除去
する。而して、下地膜１３上に所定パターンの状態で中
間層１５ａを同図（Ｄ）に示す如く、残存せしめる。Next, the resist film 14 is removed using a predetermined removal liquid, and the intermediate layer 15b placed thereon is simultaneously removed by lift-off. Thus, the intermediate layer 15a is left in a predetermined pattern on the base film 13, as shown in FIG.
次に、残存した中間層１５ｈをマスクにして５−
例えば０２プラズマにより下地膜１３に同図（匂に示す
如く、エツチングによる）臂ターニングを施す。なお、
中間層１５ａの材質としては、このプラズマエツチング
処理の際に、中間層１５ａと下地膜１３および基板との
選択比が十分に余裕をもってとれるように設定するのが
望ましい。Next, using the remaining intermediate layer 15h as a mask, the base film 13 is turned (by etching as shown in the figure) using, for example, 02 plasma. In addition,
The material of the intermediate layer 15a is desirably selected so that the selection ratio between the intermediate layer 15a and the base film 13 and the substrate can be sufficiently selected during this plasma etching process.
例えば、基板が酸化膜である場合は、中間層１５ａの材
質としては、アルミニウム、ポリシリコン、シリサイド
等の金属を使用するのが好ましい。基板がぼりシリコン
、シリサイド、アルミニウム等の金属で形成されている
場合には、中間層１５ｈは、酸化膜、窒化膜等で形成す
るのが好ましい。For example, when the substrate is an oxide film, it is preferable to use a metal such as aluminum, polysilicon, or silicide as the material for the intermediate layer 15a. When the substrate is made of metal such as silicon, silicide, or aluminum, the intermediate layer 15h is preferably formed of an oxide film, a nitride film, or the like.
このようにこの微細パターンの形成方法によれば、レジ
スト膜１４の除去処理によって中間層１５ｍ、１５ｂの
パターニングが行われる。As described above, according to this fine pattern forming method, the intermediate layers 15m and 15b are patterned by the process of removing the resist film 14.
このため、中間層１５ｈをパターニングするためのマス
ク工程を省略できる。しかも、中間層１５ａ、１５ｂの
材質として不透明の部材を使用することができる。その
結果、微細ノ４ターン６一
を有する半導体基板１２を容易に製造できると共に、製
造コストの低減を達成することができる。Therefore, a mask process for patterning the intermediate layer 15h can be omitted. Moreover, an opaque member can be used as the material for the intermediate layers 15a and 15b. As a result, it is possible to easily manufacture the semiconductor substrate 12 having four fine turns 61, and to achieve a reduction in manufacturing costs.
以上説明した如く、本発明に係る微細パターンの形成力
法によれば、中間層に不透明な膜を使用して製造を容易
にすると共に製造コストを低減させることができる等顕
著な効果を有するものである。As explained above, the fine pattern forming method according to the present invention has remarkable effects such as facilitating manufacturing and reducing manufacturing costs by using an opaque film as an intermediate layer. It is.
第１図（Ａ）及び同図（Ｂ）は、従来の微細パターンの
形成方法を工程順に示す説明図、第２図（Ａ）乃至同図
（匂は、本発明に係る微細パターンの形成方法を工程順
に示す説明図である。
１ノ・・・凸部、１２・・・半導体基板、１３・・・下
地層、１４・・・レジスト膜、１５ｇ，１５ｂ・・・中
間層。
出願人代理人 弁理士 鈴 江 武 彦７一
第１図
（Ａ）
（Ｂ）
９
Ｃ） ＣリFIGS. 1(A) and 1(B) are explanatory diagrams showing the conventional method for forming a fine pattern in the order of steps, and FIGS. It is an explanatory diagram showing the steps in the order of steps. 1 No. Convex portion, 12 Semiconductor substrate, 13 Foundation layer, 14 Resist film, 15g, 15b Intermediate layer. Applicant's representative Person Patent Attorney Takehiko Suzue 71 Figure 1 (A) (B) 9 C) Cli
Claims (3)
その表面が平坦になる厚さ分だけ形成する工程と、前記
下地膜上にレジスト膜を形成する工程と、前記レゾスト
膜にパターニングを施す工程と、パターニングされた前
記レジスト膜上及び露出した前記下地膜上に中間層を形
成する工程と、核中間層の一部分を前記レジスト膜とと
もに除去する工程と、残存した前記中間層をマスクにし
て前記下地膜にパターニングを施す工程とを具備するこ
とを特徴とする微細・ぐターンの形成方法。(1) A step of forming a base film on the main surface of the semiconductor substrate on which the uneven portion is formed to a thickness that makes the surface flat; a step of forming a resist film on the base film; a step of patterning, a step of forming an intermediate layer on the patterned resist film and the exposed base film, a step of removing a portion of the core intermediate layer together with the resist film, and a step of removing the remaining intermediate layer. A method for forming fine patterns, comprising the step of patterning the base film using a mask.
シリサイド、シリコン酸化物、シリコン窒化物の何れか
である特許請求の範囲第１項記載の微細パターンの形成
方法。(2) The material of the intermediate layer is aluminum, silicon,
The method for forming a fine pattern according to claim 1, which is made of any one of silicide, silicon oxide, and silicon nitride.
囲第１項または第２項記載の微細パターンの形成方法。(3) The method for forming a fine pattern according to claim 1 or 2, wherein the material of the base film is polystyrene.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3848683A JPS59163828A (en) | 1983-03-09 | 1983-03-09 | Formation of fine pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3848683A JPS59163828A (en) | 1983-03-09 | 1983-03-09 | Formation of fine pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59163828A true JPS59163828A (en) | 1984-09-14 |
| JPH0522380B2 JPH0522380B2 (en) | 1993-03-29 |
Family
ID=12526584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3848683A Granted JPS59163828A (en) | 1983-03-09 | 1983-03-09 | Formation of fine pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59163828A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841813A (en) * | 1971-09-27 | 1973-06-19 | ||
| JPS57143826A (en) * | 1981-02-28 | 1982-09-06 | Dainippon Printing Co Ltd | Formation of resist pattern on gapped semiconductor substrate |
| JPS5812344A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Semiconductor device |
-
1983
- 1983-03-09 JP JP3848683A patent/JPS59163828A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841813A (en) * | 1971-09-27 | 1973-06-19 | ||
| JPS57143826A (en) * | 1981-02-28 | 1982-09-06 | Dainippon Printing Co Ltd | Formation of resist pattern on gapped semiconductor substrate |
| JPS5812344A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0522380B2 (en) | 1993-03-29 |
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