JPH0522380B2 - - Google Patents
Info
- Publication number
- JPH0522380B2 JPH0522380B2 JP58038486A JP3848683A JPH0522380B2 JP H0522380 B2 JPH0522380 B2 JP H0522380B2 JP 58038486 A JP58038486 A JP 58038486A JP 3848683 A JP3848683 A JP 3848683A JP H0522380 B2 JPH0522380 B2 JP H0522380B2
- Authority
- JP
- Japan
- Prior art keywords
- intermediate layer
- film
- resist film
- forming
- fine pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000004793 Polystyrene Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、微細パターンの形成方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for forming fine patterns.
従来の微細パターンの形成方法は、凹凸部の表
面を有する半導体基板上に、所望の微細パターン
を形成する場合、次のようにして行われいてい
る。先ず、第１図Ａに示す如く、凹凸部１を有す
る半導体基板２の表面に、レジスト膜３を十分に
厚肉に形成して表面を平坦化する。レジスト膜３
の平坦な表面上に中間層として例えばシリコン酸
化膜４を形成する。次いで、シリコン酸化膜４上
に再びレジスト膜５を形成する。このレジスト膜
５に周知の写真蝕刻法にてパターンニングを施
す。
In a conventional method for forming a fine pattern, when a desired fine pattern is formed on a semiconductor substrate having an uneven surface, it is carried out as follows. First, as shown in FIG. 1A, a sufficiently thick resist film 3 is formed on the surface of a semiconductor substrate 2 having an uneven portion 1 to flatten the surface. Resist film 3
For example, a silicon oxide film 4 is formed as an intermediate layer on the flat surface of the substrate. Next, a resist film 5 is formed again on the silicon oxide film 4. This resist film 5 is patterned by a well-known photolithography method.
次にパターンニングされたレジスト膜５′をマ
スクにしてシリコン酸化膜４をパターニングす
る。更に、このパターンニングされたシリコン酸
化膜４′をマスクにして、その直下のレジスト膜
３′が残存するように、第１図Ｂに示す如くパタ
ーンニングを施し、微細パターンを得る。 Next, the silicon oxide film 4 is patterned using the patterned resist film 5' as a mask. Further, using this patterned silicon oxide film 4' as a mask, patterning is performed as shown in FIG. 1B so that the resist film 3' immediately below it remains, thereby obtaining a fine pattern.
このように従来の微細パターンの形成方法で
は、中間層であるシリコン酸化膜４の形成後に、
その上方に形成したレジスト膜５をパターンニン
グするためのマスク合せ作業を必要とする。この
ため、中間層をシリコン酸化膜４や窒化膜の如
く、透明な部材で形成する必要がある。その結
果、中間層の材質が制限されるので、製造が困難
であると共に、製造コストを高くする。また、有
機膜であるレジスト膜３上に、酸化膜や窒化膜を
形成するのが困難であり、作業性を低下する。
In this way, in the conventional method of forming fine patterns, after forming the silicon oxide film 4 as the intermediate layer,
A mask alignment operation is required to pattern the resist film 5 formed above. Therefore, it is necessary to form the intermediate layer with a transparent material such as silicon oxide film 4 or nitride film. As a result, the material of the intermediate layer is limited, making it difficult to manufacture and increasing the manufacturing cost. Furthermore, it is difficult to form an oxide film or a nitride film on the resist film 3, which is an organic film, which reduces workability.
〔発明の目的〕
本発明は、中間層に不透明な膜の使用を可能に
して、製造を容易にすると共に製造コストの低減
を達成した微細パターンの形成方法を提供するこ
とを目的とするものである。[Object of the Invention] An object of the present invention is to provide a method for forming a fine pattern that enables the use of an opaque film as an intermediate layer, thereby facilitating manufacturing and reducing manufacturing costs. be.
本発明の微細パターンの形成方法は、凹凸部を
有する基板上に微細なパターンを形成する際、前
記基板の凹凸部上に下地膜をその表面が平坦にな
る厚さ分だけ形成し、前記下地膜上にレジスト膜
を形成する。この後、前記レジスト膜をパターニ
ングし、当該パターニングされたレジスト膜上及
び露出した下地膜上に中間層を形成する。そし
て、前記中間層の一部分を前記パターンニングさ
れたレジスト膜とともに除去した後、残存した中
間層をマスクにして前記下地膜をパターンニング
するというものである。これにより、中間層に不
透明な膜の使用を可能にして、製造を容易にする
と共に製造コストの低減を達成した微細パターン
の形成方法である。
In the method for forming a fine pattern of the present invention, when forming a fine pattern on a substrate having an uneven part, a base film is formed on the uneven part of the substrate to a thickness that makes the surface flat. A resist film is formed on the ground film. Thereafter, the resist film is patterned, and an intermediate layer is formed on the patterned resist film and the exposed base film. Then, after removing a portion of the intermediate layer together with the patterned resist film, the underlying film is patterned using the remaining intermediate layer as a mask. This makes it possible to use an opaque film as an intermediate layer, thereby facilitating manufacturing and reducing manufacturing costs.
以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
先ず、第２図Ａに示す如く、表面に多数の凸部
１１を有する半導体基板１２を用意する。この半
導体基板１２の表面に、例えばポリスチレンを主
成分とする有機物を回転塗布法で厚さ約1.5μｍ塗
布し、表面の平坦な下地層１３を形成する。 First, as shown in FIG. 2A, a semiconductor substrate 12 having a large number of convex portions 11 on its surface is prepared. On the surface of this semiconductor substrate 12, an organic material mainly composed of polystyrene, for example, is applied to a thickness of about 1.5 μm by a spin coating method to form a base layer 13 with a flat surface.
次いで、下地層１３を乾燥させた後、その表面
にレジストを回転塗布法で厚さ1μｍ塗布してレ
ジスト膜１４を形成する。このレジスト膜１４に
感光、現像等を行い同図Ｂに示す如く、パターニ
ング処理を施す。 Next, after drying the base layer 13, a resist film 14 is formed by coating the surface of the base layer 13 with a thickness of 1 μm using a spin coating method. This resist film 14 is exposed to light, developed, and subjected to a patterning process as shown in FIG.
次いで、同図Ｃに示す如く、パターンニングさ
れたレジスト膜１４の表面及び露出した下地層１
３上に、例えばアルミニウムを真空蒸着法または
スパツタリング法にて厚さ約3000Å堆積し、中間
層１５ａ，１５ｂとする。ここで、半導体基板１
２に向つて飛来して来るアルミニウム粒子は、可
能な限り基板面に対して垂直に飛来するように設
定する。また、中間層１５ａが形成される下地膜
１３と、半導体基板１２は冷却しておくのが望ま
しい。このような操作によつて、堆積するアルミ
ニウム粒子のステツプカバレイジを極端に悪く
し、下地膜１３上の中間層１５ａとレジスト膜１
４上の中間層１５ｂとを分離するものである。 Next, as shown in Figure C, the surface of the patterned resist film 14 and the exposed base layer 1 are removed.
For example, aluminum is deposited to a thickness of about 3000 Å on the intermediate layers 15a and 15b by vacuum evaporation or sputtering. Here, semiconductor substrate 1
The aluminum particles flying toward 2 are set so that they fly as perpendicular to the substrate surface as possible. Further, it is desirable that the base film 13 on which the intermediate layer 15a is formed and the semiconductor substrate 12 be cooled. Such an operation extremely deteriorates the step coverage of the deposited aluminum particles and damages the intermediate layer 15a on the base film 13 and the resist film 1.
4 and the intermediate layer 15b on top.
次にレジスト膜１４を所定の除去液で除去し、
その上に載置した中間層１５ｂをリフトオフによ
り同時に除去する。而して、下地膜１３上に所定
パターンの状態で中間層１５ａを同図Ｄに示す如
く、残存せしめる。 Next, the resist film 14 is removed with a predetermined removal liquid,
The intermediate layer 15b placed thereon is simultaneously removed by lift-off. Thus, the intermediate layer 15a is left in a predetermined pattern on the base film 13, as shown in FIG.
次に、残存した中間層１５ａをマスクにして、
例えばO2プラズマにより下地膜１３に同図Ｅに
示す如く、エツチングによるパターニングを施
す。なお、中間層１５ａの材質としては、このプ
ラズマエツチング処理の際に、中間層１５ａと下
地膜１３および基板との選択比が十分に余裕をも
つてとれるように設定するものが望ましい。例え
ば、基板が酸化膜である場合は、中間層１５ａの
材質としては、アルミニウム、ポリシリコン、シ
リサイド等の金属を使用するのが好ましい。基板
がポリシリコン、シリサイド、アルミニウム等の
金属で形成されいる場合には、中間層１５ａは、
酸化膜、窒化膜等で形成するのが好ましい。 Next, using the remaining intermediate layer 15a as a mask,
For example, the base film 13 is patterned by etching using O 2 plasma as shown in FIG. The material of the intermediate layer 15a is desirably selected so that the selectivity between the intermediate layer 15a and the base film 13 and substrate can be sufficiently selected during this plasma etching process. For example, when the substrate is an oxide film, it is preferable to use a metal such as aluminum, polysilicon, or silicide as the material for the intermediate layer 15a. When the substrate is made of metal such as polysilicon, silicide, or aluminum, the intermediate layer 15a is
It is preferable to use an oxide film, a nitride film, or the like.
このようにこの微細パターンの形成方法によれ
ば、レジスト膜１４の除去処理によつて中間層１
５ａ，１５ｂのパターンニングが行われる。この
ため、中間層１５ａをパターニングするためのマ
スク工程を省略できる。しかも、中間層１５ａ，
１５ｂの材質として不透明の部材を使用すること
ができる。その結果、微細パターンを有する半導
体基板１２を容易に製造できると共に、製造コス
トの低減を達成することができる。さらに、不透
明な部材をマスクに用いても、マスク合せが可能
であり、凹凸部上の下地膜（例えば酸化膜）をエ
ツチングすることができる。 According to this method of forming a fine pattern, the intermediate layer 1 is removed by the removal process of the resist film 14.
Patterning of 5a and 15b is performed. Therefore, a mask process for patterning the intermediate layer 15a can be omitted. Moreover, the intermediate layer 15a,
An opaque member can be used as the material of 15b. As a result, the semiconductor substrate 12 having a fine pattern can be easily manufactured, and manufacturing costs can be reduced. Furthermore, even if an opaque member is used as a mask, mask alignment is possible, and the base film (for example, oxide film) on the uneven portion can be etched.
以上説明した如く、本発明に係る微細パターン
の形成方法によれば、中間層に不透明な膜を使用
して製造を容易にすると共に製造コストを低減さ
せることができる等顕著な効果を有するものであ
る。さらに、不透明な部材をマスクに用いても、
マスク合せが可能で、かつ、凹凸部上の下地膜を
正確にパターニングすることができる。
As explained above, the method for forming a fine pattern according to the present invention has remarkable effects such as using an opaque film in the intermediate layer to facilitate manufacturing and reduce manufacturing costs. be. Furthermore, even if an opaque material is used as a mask,
Mask alignment is possible, and the base film on the uneven portion can be accurately patterned.
第１図Ａ及び同図Ｂは、従来の微細パターンの
形成方法を工程順に示す説明図、第２図Ａ乃至同
図Ｅは、本発明に係る微細パターンの形成方法を
工程順に示す説明図である。
１１……凸部、１２……半導体基板、１３……
下地層、１４……レジスト膜、１５ａ，１５ｂ…
…中間層。
1A and 1B are explanatory diagrams showing a conventional method for forming a fine pattern in order of steps, and FIGS. 2A to 2E are explanatory diagrams showing a method for forming a fine pattern according to the present invention in order of steps. be. 11...Convex portion, 12...Semiconductor substrate, 13...
Base layer, 14...Resist film, 15a, 15b...
...middle class.
Claims (1)
成する際、前記基板の凹凸部上に下地膜をその表
面が平坦になる厚さ分だけ形成する工程と、前記
下記地膜上にレジスト膜を形成する工程と、前記
レジスト膜にパターンニングを施す工程と、パタ
ーニングされたレジスト膜上及び露出した下地膜
上に中間層を形成する工程と、前記中間層の一部
分を前記パターンニングされたレジスト膜ととも
に除去する工程と、残存した中間層をマスクにし
て前記下地膜にパターンニングを施す工程とを具
備することを特徴とする微細パターンの形成方
法。 ２ 前記中間層は、アルミニウム、シリコン、シ
リサイドを含む不透明な部材の中から選ばれるい
ずれか一つであることを特徴とする特許請求の範
囲第１項に記載の微細パターンの形成方法。[Scope of Claims] 1. When forming a fine pattern on a substrate having uneven parts, a step of forming a base film on the uneven parts of the substrate to a thickness that makes the surface flat; a step of forming a resist film on the resist film; a step of patterning the resist film; a step of forming an intermediate layer on the patterned resist film and the exposed base film; A method for forming a fine pattern, comprising the steps of removing the resist film together with the patterned resist film, and patterning the base film using the remaining intermediate layer as a mask. 2. The method for forming a fine pattern according to claim 1, wherein the intermediate layer is any one selected from opaque materials including aluminum, silicon, and silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3848683A JPS59163828A (en) | 1983-03-09 | 1983-03-09 | Formation of fine pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3848683A JPS59163828A (en) | 1983-03-09 | 1983-03-09 | Formation of fine pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59163828A JPS59163828A (en) | 1984-09-14 |
| JPH0522380B2 true JPH0522380B2 (en) | 1993-03-29 |
Family
ID=12526584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3848683A Granted JPS59163828A (en) | 1983-03-09 | 1983-03-09 | Formation of fine pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59163828A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841813A (en) * | 1971-09-27 | 1973-06-19 | ||
| JPS57143826A (en) * | 1981-02-28 | 1982-09-06 | Dainippon Printing Co Ltd | Formation of resist pattern on gapped semiconductor substrate |
| JPS5812344A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Semiconductor device |
-
1983
- 1983-03-09 JP JP3848683A patent/JPS59163828A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4841813A (en) * | 1971-09-27 | 1973-06-19 | ||
| JPS57143826A (en) * | 1981-02-28 | 1982-09-06 | Dainippon Printing Co Ltd | Formation of resist pattern on gapped semiconductor substrate |
| JPS5812344A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59163828A (en) | 1984-09-14 |
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