JPH0675360A - Reticle and production of semiconductor device using the same - Google Patents

Abstract

PURPOSE:To provide a reticle which can suppress deviation of exposure focus between a scribe region and a chip region. CONSTITUTION:A dummy pattern 34 is formed on the center part of the reticle 31 formed with a scribe region pattern 33 at the center area. For example, when a wiring layer is formed by patterning in the chip region of a wafer, a dummy layer having the same thickness as that of the wiring layer is formed on the scribe region of the wafer so as to prevent deviation of exposure focuses between the scribe region and the chip region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reticle used in a lithography process in a semiconductor integrated circuit manufacturing process, and to a method of manufacturing a semiconductor device having good pattern accuracy.

[0002]

2. Description of the Related Art In an integrated circuit forming process by a reduction projection exposure method using a reticle which is a mask for forming a semiconductor integrated circuit, a semiconductor device to be formed is miniaturized and highly integrated. Exposure focusing in the lithography process has become very difficult.
In recent years, with regard to semiconductor memory devices, the capacity has been increased, the chip area has been increased, and one reticle can expose only a few chips at a time. In particular,
In the case of simultaneous exposure of 2 chips or simultaneous exposure of 4 chips with one reticle, the scribe area pattern 2 is the center of the reticle (indicated by X in the drawings) as shown in FIGS. ing. Focusing of such projection exposure is performed at a position on the wafer corresponding to the center of the reticle 1, that is, as shown in FIG. 12A, the resist 3 applied on the scribe area of the wafer.
Focusing is done on the surface of the. Compared with such a scribe area, the integrated circuit pattern formation area is formed, for example, as shown in FIG.
As shown in FIG. 2B, the height is high and a step is formed. In FIG. 12B, 4 is a semiconductor substrate, 5 is an oxide film, and 6 is a SiO ₂ insulating film.
It is similar to the scribe area shown in FIG. And
In the integrated circuit forming region (FIG. 12B), the first polysilicon layer 7 is patterned on the SiO ₂ insulating film 6, and the interlayer insulating film 8, the second polysilicon layer 9, the interlayer insulating film 10, First aluminum wiring layer 11, interlayer insulating film 12, second
Since the aluminum wiring layer 13 is formed, as described above,
When focusing on the resist 3 surface on the scribe area,
There is a problem that the exposure focus shifts in the integrated circuit formation region.

Further, it is difficult to focus because the pattern of the semiconductor integrated circuit is becoming finer and the area of the reticle is becoming larger and the area where the pattern is away from the center of exposure is increasing. The problem is getting more serious.

The present invention was devised in view of such conventional problems, and is equivalent to focusing on the integrated circuit formation region even if the central portion of the exposure surface is the scribe region. A method for manufacturing a reticle and a semiconductor device that enable the focusing of the above.

[0005]

[0006]

The invention according to claim 1 is
In a reticle in which a plurality of chip areas on a semiconductor wafer are simultaneously exposed and a scribe area pattern is formed in the central portion, a dummy pattern is formed in the scribe area pattern located in the central portion, which is a solution means. .

According to a second aspect of the present invention, a method of manufacturing a semiconductor device in which a plurality of chip areas on a semiconductor wafer are simultaneously exposed and a plurality of pattern forming steps are performed using a reticle having a scribe area pattern formed in a central portion thereof. At
The solution is to use a reticle in which a dummy pattern is formed in the scribe region pattern located in the central portion in at least one pattern forming step.

According to a third aspect of the present invention, the reticle in which a dummy pattern is formed in the scribe region pattern located in the central portion is used in a wiring layer pattern forming step.

[0009]

According to the first aspect of the present invention, a dummy pattern is formed in the scribe area pattern located at the center of the reticle, and if the resist is exposed using this reticle, the integrated circuit forming area (chip area) is formed. The material layer to be formed can be formed also in the scribe region on the semiconductor wafer, and the deviation of the exposure focus can be corrected by reducing the step size between the scribe region and the integrated circuit formation region. As a result, it is possible to prevent the collapse of the pattern to be formed in the integrated circuit formation region.

According to a second aspect of the present invention, at least one pattern forming step uses a reticle in which a dummy pattern is formed in a scribe area pattern located in a central portion, so that exposure focusing is performed in the scribe area. It is possible to reduce the focus shift in the chip area in the case of breakage.

According to the third aspect of the present invention, the wiring layer having the same thickness as the chip area can be formed on the scribe area by using the reticle on which the dummy pattern is formed in the wiring layer pattern forming step. it can. When the wiring layer is overlaid on the scribe region, the average height of the surface of the chip region can be approximated, and exposure with less shift of the exposure focus on the chip region is possible. Therefore, a highly accurate resist mask can be formed, and a fine pattern can be surely formed even when high integration is advanced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Details of a reticle according to the present invention and a method of manufacturing a semiconductor device using the reticle will be described below with reference to the embodiments shown in the drawings.

In this embodiment, an SRAM (Static Random) is used.
This is an example in which the present invention is applied to a manufacturing method of a m.Acccess Memory), and FIGS.

First, in this embodiment, a silicon oxide film 22 is formed on the surface of a silicon wafer 21, and then a field oxide film 22A that defines a chip region and a scribe region is formed by a known method. Note that FIG. 1A shows a scribe region a to which the center of the reticle in one section of exposure corresponds, and FIG. 1B shows a chip region b. next,
As shown in FIGS. 1A and 1B, the silicon wafer 21
A first interlayer insulating film 23 made of SiO ₂ is deposited on the entire surface.

Next, after depositing a first polysilicon layer 24 on the first interlayer insulating film 23 by a CVD method, a resist (not shown) is coated. The resist is exposed by a step-and-repeat method in which a reticle 31 as shown in FIG. 9 is used to expose one section (field) and the wafer is moved one step to expose an adjacent field. This reticle 31 is composed of four chip area patterns 32, a scribe area pattern 33, and a dummy pattern 34 formed in the scribe area pattern 33 located at the center. The design pattern of the first polysilicon layer 24 is drawn in the chip region pattern 32.

A resist pattern is formed by exposing the resist using the reticle 31 to cause a phenomenon, and the first polysilicon layer 24 is patterned by dry etching using the resist pattern as a mask. At this time, as shown in FIG. 2A, the first polysilicon dummy layer 24a corresponding to the dummy pattern 34 of the reticle 31 is formed in the scribe region a.

Next, as shown in FIGS. 3A and 3B, a second interlayer insulating film 25 is deposited on the entire surface. And
After depositing a polysilicon film on the second interlayer insulating film 25, resist peening is performed using a reticle having no dummy pattern to form the second polysilicon layer 26 only in the chip region (see FIG. ) And (B)).

Thereafter, as shown in FIGS. 5A and 5B, after depositing a third interlayer insulating film 27 on the entire surface of the wafer,
A contact hole is opened in the third interlayer insulating film 27 in the chip area, and then an aluminum film is formed on the entire surface. For the patterning of the aluminum film, a reticle having a dummy pattern formed in the central portion thereof is used similarly to the reticle shown in FIG. 9 after applying a resist on the aluminum film.
The pattern of the first aluminum wiring layer is drawn on the chip area pattern of this reticle.

Using such a reticle, exposure and phenomenon are performed to pattern the aluminum film, and the first aluminum dummy layer 28a as shown in FIG. 6 (A) and the first aluminum dummy layer 28a as shown in FIG. 6 (B). 1. Aluminum wiring layer 28 is formed.

Next, as shown in FIGS. 7 (A) and 7 (B),
After depositing the fourth interlayer insulating film 29 on the entire surface, FIG.
As shown in (A) and (B), the second aluminum wiring layer 30 is deposited on the entire surface, and the resist 3 is applied thereon. At this time, the exposure focusing is performed on the surface of the resist 3 on the scribe area, as shown in FIG. The heights of the surface of the resist 3 in the scribe region and the chip region (FIG. 8B) are substantially the same because the first polysilicon dummy layer 24a and the first aluminum dummy layer 28a are formed on the scribe region. Since the height is the same, the focus of exposure on the chip area is equivalent to that of focusing on the scribe area, and a fine pattern can be reliably formed even with high integration. In such exposure focusing, the second polysilicon layer 26 is provided because the first polysilicon dummy layer 24a is present.
The defocusing can be prevented even in the patterning of. In the subsequent manufacturing process, the semiconductor device may be completed by using a method similar to the conventional one.

Although the embodiment has been described above, the present invention is not limited to this, and various design changes can be made according to the semiconductor device to be manufactured.

For example, although the present invention is applied to the manufacture of the SRAM in the above embodiment, the present invention is not limited to this.
It can be applied to the manufacture of all semiconductor devices.

Further, although the reticle for four chips is used in the above embodiment, the present invention can of course be applied to a reticle for two chips having a scribe area pattern at the center of the reticle.

Further, in the above embodiment, the wiring layers other than the second polysilicon layer 26 are left as the dummy pattern layers (the first polysilicon dummy layer 24a and the first aluminum dummy layer 28a) in the scribe area, but the chip area is not used. Of course, the dummy layer to be left may be specified in consideration of the unevenness of the structure formed above.

[0025]

As is apparent from the above description, according to the present invention, even when the central portion of the exposure surface is the scribe area, the same focusing as in the device forming area (chip area) is performed. It is possible to obtain a fine pattern without fail even if the degree of integration of the semiconductor device is increased.

As described above, since it is only necessary to form the dummy pattern on the reticle, there is an effect that the lithography accuracy can be improved without increasing the manufacturing process.

[Brief description of drawings]

1A and 1B are cross-sectional views of a main part showing a process of an embodiment of a method for manufacturing a semiconductor device of the present invention.

2A and 2B are cross-sectional views of a main part showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

3 (A) and 3 (B) are cross-sectional views of the essential part showing the steps of the embodiment of the method for manufacturing a semiconductor device of the present invention.

FIGS. 4A and 4B are cross-sectional views of a main part showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

5A and 5B are cross-sectional views of the essential part showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

6 (A) and 6 (B) are cross-sectional views of essential parts showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

7 (A) and 7 (B) are cross-sectional views of essential parts showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

8A and 8B are cross-sectional views of a main part showing the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a plan view showing an embodiment of the reticle of the present invention.

FIG. 10 is a plan view of a conventional reticle.

FIG. 11 is a plan view of a conventional reticle.

FIG. 12A is a sectional view of a conventional scribe region,
(B) is a cross-sectional view of the chip region.

[Explanation of symbols]

 a ... scribe region b ... chip region 3 ... resist 21 ... silicon wafer 22 ... silicon oxide film 23 ... first interlayer insulating film 24 ... first polysilicon layer 24a ... first polysilicon dummy layer 25 ... second interlayer insulating film 26 Second polysilicon layer 27 Third interlayer insulating film 28 First aluminum wiring layer 28a First aluminum dummy layer 29 Fourth interlayer insulating film 30 Second aluminum wiring layer 31 Reticle 32 Chip area pattern 33 … Scribe area pattern 34… Dummy pattern

Claims (3)

[Claims] 1. A reticle in which a plurality of chip regions on a semiconductor wafer are exposed at the same time and a scribe region pattern is formed in a central portion, and a dummy pattern is formed in the scribe region pattern located in the central portion. Characteristic reticle. 2. A method for manufacturing a semiconductor device, comprising: simultaneously exposing a plurality of chip regions on a semiconductor wafer and performing a plurality of pattern forming steps using a reticle having a scribe region pattern formed in a central portion thereof, wherein at least one pattern is provided. A method of manufacturing a semiconductor device, wherein a reticle having a dummy pattern formed in a scribe region pattern located in the central portion is used in the forming step. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the reticle in which a dummy pattern is formed in the scribe region pattern located at the center is used in a wiring layer pattern forming step.