KR20010003781A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR20010003781A
KR20010003781A KR1019990024216A KR19990024216A KR20010003781A KR 20010003781 A KR20010003781 A KR 20010003781A KR 1019990024216 A KR1019990024216 A KR 1019990024216A KR 19990024216 A KR19990024216 A KR 19990024216A KR 20010003781 A KR20010003781 A KR 20010003781A
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South Korea
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film
imd
wafer
oxide film
semiconductor device
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KR1019990024216A
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Korean (ko)
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이상화
소홍선
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김영환
현대전자산업 주식회사
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Priority to KR1019990024216A priority Critical patent/KR20010003781A/en
Publication of KR20010003781A publication Critical patent/KR20010003781A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to sufficiently obtain the process margin by performing a CMP process after partially removing an IMD film. CONSTITUTION: A method for fabricating a semiconductor device comprises the step of forming an IMD(inter metal dielectric) film on an upper surface of a structure after forming a lower metal wire(22) on a semiconductor substrate(21). The semiconductor substrate(21) is formed with a lower structure. Then, a chip die area of a wafer is protected by a photosensitive film. After that, an etching process is carried out so as to etch the IMD film positioned at an edge of the wafer. Then, the photosensitive film is removed. Next, the IMD film is flattened by performing a CMP(chemical and mechanical polishing) process.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 하부 금속 배선 이후의 공정인 IMD(Inter Metal Dielectric)막 형성시 잔류하는 산화막의 증착 균일도를 향상시키기 위한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving the deposition uniformity of an oxide film remaining when forming an intermetal dielectric (IMD) film after a lower metal wiring.

도 1(a) 내지 1(d)는 종래 반도체 소자의 제조 방법을 설명하기 위한 도면으로, 도 1(b) 내지 1(d)의 각 부분은 도 1(a)에 도시한 웨이퍼의 각 부분과 대응된다. 즉, A 부분은 웨이퍼의 중앙 부분, C 부분은 웨이퍼의 에지(edge) 부분, B부분은 C 부분에 인접한 부분을 나타낸다.1 (a) to 1 (d) are diagrams for explaining a conventional method of manufacturing a semiconductor device, and each part of FIGS. 1 (b) to 1 (d) is a part of the wafer shown in FIG. Corresponds to That is, the portion A represents the center portion of the wafer, the portion C represents the edge portion of the wafer, and the portion B represents the portion adjacent to the portion C.

도 1(b)에 도시된 바와 같이, 하부 구조가 형성된 반도체 기판(11) 상부에 금속층을 형성하고, 금속배선 형성용 감광막(13)을 이용한 식각 공정으로 금속층을 패터닝하여 하부 금속 배선(12)을 형성한다.As shown in FIG. 1B, a metal layer is formed on the semiconductor substrate 11 on which the lower structure is formed, and the metal layer is patterned by an etching process using the photosensitive film 13 for forming metal wirings. To form.

도 1(c)에 도시된 바와 같이, 하부 금속 배선(12)의 갭 필링(gap filling)을 위하여 전체 구조 상부에 고밀도 플라즈마(HDP) 산화막(14) 및 CVD 산화막(15)을 순차적으로 형성하여 IMD막(16)을 형성한다.As shown in FIG. 1C, a high density plasma (HDP) oxide film 14 and a CVD oxide film 15 are sequentially formed on the entire structure for gap filling of the lower metal wiring 12. An IMD film 16 is formed.

도 1(d)에 도시된 바와 같이, CMP 공정을 실시하여 IMD막(16)을 평탄화한다. 이후, 콘택 홀 형성 및 상부 금속 배선 형성 공정 등을 진행한다.As shown in Fig. 1D, a CMP process is performed to planarize the IMD film 16. Figs. Thereafter, contact hole formation and upper metal wiring formation processes are performed.

CMP 공정의 연마량은 하부 패턴 즉, 하부 금속 배선(12)의 밀도에 가장 많이 의존하며, 패턴이 형성된 부분(A, B)에 비하여 평판으로 되어 있는 부분(C)의 IMD막(16) 연마량은 2 내지 3배정도 높게 된다. 즉, 패턴이 형성되지 않은 웨이퍼의 에지 부분(C)의 연마량이 패턴이 형성된 웨이퍼 중앙 부분(A)에 비해 현저히 낮아지게 된다. 웨이퍼의 에지에 인접한 부분(B)은 웨이퍼 에지 부분(C)의 느린 연마 속도에 의해 연마가 방해되며, 따라서 웨이퍼 중앙 부분(A)과 에지 부분(C)의 잔류 산화막의 두께는 3000Å 정도로 차이가 나게 된다. 이러한 현상은 후속 비아 홀 형성시 웨이퍼 에지 인접 지역(B)에서 정상적인 비아 홀이 형성되는 것을 방해하여, 이로 인하여 웨이퍼 인접 지역(B)의 다이(die)에서는 소자가 제대로 동작하지 않아 패일이 발생하게 된다.The polishing amount of the CMP process is most dependent on the lower pattern, that is, the density of the lower metal wiring 12, and the polishing of the IMD film 16 of the portion C, which is a flat plate, compared to the portions A and B on which the pattern is formed. The amount is about 2 to 3 times higher. That is, the amount of polishing of the edge portion C of the wafer on which the pattern is not formed becomes significantly lower than the center portion A of the wafer on which the pattern is formed. The portion B adjacent to the edge of the wafer is hindered by the slow polishing speed of the wafer edge portion C, so that the thickness of the residual oxide film between the wafer center portion A and the edge portion C is approximately 3000 mm 3. I will. This phenomenon prevents the formation of normal via holes in the wafer edge adjacent areas B during subsequent via hole formation, which causes the device to not work properly in the dies of the wafer adjacent areas B, causing a failure. do.

이러한 문제점은 웨이퍼 에지 부분(C)에도 하부 금속 배선 형성용 마스크를 이용하여 패터닝하는 방법으로 해결할 수 있지만, 웨이퍼 에지 부분(C)의 하부 구조가 이전의 여러 가지 공정들에 의해 심한 단차를 갖기 때문에 하부 금속 배선 형성용 마스크 공정이 목적하는 데로 진행되지 않게 된다. 이에 의해 웨이퍼 에지 부분(C)의 하부 금속 배선(12) 식각시 떨어져 나가는 금속 조각들이 결함(defect) 또는 파티클로 작용하여 전체 다이의 패일을 유발하기 되는 문제점이 있다.This problem can be solved by patterning the wafer edge portion C using a mask for forming a lower metal wiring, but since the underlying structure of the wafer edge portion C has a severe step by a variety of previous processes. The mask process for forming the lower metal wirings does not proceed as desired. As a result, the metal pieces that fall off during the etching of the lower metal wiring 12 of the wafer edge portion C act as defects or particles, causing the entire die to fail.

이와 같은 IMD막의 증착 불균일성은 8인치(inch) 웨이퍼를 기준으로 전체 생산 네드 다이가 25% 정도 감소하는 문제를 야기한다.This deposition nonuniformity of the IMD film causes a problem of a 25% reduction in the overall production ned die on an 8 inch wafer.

따라서, 본 발명은 웨이퍼 에지 부분의 하부 금속배선 상에 형성된 IMD막을 CMP 공정 전 일정량 제거하여, 전체 웨이퍼의 연마량을 동일한 조건으로 맞추므로써 잔류 IMD막의 증착 균일성을 개선할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to manufacture a semiconductor device capable of improving the uniformity of deposition of the residual IMD film by removing a certain amount of the IMD film formed on the lower metal interconnection of the wafer edge portion before the CMP process, matching the polishing amount of the entire wafer to the same conditions The purpose is to provide a method.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 하부구조가 형성된 반도체 기판 상에 하부 금속 배선을 형성한 후, 전체 구조 상부에 IMD막을 형성하는 단계와, 웨이퍼의 칩 다이 지역을 감광막으로 보호하고 식각 공정을 진행하여 웨이퍼 에지 부분의 IMD막을 일정 두께 식각하는 단계와, 상기 감광막을 제거하고 CMP 공정을 실시하여 상기 IMD막을 평탄화하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method according to the present invention for achieving the above object is to form a lower metal wiring on the semiconductor substrate on which the lower structure is formed, to form an IMD film over the entire structure, and to form a chip die region of the wafer And etching the IMD film at the wafer edge portion by protecting the photosensitive film and performing an etching process, and removing the photosensitive film and performing a CMP process to planarize the IMD film.

도 1(a) 내지 1(d)는 종래 반도체 소자의 제조 방법을 설명하기 위해 도시한 도면.1 (a) to 1 (d) are diagrams for explaining a conventional method for manufacturing a semiconductor device.

도 2(a) 내지 2(d)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 도면.2 (a) to 2 (d) are diagrams for explaining a method of manufacturing a semiconductor device according to the present invention.

＜도면의 주요 부분에 대한 부호 설명＞<Explanation of symbols on the main parts of the drawing>

21 : 반도체 기판 22 : 하부 금속 배선21 semiconductor substrate 22 lower metal wiring

23 : HDP 산화막 24 : CVP 산화막23: HDP oxide film 24: CVP oxide film

25 : 감광막25 photosensitive film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2(a) 내지 2(d)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 도면으로, 도 2(b) 내지 2(d)의 각 부분은 도 2(a)에 도시한 웨이퍼의 각 부분과 대응된다. 즉, A 부분은 웨이퍼의 중앙 부분, C 부분은 웨이퍼의 에지(edge) 부분, B부분은 C 부분에 인접한 부분을 나타낸다.2 (a) to 2 (d) are diagrams for explaining a method of manufacturing a semiconductor device according to the present invention. Each part of FIGS. 2 (b) to 2 (d) is shown in FIG. 2 (a). Corresponds to each part of a wafer. That is, the portion A represents the center portion of the wafer, the portion C represents the edge portion of the wafer, and the portion B represents the portion adjacent to the portion C.

도 2(b)에 도시된 바와 같이, 하부 구조가 형성된 반도체 기판(21) 상부에 금속층을 형성하고, 금속 배선 형성용 감광막(도시되지 않음)을 이용한 식각 공정으로 하부 금속 배선(22)을 형성한다. 이후, 전체 구조 상부에 고밀도 플라즈마(High Density Plasma; HDP) 산화막(23) 및 CVD 산화막(24)을 순차적으로 형성하여 IMD막(20)을 형성한 다음, 웨이퍼의 칩 다이 지역(A, B)을 감광막(25)으로 보호하고 식각 공정을 실시한다.As shown in FIG. 2B, a metal layer is formed on the semiconductor substrate 21 on which the lower structure is formed, and the lower metal wiring 22 is formed by an etching process using a photosensitive film (not shown) for forming a metal wiring. do. Thereafter, the high density plasma (HDP) oxide film 23 and the CVD oxide film 24 are sequentially formed on the entire structure to form the IMD film 20, and then the chip die regions A and B of the wafer. Is protected by the photosensitive film 25 and the etching process is performed.

도 2(c)에 도시된 바와 같이, 웨이퍼의 칩 다이 지역(A, B)에만 감광막(25)을 형성하였으므로, 웨이퍼 에지 부분(C)의 CVD 산화막(24)만이 일정량 제거된다. 이후, 감광막(25)을 제거한다. 이에 의해, 웨이퍼 에지 부분(C)의 IMD막은 웨이퍼의 칩 다이 지역(A, B)보다 낮은 높이를 갖게 된다.As shown in Fig. 2C, since the photosensitive film 25 is formed only in the chip die regions A and B of the wafer, only a certain amount of the CVD oxide film 24 of the wafer edge portion C is removed. Thereafter, the photosensitive film 25 is removed. As a result, the IMD film of the wafer edge portion C has a height lower than the chip die regions A and B of the wafer.

도 2(d)에 도시된 바와 같이, CMP 공정을 실시한다. 이후, 콘택 홀을 형성하고 상부 금속배선 형성 공정을 계속해서 진행한다. 도시된 것과 같이, 웨이퍼 에지 부분(C)은 웨이퍼의 칩 다이 지역(A, B)에 비해 낮게 형성되어 있기 때문에, CMP 공정시 연마량이 낮더라도 주변의 IMD막과 동일한 높이를 얻을 수 있게 된다. 결국 웨이퍼 전 지역에 걸쳐서 잔류하는 IMD막(20)의 두께가 균일하게 된다.As shown in FIG. 2 (d), a CMP process is performed. Thereafter, contact holes are formed and the upper metal wiring forming process is continued. As shown, since the wafer edge portion C is formed lower than the chip die regions A and B of the wafer, even if the polishing amount is low during the CMP process, the same height as the surrounding IMD film can be obtained. As a result, the thickness of the IMD film 20 remaining over the entire wafer area becomes uniform.

여기에서, CVD 산화막(24)은 Si-rich 산화막, PE-USG, O3-TEOS 중 어느 하나를 이용하여 형성한다. 또한, HDP 산화막(23) 형성 전 실리콘 옥시 나이트라이드와 같은 질화막을 형성할 수도 있다.Here, the CVD oxide film 24 is formed using any one of a Si-rich oxide film, PE-USG, and O 3 -TEOS. In addition, a nitride film such as silicon oxynitride may be formed before the HDP oxide film 23 is formed.

또한, 이와 같은 방법은 폴리실리콘간 산화막(IPO) 형성시에도 적용할 수 있다.This method can also be applied to the formation of an interpolysilicon oxide film (IPO).

상술한 바와 같이, 본 발명에 따르면 IMD막을 형성한 후, 웨이퍼 에지 분의 IMD막을 일정량 제거한 후 CMP 공정을 실시하므로써, 웨이퍼 전체의 잔류 산화막의 증착 균일성을 확보할 수 있어 8인치 웨이퍼를 기준으로 네트 다이를 25% 이상 확보할 수 있고, 후속 공정 진행시의 마진을 충분하게 확보할 수 있는 효과가 있다.As described above, according to the present invention, after forming the IMD film and then removing the predetermined amount of the IMD film at the wafer edge, the CMP process can be performed to ensure the uniformity of deposition of the remaining oxide film over the entire wafer. The net die can be secured more than 25%, and sufficient margin can be secured during the subsequent process.

Claims (5)

하부구조가 형성된 반도체 기판 상에 하부 금속 배선을 형성한 후, 전체 구조 상부에 IMD막을 형성하는 단계와,Forming a lower metal wiring on the semiconductor substrate on which the lower structure is formed, and then forming an IMD film over the entire structure; 웨이퍼의 칩 다이 지역을 감광막으로 보호하고 식각 공정을 진행하여 웨이퍼 에지 부분의 IMD막을 일정 두께 식각하는 단계와,Protecting the chip die area of the wafer with a photosensitive film and performing an etching process to etch a predetermined thickness of the IMD film at the wafer edge; 상기 감광막을 제거하고 CMP 공정을 실시하여 상기 IMD막을 평탄화하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.Removing the photosensitive film and performing a CMP process to planarize the IMD film. 제 1 항에 있어서,The method of claim 1, 상기 IMD 막은 고밀도 플라즈마 산화막인 것을 특징으로 하는 반도체 소자의 제조 방법.And the IMD film is a high density plasma oxide film. 제 1 항에 있어서,The method of claim 1, 상기 IMD 막은 고밀도 플라즈마 산화막 및 CVD 산화막의 적층 구조인 것을 특징으로 하는 반도체 소자의 제조 방법.And said IMD film is a laminated structure of a high density plasma oxide film and a CVD oxide film. 제 3 항에 있어서,The method of claim 3, wherein 상기 CVD 산화막은 Si-rich 산화막, PE-USG, O3-TEOS 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The CVD oxide film is a method of manufacturing a semiconductor device, characterized in that formed using any one of Si-rich oxide film, PE-USG, O 3 -TEOS. 제 1 항에 있어서,The method of claim 1, 상기 IMD막은 고밀도 플라즈마 산화막과 CVD 산화막을 2층 이상 적층하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the IMD film is formed by stacking two or more layers of high density plasma oxide film and CVD oxide film.
KR1019990024216A 1999-06-25 1999-06-25 Method of manufacturing a semiconductor device KR20010003781A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541290B2 (en) 2007-03-08 2009-06-02 Samsung Electronics Co., Ltd. Methods of forming mask patterns on semiconductor wafers that compensate for nonuniform center-to-edge etch rates during photolithographic processing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541290B2 (en) 2007-03-08 2009-06-02 Samsung Electronics Co., Ltd. Methods of forming mask patterns on semiconductor wafers that compensate for nonuniform center-to-edge etch rates during photolithographic processing

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