JPS6211491B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Processing the main surface of a semiconductor wafer into a desired pattern, forming a semiconductor region having a desired pattern within the semiconductor wafer, or forming a desired layer having a desired pattern on the semiconductor wafer. When forming a semiconductor wafer, a mask having a desired pattern is formed on a semiconductor wafer.

This mask is usually made by forming a material layer on a semiconductor wafer, forming a photoresist layer on the material layer, and using an exposure mask having a desired pattern on the photoresist layer. The exposed photoresist layer is exposed to light, and then the exposed photoresist layer is developed to form a mask having a desired pattern of the photoresist layer, and then the above-mentioned material layer is formed using the mask as a mask. The photoresist layer is obtained by performing an etching process on the photoresist layer, or the above-mentioned mask material layer is used as a photoresist layer, and the photoresist layer is exposed to light using an exposure mask having a desired pattern. It can be obtained by developing a photoresist layer.

By the way, as described above, when forming a mask having a desired pattern on a semiconductor wafer using an exposure mask, relative alignment between the semiconductor wafer and the exposure mask is required. Alignment marks are required on top.

The present invention relates to a method of manufacturing alignment marks on semiconductor wafers for such needs.

As alignment marks on semiconductor wafers,
Conventionally, alignment marks have been made using the edge of an oxide film attached to a semiconductor wafer, grooves made in the semiconductor wafer have been used as alignment marks, and through holes drilled in the semiconductor wafer have been used as alignment marks. Some proposals have been made for use as alignment marks.

However, if the alignment mark is the edge of an oxide film attached to the semiconductor wafer or a groove made in the semiconductor wafer, If a semiconductor film or metal film is formed on the semiconductor wafer, or if the semiconductor wafer is subjected to thermal oxidation treatment, etching treatment, etc. before forming a mask with the desired pattern using an exposure mask, This method has disadvantages in that the alignment mark is damaged, or the contrast of the alignment mark is reduced, resulting in an alignment mark with a degraded S/N ratio.

In addition, if the alignment mark is a through hole drilled in a semiconductor wafer, before forming a mask with a desired pattern on the semiconductor wafer using an exposure mask. When the above-mentioned processing is performed, the through holes used as alignment marks may be filled with other materials, or the ends of the through holes may be damaged, resulting in alignment marks with degraded S/N. It had drawbacks.

Accordingly, the present invention proposes a novel method for manufacturing alignment marks on semiconductor wafers, which does not have the above-mentioned drawbacks, as will become clear from the detailed description below.

First, in order to facilitate understanding of the present invention, we will first explain the alignment marks on a semiconductor wafer obtained by the method for producing alignment marks on a semiconductor wafer according to the present invention with reference to FIGS. 1 and 2. To give an example, at least two first and second regions 4 and 5 in which a large number of microscopic depressions 3 having an arcuate cross section are arranged at predetermined positions on the main surface 2 of the semiconductor wafer 1, They are arranged in such a way that a third region 7 consisting of a linearly extending flat surface 6 is left in between. In this case, a large number of minute depressions 3 extend adjacent to each other in a straight line.

The above is an example of the structure of an alignment mark on a semiconductor wafer obtained by the method of manufacturing an alignment mark on a semiconductor wafer according to the present invention.

Next, an example of a method for manufacturing an alignment mark on a semiconductor wafer according to the present invention for manufacturing an alignment mark having such a configuration will be described with reference to FIG. On the main surface 2 of the wafer 1 (FIG. 3A), a mask material layer 21 such as a thermal oxide film or a nitride film is formed to a thickness of, for example, 5000 Å by a method known per se. Figure B).

Next, a large number of micro-windows 2 are formed on the mask material layer 21.
For etching, the photoresist material has a pattern in which at least two first and second mask layer sections 23 and 24 are arranged in such a manner as to leave a linearly extending section 25. The mask layer 26 is formed by a photolithographic method known per se (FIG. 3C).

Next, by etching the mask material layer 21 using the etching mask layer 26 as a mask, a large number of micro-windows 27 formed by the mask material layer 21 and corresponding to the etching mask layer 26 are formed. A portion 30 in which the arranged first and second mask layer portions 28 and 29 extend linearly.
An etching mask layer 31 having a pattern arranged in such a manner as to leave the etching mask layer 26 is formed, and then the mask layer 26 is removed (FIG. 3D).

Next, the semiconductor wafer 1 is subjected to an isotropic etching process by plasma etching using the etching mask layer 31 as a mask.
The alignment marks described above in FIG. 2 and FIG. 2 are formed (FIG. 3E).

Next, the mask layer 31 is removed from the semiconductor wafer 1, thereby obtaining the desired alignment marks shown in FIGS. 1 and 2 (FIG. 3F).

As described above, the manufacturing method of the alignment mark according to the present invention has been clarified. According to the alignment mark shown in FIGS. 1 and 2 obtained by the present invention, the first and second regions are Since the minute depressions 3 in 4 and 5 have an arcuate cross section (an arcuate cross section of a circle with a diameter of about 1 to 5 μm), there is no specular reflection at the minute depressions 3, but the flat surface in the third region 7 It has a specular reflection at 6 and therefore functions as a high contrast alignment mark.
Therefore, according to the method for manufacturing an alignment mark according to the present invention, the alignment mark can be manufactured as having a large contrast.

Further, according to the method for manufacturing an alignment mark according to the present invention, since the minute depressions in the first and second regions are formed by isotropic etching treatment using plasma etching treatment, the minute depressions are formed on the surface of the semiconductor wafer. Regardless of the orientation, that is, even if the surface orientation of the semiconductor wafer is 111 planes other than 100 planes, it is possible to easily form a clear outline with high precision, and therefore, alignment marks can be It can be easily formed with high precision regardless of the surface orientation of the semiconductor wafer.

Note that the above description merely shows one example of the present invention, and as shown in FIGS. 4 and 5,
Four regions 41, 42, 43 and 44 similar to the first regions 4 and 5 in the case of FIG. 1 and FIG. 2 are formed, and the regions in the case of FIG. 1 and FIG. 7 may be formed as a cross-shaped region 45 orthogonal to each other, and various other modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

1 and 2 are a schematic plan view and a cross-sectional view thereof showing an example of an alignment mark formed by the alignment mark manufacturing method according to the present invention. FIG. 3 is a schematic cross-sectional view of successive steps showing an example of a method for manufacturing an alignment mark according to the present invention. 4 and 5 are a schematic plan view and a sectional view thereof showing other examples of alignment marks formed by the alignment mark manufacturing method according to the present invention. 1...Semiconductor wafer, 2...Main surface, 3...Minute depression, 4, 5, 7...Region, 6...Flat surface,
21...Mask material layer, 23, 24, 28, 29...
...mask material layer portion, 25, 30... linearly extending portion, 26, 31... etching mask layer, 27... micro window.

Claims (1)

[Claims] 1. At a predetermined position on the main surface of the semiconductor wafer,
Forming an etching mask layer having a pattern in which at least two first and second mask layer portions each having a large number of micro-windows are arranged in such a manner that a linearly extending portion remains. A large number of minute depressions having an arcuate cross section are arranged at predetermined positions on the main surface of the semiconductor wafer by isotropic etching process by plasma etching process on the semiconductor wafer using the etching mask layer. forming an alignment mark in which the first and second regions are arranged in such a manner that a third region formed by a flat surface extending linearly is left between them; 1. A method for producing an alignment mark on a semiconductor wafer, comprising: