JPS6169146A - Flattening for coated film - Google Patents

Abstract

PURPOSE:To enable to obtain the formation of a flat film, which is not affected by the base configuration, in the shape of a practical thin film by a method wherein an applied film is provided on the substrate more than two times thicker than the step difference and the applied film is dissolved in the prescribed film thickness or a dry etching is performed on the applied film in the prescribed film thickness. CONSTITUTION:Field oxide films 2, a gate oxide film 3 and a polycrystalline silicon film 4 are formed on a silicon substrate 1, and furthermore, an oxide film 5 and an Al-Si alloy film 6 are deposited. A resist film is applied on the alloy film film 6 and after the whole is dipped in a TM developer, the resist film is decreased and the flat applied film, which is not affected by the base step difference, is obtained. A processing is performed on intermediate layers, SOG films 9, using resist patterns 10 as masks, an etching is selectively performed on the flat film 8 and a selective etching is performed on the alloy film 6 with mixed gas of CCl4 and O2 using the SOG films 9 and the flat film 8 as masks. As the film thickness of the flattened layer is formed in a thin film type, a processing can be accurately performed and the resist patterns on the uppermost layers can be highly resolved without being affected by the stepped configuration of the base substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for providing a flattened film on the surface of a semiconductor substrate or the like.

[Technical background of the invention and its problems]

Conventionally, in the field of microfabrication technology, typified by semiconductor device manufacturing technology, many films, typified by resist films, are used. Generally, the coating shows coverage that reflects the steps and unevenness of the surface of the underlying substrate, and is not flat. For this reason, for example, in a multilayer resist process, a lower layer that is also provided to flatten the underlying layer is often made extremely thick to reflect the unevenness of the underlying layer. As a result, machining accuracy decreases. In addition, in a technique called etch pack method, the flat shape of the surface of the resist film is etched and the underlying layer is etched at the same time to make the underlying layer flat. Because of the reflection, it was not possible to make the film thinner and the etching process time increased. Further, the resist pattern itself is coated sufficiently thick due to restrictions regarding the shape of steps, etc., resulting in dissatisfaction with resolution. In the two-layer method called special KCEL, the thickness of the fi CEL layer varies due to the unevenness of the underlying regular resist film, which greatly impairs the uniformity of the line width.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a highly practical method for achieving a thin film that is flat and unaffected by the underlying shape.

[Summary of the invention]

In the present invention, a resist film is formed on a substrate having one level difference or unevenness to a sufficiently thick thickness of at least twice the level difference, and then melted or dry etched to a predetermined film thickness so that the desired film thickness is not affected by the underlying level difference. The main idea is to form a supported film. Namely.

The present invention is a method for forming a flat film with a practical film thickness by utilizing the property that a sufficiently thick film forms a flat surface that is not easily affected by the level difference between the base layers.

〔Effect of the invention〕

By applying the present invention, sufficient flatness can be achieved with a thin film, making patterning extremely easy and resulting in excellent resolution and processing accuracy. Multilayer resist process, +″FW (lF
MK[I:N*”y f ” y l 'llz O-mouth has the effect of becoming 9-fold.

[Embodiments of the invention]

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 1 to 6 are cross-sectional views showing the manufacturing process of a MOS (MOS) gingister according to an embodiment of the present invention, specifically, the type of wiring pattern forming process. Using well-known technology,
As shown in FIG. 1, a field oxide film 2, a genit oxide film 3, and a polycrystalline silicon gate 4 are formed on a silicon substrate 1 for element isolation, and an oxide film 5 is further deposited thereon.

and oxide film 5. A contact hole is provided and this oxidized g
1'-1-8i alloy PA6 (workpiece) for wiring on 5
was deposited. Note that 7 in the figure indicates a source/drain region.

Next, as shown in FIG.
After soft-baking the l-il, it was immersed for 6 minutes in Tama Chemical fiTM developer bath maintained at 50C.
Washed with water and dried. As a result, as shown in Fig. 3, the resist film was reduced to 1.5βm, and an extremely flat coating film unaffected by the underlying step was formed, and an intermediate layer of S.
-Gf: Coated. 0NPR-8 as shown in Figure 4
00 resist is applied to a thickness of 1.5 μm by a spin code method, exposed, developed and post-baked. Then, as shown in FIG. 5, using the resist pattern 10 as a mask, the intermediate i'J-8.0.G9 was processed by a reactive ion etching method using a mixed gas of CF and H2.

Furthermore, as shown in Figure 86, resist patterns 10 and 8-0
The planar film 8 was selectively etched using -09 as a mask.

At this time, the resist pattern 10 on the top layer is removed.

Next is the mixed gas of CC/4 and 02? Using the reactive ion etching method used, the AJ-8i alloy film 6 was selectively etched using the s.0.G9 and flat film 8 as masks. As a result, as shown in FIG. 7, the machined shape according to this example was machined with high precision because the thickness of the flattened layer to be machined was reduced. In addition, the resist pattern provided on the top layer was dusted with high resolution without being affected by the stepped shape of the underlying substrate because the underlying layer was significantly flattened and IA7J.

[Other embodiments of the invention]

FIGS. 8 to 11 are O process cross-sectional views for explaining other embodiments of the present invention. Here, an example will be described in which an MOa type semiconductor element is manufactured using multilayer wiring technology.

As shown in FIG. 8 (8i0212 was formed on the 8i substrate 11 and an AJ-S i alloy wiring pattern 13 was formed, 8i0214 was then coated by the LPCVD method. Thereafter, as shown in FIG. 9, the 8i0214 was coated by the spin code method. A resist was applied to a thickness of 3.0 μm.

Next, soft bake at 90℃ for 2 minutes, then 50'
The Tama Kagaku Group TM Dipero maintained at C was immersed in a bar for 8 minutes, washed with water, and dried to obtain a coating film with a thickness of about 1.0 μm that was extremely flat and unaffected by the level difference in the base as shown in Figure 10. Dry etching was performed using a mixed gas of CFI4 and H2. At this time, resists 15 and 5i02 had almost the same etching speed. As a result, a flattened 8i02 film 14 as shown in Fig. 11 was obtained.The 5i02 film obtained as a result of 0 or more has a flattened step shape on the base, and the line width of wiring provided in multiple layers. The uniformity was improved and a significant improvement in reliability was achieved.

The present invention has been described in detail using Examples above.

The application of the present invention is not limited to these embodiments.1 For example, it is possible to thin a sufficiently thick film and then layer the thin films to make it more flat. The effect of the present invention was also obtained even when the film was thinned until the substrate was exposed and then coated again.

In this embodiment, the film may be thinned by using an organic alkali aqueous solution or by dry etching.

[Brief explanation of drawings]

Figures 1 to 7 show an example in which the present invention is applied to a multilayer resist process, and Figures 8 to 7 show an example in which the present invention is applied to an etch-back process. It is a process sectional view shown. 1...Si substrate, 2...Field oxide film 3...
Gate oxide film, 4... polycrystalline silicon gate 5...
Oxide film, 6...AJI-8i alloy film (workpiece) 7
... Source/drain region, 8... Flattened resist, 9... Intermediate layer/S/0/G, 10... Resist pattern 11...8i substrate, 12...5i0213
...AJ-81,14...5i02 (insulating film) 15
...Hiratanaka resist agent Patent attorney Kensuke Norichika (and 1 other person) Figure 2

Claims (2)

[Claims] (1) The method is characterized by comprising the steps of providing a coating film on a substrate having steps or unevenness to a thickness at least twice as thick as the steps, and then dissolving or dry etching the coating film to a predetermined thickness. A method for leveling a flattened film. (2) In the method for flattening a film as set forth in claim 1 above, the flattened film is formed by repeating the step of forming the flattened film at least twice or more. Flattening method.