JPS5890728A - Mark for alignment on semiconductor wafer and manufacture thereof - Google Patents

Abstract

PURPOSE:To form an alignment mark havng a large contrast, by interposing a region defined by a flat surface between regions where a multiplicity of minute cavities each having a circular cross section are arranged. CONSTITUTION:At a predetermined position on a main surface 2 of a semiconductor wafer 1, at least two regions 4 and 5 are formed each of which has a multiplicity of minute cavities 3 arranged therein. In addtion, a region 7 defined by a linearly elongated flat surface 6 is disposed between the regions 4, 5. In this case, the minute cavities 3 are linearly elongated adjacently to each other. Such an alignment mark has no regular reflection at the cavities 3 in the regions 4, 5 but has a regular reflection at the flat surface 6 in the region 7. Thus, it is possible to form an alignment mark having a large contrast.

Description

[Detailed description of the invention] Processing the main surface of a semiconductor wafer into a desired pattern,
When forming a semiconductor region having a predetermined pattern in the semiconductor cube 77 or forming a required layer having a required pattern on a semiconductor wafer, a mask having a required pattern is formed on the semiconductor wafer. . This mask is usually made by forming a material layer that serves as the mask on a semiconductor wafer, forming seven photoresist layers on the material layer, and using an exposure mask having a desired pattern on the photoresist layer. The exposed photoresist is then subjected to a development process to form a mask having a desired pattern of the photoresist layer, and then the mask is used as a mask as described above. obtained by etching a layer of material that
The material layer serving as the mask described above is a photoresist layer,
It can be obtained by exposing the photoresist layer to light using an exposure mask having a desired pattern, and then applying fA to the exposed photoresist layer.

By the way, when forming a mask having a desired pattern on a semiconductor wafer using such an exposure mask, relative alignment between the semiconductor quefer and the exposure mask is required.
For this reason, alignment marks are required on the semiconductor wafer.

The present invention relates to alignment marks on semiconductor wafers for such needs and a method for making the same.

Traditionally, this type of alignment mark on semiconductor wafers is
One uses the edge of an oxide film attached to a semiconductor wafer as an alignment mark, one uses a groove made in a semiconductor wafer as an alignment mark, and another uses a through hole drilled in a semiconductor wafer as an alignment mark. 0
However, if the alignment mark is an edge of an oxide film attached to a semiconductor wafer or a groove made in the semiconductor wafer, If a semiconductor film or metal film, etc. is formed on the semiconductor wafer, or if the semiconductor wafer is subjected to thermal oxidation treatment, etching treatment, etc. before forming a mask with the required pattern using an exposure mask, the position If the alignment mark is damaged or
This has the disadvantage that the contrast of the alignment mark decreases, resulting in an alignment mark with a deterioration of 8/N.

In addition, if the alignment mark is a through hole drilled in a semiconductor wafer, the above-mentioned process is performed after forming a mask having a desired pattern on the semiconductor wafer using an exposure mask. If you do this,
The through hole used as the alignment mark was buried with other materials, or the end of the through hole was damaged, resulting in a deteriorated alignment mark of 87N.

Therefore, the present invention aims to propose an alignment mark on a conductive wafer and a method for manufacturing the same, which are free from the above-mentioned drawbacks, and will become clear from the following description.

1 and 23 show an example of alignment marks on a semiconductor wafer according to the present invention. At least two first and second regions 4 and 5 each having an array of small depressions 6 extend in instant contact with a linearly extending flat surface 6 between them. .

The above is an example of the configuration of a positioning mark on a semiconductor wafer according to the present invention.
This can be manufactured as shown in FIG. 5 and described below.

That is, a mask material layer 2 such as a thermal oxide film, a nitride film, etc.
1 by methods known per se, e.g.
(FIG. 5B), and then at least two micro-windows 22 are arranged on the mask material layer 21.
The etching mask layer 26 is made of a photoresist material and has a pattern in which two first and #I2 mask layer portions 25 and 24 are arranged with a rectangularly extending portion 25 remaining. It is formed by the 7-otrinography method (Fig. 5, 0).

Next, by etching the mask material layer 21 using this etching mask layer 26 as a mask, the irises formed by the mask material layer 21 and having a large number of micro-windows 27 arranged corresponding to the etching mask layer 26 are etched. Part 5 where the first and second mass layer parts 28 and 29 can extend linearly
An etching mask layer 51 having a pattern arranged in such a manner that zeros are left is formed, and then the mask layer 26 is removed (FIG. 3D).

Next, plasma etching is performed as a uniform etching process on the semiconductor wafer 1 using the etching mask layer 51 as a mask. Formation JI3 Figure E),
After that, the mask layer 51 is removed from the semiconductor wafer 1,
In this way, the desired alignment marks shown in FIGS. 1 and 2 are obtained (FIG. 3F).

The embodiments of the alignment mark and its manufacturing method according to the present invention have been clarified above, but according to the alignment mark shown in Fig. a11 and Fig. 1ilZ according to the present invention, the first and second regions 4 and The copying small sickle 3 in 5 has an arcuate cross section (
Since it has an arcuate cross section of a circle with a diameter of about 1 to 5 μm,
There is no specular reflection at the micro-sandwich 6, but with a specular reflection at the flat surface 6 in the third region 7, thus functioning, and the alignment mark is as described at the beginning. For conventional alignment! It has the characteristic that it does not have the disadvantages associated with -.

Furthermore, the method of manufacturing the alignment mark shown in FIG. 5 according to the present invention has the great feature that the above-mentioned characteristic alignment mark can be easily obtained through an extremely simple process. .

In addition to the improvement, an example of the present invention is shown, as shown in FIGS. 4 and 5,
Four regions similar to regions 4 and 5 were formed as 1 base 41, 42, 43 and 44, and accordingly, FIGS. 1 and 2
In the case of the figure, the region 7 may be formed as a cross-shaped headrest 45, and various other modifications may be made.

4, the 11th page of the beautiful cod, Ming Dynasty 1 and! Figure 2 shows an example of the present invention and a cross-sectional view thereof, and Figure 6 shows an example of its manufacturing method.
The r-direction view, FIGS. 4 and 5 are schematic plan views showing other ψ angles of the present invention, and their cross-sections [fl+f].

Nippon Telegraph and Telephone Corporation Figure 1 Figure 8 Month Figure 4 Figure δ

Claims (1)

[Claims] 1. At least two first and second regions each having a plurality of microscopic depressions each having an arcuate cross section are arranged at predetermined positions on the main surface of the semiconductor wafer. An alignment mark on a semiconductor wafer, characterized by ◆, which is arranged in such a manner as to leave a third region formed of a flat surface extending linearly at equal intervals. 2. At a predetermined position on the main surface of the semiconductor wafer, at least two first and second mask layer parts formed by an array of five copying small windows leave a part that can be linearly extended. a process of forming an etching mask layer having a pattern arranged in the form of an etching mask layer, and performing an equal-fortune etching process on the semiconductor wafer using the etching mask layer;
At a predetermined position on the main surface of the semiconductor wafer, first and second regions each having a plurality of microscopic depressions each having an arcuate cross section are arranged on a flat surface with a straight line Kg extending therebetween. 1. A method for producing an alignment mark on a semiconductor wafer, the method comprising the step of forming alignment marks arranged in such a manner as to leave a fifth region. (5) In the method for manufacturing an alignment mark on a semiconductor wafer as set forth in claim 2fj, the alignment mark on a semiconductor wafer is characterized in that the above-mentioned etching process is a plasma etching process. manufacturing method.