JPS6030118B2 - Pattern formation method for hybrid thin film integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for performing alignment during pattern formation of the second and subsequent layers in a pattern formation method for a hybrid integrated circuit made of multilayer thin films.

In general, in a hybrid thin film integrated circuit, in order to form a film resistance element, a film capacitor, a film inductance, etc. on the same substrate, several metal thin film layers are deposited and patterned.

In the manufacturing process of this hybrid thin film integrated circuit, for example, when manufacturing a resistor element, the thin film layer is composed of at least two layers: a resistor film shoulder and a conductor (electrode) layer, and each layer is etched using a photoetching method. When performing pattern formation, the bibrow shaped pattern is formed by partially overlapping resistive elements on the first layer. When positioning by overlapping, it is important to perform the work precisely because it is necessary to bring the resistance value close to the standard value (design value). FIGS. 1 a to 1 d show a conventional pattern forming alignment method as a process for manufacturing a resistive element.
This will be explained with reference to FIGS. 2a and 2b.

FIGS. 1 and 2 schematically illustrate an example of the tantalum-based thin film resistor manufacturing process using a cross-sectional view, an enlarged cross-sectional view, and a plan view. First, a resistor is formed on the entire surface of the substrate 1 (FIG. A body film (tantalum nitride film) 2 is produced. Next, after applying photoresist (photosensitive resin), resist processing such as exposure and development is performed using a mask (a mask consisting of a light-transmitting part and an opaque part) shaped in the desired pattern and alignment mark pattern. Then, a photoresist pattern is formed, and then unnecessary portions are etched away using a resistor film etchant (etching solution), and the resist is further peeled off to form the desired pattern of the resistor film 2 and the alignment pattern 3 ( Figure 1b) is obtained. Next, Figure 1c
A conductive metal film 4 (nichrome-gold) is formed on the entire surface of the substrate 1 by sputtering as shown in FIG. Thereafter, in the same way as forming the resistor film pattern, photoresist is applied, and a mask having the desired conductor pattern and alignment mark pattern is used to expose the resistor pattern previously formed under the conductor metal film 4. It is necessary to align with 2. Therefore, in order to perform this alignment, it is necessary to overlap the alignment pattern on the mask and the alignment pattern under the conductor metal film 4 through the conductor metal film 4. The alignment pattern under the conductive metal film 4 at this time is shown in Figure 2a.
As shown in FIG. 3B, this can be confirmed by observing the difference in level between the substrate and the pattern using light reflection, making it possible to overlap the pattern with the mask. After alignment using the above method, resist processing such as exposure and development is performed, and unnecessary metal film is removed using a corrosive solution for the conductor metal film 4. After that, the resist pattern is peeled off to form the desired conductor. By obtaining the pattern d in FIG. 1, it is possible to manufacture a thin film resistive element. However, in this method, in the alignment during exposure for overlapping the resistor film pattern 2 and the mask for forming a conductor photoresist pattern, the three-dimensionality of the alignment pattern under the conductor metal film 4 depends on the unevenness of the ceramic substrate. Due to surface roughness), the height of the pattern from the substrate surface is also irregular, which greatly affects the degree of scattering of light reflection, making it difficult to improve alignment accuracy. . The present invention relates to a method for alignment during pattern formation of a hybrid integrated circuit made of multilayer thin films, and an object of the present invention is to improve alignment accuracy.

According to the present invention, by using a ceramic substrate having a partial glaze film at a position outside the desired pattern formation area,
A method for forming a pattern for a hybrid thin film integrated circuit is obtained, which is characterized in that an alignment pattern is formed on this glaze.

Hereinafter, the present invention will be explained in detail with reference to FIGS. 3 and 4.

3A to 3D and FIGS. 4A and 4B are a sectional view, an enlarged sectional view, and a plan view showing the manufacturing process of a tantalum-based thin film resistor element, which is an example of the manufacturing process of a hybrid thin film integrated circuit according to the present invention.

As shown in FIG. 3a, a partial glaze 6 with a thickness of several tens of microns is provided at a position outside the desired pattern forming area of the substrate 1 by coning and baking a glass material to take advantage of the smoothness of the glass surface. After that, a resistor film (
A tantalum nitride film) 2 is produced. Next, after applying photoresist, a desired pattern and a partial glaze 6 on the substrate 1 are formed.
A photoresist pattern is formed by performing resist processing such as exposure and development using a mask with an alignment mark pattern formed at the dimensional position of , and then unnecessary portions are etched away using a resistor film etchant. Then, by peeling off the resist pattern, a desired pattern of the resistor film 2 and an alignment pattern 3 are formed on the ceramic surface and the glaze surface, respectively, as shown in FIG. 3B. Next, as shown in FIG.
In the same way as pattern formation, photoresist is applied and a mask with the desired conductor pattern and alignment mark pattern is used to align the resistor pattern with the resistor pattern formed under the conductor metal film 4. Alignment is performed by overlapping the alignment pattern formed on the smooth partial glaze 6 at the same time with the alignment pattern of the mask through the conductor metal film 4 when forming the pattern. Since the alignment pattern under the conductive metal film 4 is formed on the glaze 6, the height of the pattern from the glaze surface is constant, and the degree of scattering of light reflection is low, so the outline of the pattern is The image becomes clearer, and the overlay, or positioning, with the mask becomes more reliable. After alignment as described above, the desired pattern shown in FIG. A conductor (electrode) pattern is obtained. This method
Compared to the conventional method, the pattern outline of the alignment mark under the conductor film becomes unclear due to the surface pattern of the ceramic surface in the conventional method, but according to the present invention, the fired glazed surface of the glass material Since the smoothness is greater than that of the ceramic surface, the pattern outline of the alignment mark on the glazed surface becomes clearer, making it easier to align the pattern with the mask, that is, the desired pattern of the second and subsequent layers relative to the desired pattern of the first layer. This has the advantage of increasing the accuracy of alignment.

[Brief explanation of the drawing]

1A to 1D and FIGS. 2A and 2B schematically illustrate the pattern forming process of a conventional thin film resistive element using a sectional view, an enlarged sectional view, and a plan view. 3A to 3D and FIGS. 4A and 4B schematically illustrate an example of pattern formation of a thin film resistive element according to the present invention using a sectional view, an enlarged sectional view, and a plan view. 1...Ceramic substrate, 2...Resistor film (tantalum nitride film), 3.
...Positioning pattern consisting of resistor film, 4...
- Conductor film, 5... light beam, 6... glaze. Figure 2 Figure 3 Younger brother Figure 4

Claims (1)

[Claims] 1. A method for patterning a hybrid thin film integrated circuit, which comprises using a substrate having a partial glaze film at a position different from the desired pattern formation area, and forming an alignment pattern on the glaze.