JPH04100207A - Positioning mark forming method for electron-beam exposure - Google Patents

Abstract

PURPOSE:To reduce the occupying area of positioning marks on a silicon substrate by forming a film of a substance which makes the etching selecting ratio larger against the SiO2 film of the silicon substrate on the SiO2 film and etching the whole area of the positioning marks by exposure after forming the first positioning mark in a projecting form. CONSTITUTION:This method contains a process for forming a film of a substance which makes the etching selecting ratio larger against the SiO2 film 2 on the film 2 of a silicon substrate l, process form forming the first positioning mark in a projecting form by etching the film of the substance, and process for etching the whole area of positioning marks 3M by exposure at the time of etching a layer formed later. For example, aluminum 3 is used as the substance which makes the etching selecting ratio larger against the SiO2 film 2. In addition, the positioning marks 3M are formed by setting the first and second mark areas as the mark area and alternately utilizing the first and second marks whenever the layer to be etched is changed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for forming alignment marks for electron beam exposure that reduces the area occupied on a silicon substrate.

[Conventional technology]

One of the methods for drawing patterns for LSIs (Large Scale Integrated Circuits) is the electron beam direct drawing method, in which patterns are drawn directly on a substrate using an electron beam. LSI has a multilayer structure, and since a predetermined location on the upper layer must be placed over a predetermined location on the lower layer by T degrees, it is necessary to align the layers. To this end, alignment marks must be formed on the substrate that provide information as reference positions. FIG. 4 shows a perspective view of the alignment mark. In FIG. 4, 1 is a silicon substrate, 2 is S10, M,
2-1 is a recessed portion, 2M is an alignment mark, and A is a mark area. Conventionally, the alignment mark 2M is formed by depositing the SiO□ film 2 on the silicon substrate 1, securing a mark area A in a part of the silicon substrate 1, and etching it. In the example shown in FIG. 4, by forming the recess 2-1 by etching, the alignment mark 2M is naturally formed to protrude from the bottom of the recess. FIG. 3 is a diagram illustrating such alignment marks. Figure 3 (a) is a view of mark area A in Figure 4 viewed from above, and Figure 3 (b) is a cross section taken along line I-1 in Figure 3 (a). The figure shows. The reference position can be determined by scanning the alignment mark 2M in the X direction and the Y direction with an electron beam, and checking the reflected signal. FIG. 3(C) shows the waveform of the reflected signal W at that time, and a peak appears when scanning directly above the alignment mark 2M. This peak allows the reference position to be known. Although the above-described alignment mark 2M has a protruding shape, it can also be formed in a concave shape from the surroundings. In the second embodiment described later, such a shape is used (alignment mark 2 M in Fig. 2(a)).
+Reference). The alignment marks are formed in the layer that is about to be etched and are scanned with the electron beam used to soften the etching pattern, so that the scanned portions of the alignment marks are also etched. However, since some of the alignment marks are destroyed, the alignment marks can only be used once. This is because when a partially destroyed item is used again, the destroyed part may be scanned again, but the reference position cannot be detected accurately. In addition, as conventional documents regarding alignment marks for electron beam exposure, there are, for example, JP-A-63-53924 and JP-A-63-164215.

[Problem M that the invention attempts to solve]

Problem C) The conventional alignment mark for electron beam exposure described above is
Since a dedicated mark area was secured and formed for each layer of the multilayer structure, there was a problem in that the number of mark areas equal to the number of layers in the multilayer structure was required. (Explanation of the problem) As mentioned above, the alignment marks formed by the conventional method are destroyed after one use, so it is necessary to provide each layer to be formed with its own alignment mark. Therefore, it is necessary to secure a mark area corresponding to the number of layers to form the mark. FIG. 5 and FIG. 6 are diagrams showing four mark areas,
A, B, C, and D are mark areas, respectively. When manufacturing an LSI with a four-layer structure, it is necessary to secure four mark areas in this way, which reduces the area for forming circuit elements. The present invention aims to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the following measures were taken in the method of forming alignment marks for electron beam exposure of the present invention. That is, there is a step of depositing a material having a high etching selectivity with respect to a 3.08 film on the SiO, II silicon substrate, and etching the film of the material into a shape in which the first alignment mark is projected. The method includes a step of forming the alignment mark, and a step of etching the mark area of the alignment mark by exposing the entire surface thereof when etching the formed layer. For example, aluminum can be used as the substance having a high etching selectivity with respect to the Sto film. Further, a first mark area and a second mark M area are set as mark areas, and each time the layer to be etched changes, the first mark area and the second mark area M are set as mark areas. The alignment marks were formed by alternately using the second mark areas.

[For production]

In the method of forming the first alignment mark in a protruding shape using a material having a high etching selectivity with respect to the StOt film, it is possible to use only one mark area. Further, in the method of forming alignment marks by alternately using the first mark area and the second mark area, it is possible to use only two mark areas. Therefore, the method of the present invention requires only one or two mark wI areas 1a even if the number of multilayer LSIs increases.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. [First Embodiment 2 A first embodiment of the present invention is shown in FIGS. 1(a) to 1[ff1rC]. In this example, only one mark area is required, and the first alignment mark to be formed is etched with a material (with a high etching selectivity for the S,02 film).
It is made of a material f) that is difficult to be etched when the 5,0□ film is etched, and is designed to continue protecting it. In these figures, ■ is a silicon substrate, 2 is S, O□
The films 2M and 3M are alignment marks, 3 is an aluminum film, 4 is a resist, 4-1 to 4-4 are resist recesses, 5 is a first aluminum film, and 7 is a second aluminum film. 1(a) (a) to FIG. 1(c) (wa) are the formation and processing of alignment marks when forming a four-layer LSI on the silicon base Fi,1. The process of (1) From (a) to (c) in Figure 1 (a), the first alignment mark 3M
This is the process of forming. First, place S on the silicon substrate 1.
A 10□ film 2 is formed, and an aluminum film 3 is deposited thereon. This film is deposited using a normal Svanta device and has a thickness of about 8,000 coats. Aluminum is an example of a substance that has a high etching selectivity with respect to the S and Ot films 2. (2) Figure 1 (a) (b): Coat the resist 4 on the aluminum film 3, and apply the resist only to the areas where alignment marks are to be formed by patterning and development using an exposure machine using a normal mask. 4
The remaining portion becomes a resist recess 4-1 from which the resist has been removed. (3) (c) in FIG. 1(a) After etching, the resist 4 is removed to obtain alignment marks 3M made of aluminum. This is the first alignment mark. (4) FIG. 1(a) (d) (d) is a top view of the alignment mark 3M formed as described above. The cross-sectional view taken along the line ■-■ is the figure (c). (5) (e) in FIG. 1(b) First, a contact hole is drawn. Therefore, first apply the resist 4, then perform alignment using the alignment mark 3M as a reference (even if it is covered with the resist 4, the alignment mark 3M can be detected through it), and A first contact hole (not shown) is drawn using an electron beam (1st contact drawing). At the same time, the entire area around the alignment mark 3M is also exposed with the electron beam. When this is developed, the area around the alignment mark 3M becomes a resist recess 4-2 as shown in (e). (6) (to) of FIG. 1(b) Etch the S,02 film 2 according to the pattern of the resist 4. S, O, and 2M, which is a part of the film 2, remain below the alignment mark 3M, and this and the alignment mark 3M
Together, they form an alignment mark. This gives the alignment mark a steeper shape. ('7) (g) in FIG. 1(b) A first aluminum film 5 is deposited to a thickness of approximately 8,000 mm using an ordinary sputtering device. After applying a resist 4 thereon, a pattern for etching the aluminum layer is drawn. At this time, the entire mark area (that is, the periphery of the alignment mark) is exposed to light. (8) (H) in FIG. 1(b) Develop the resist 4. The resist 4 in the mark area portion exposed entirely to light is removed to form a resist recess 4-3. (9) Etching the first aluminum film 5 (see (b) in FIG. 1). Since the first aluminum film 5 is used as a wiring layer, desired wiring is realized by this etching. 0ω (nu) in FIG. 1(c) A CVD oxide film 6 of about 1 μm is deposited as a film for insulating between the eyebrows, and a resist 4 is applied thereon. Then, a second contact hole is drawn with an electron beam (2nd contact drawing), and at the same time, the entire area around the alignment mark (mark area) is exposed. The 2nd contact is for connecting the wiring in the first aluminum film 5 and the wiring to be formed later on the CVD oxide film 6. 01) (L) in FIG. 1(C) Develop the resist 4. Since the entire surface of the resist 4 in the mark area is exposed, it is removed by development and a resist recess 4-4 is formed. (2) (2) in FIG. 1(c) After etching the CVD oxide film 6 (2nd contact etching), the remaining resist 4 is removed. (W) in FIG. 1(c) A second aluminum film 7 is deposited to a thickness of about 1 μm using a normal sputtering device. When patterning the second aluminum film 7 to form the second wiring layer, it can be formed in the same manner as when patterning the first aluminum film 5 to form the first wiring layer. Even as the process of forming the multilayer structure progresses as described above, the initial alignment marks are saved and continue to be used. Therefore, the area required for the mark area is only one mark area, and the area for forming the circuit element becomes large. [Second Embodiment] FIGS. 2(a) to 2(b) show a second embodiment of the present invention. This example is an example in which only two mark areas are required. . The two mark areas are used alternately each time the layer to be processed changes. In these figures, symbols are used in Figures 1(a) to 1(c).
) corresponding to those of 2M+, 2Mg, 8M,, 8M
The mark is an alignment mark, and A and B are mark areas. As mentioned above, the shape of the alignment mark may be a shape that protrudes from the surroundings, or conversely, it may be a shape that is recessed from the surroundings. In this embodiment, a shape that is recessed is used. It is said that 2(a) (a) to FIG. 2(b) (h) are the process of forming and processing alignment marks when forming a four-layer LSI on the silicon substrate 1. shows. (1) (b) in Figure 2(a) Prepare spaces for two locations A and B as the mark H area. Then, a resist is applied and a film of SiO, Ill! is deposited on the silicon substrate l! Before drawing the pattern for etching 2, draw the mark H area A.
A positioning mark 2M is formed, and (A) is a top view in that state. (2) First alignment mark 2M in mark area A (b) in FIG. 2(a). A cross-sectional view of the state in which is formed is shown. (3) (c) in FIG. 2(a) After applying the resist 4, align it using the alignment mark 2M1 as a reference, and SiO,! ! A pattern for etching 12 is drawn using an electron beam. At this time, the following drawings are simultaneously performed on mark areas A and H, respectively. ■For mark area B... In order to form a positioning mark to be used next, the shape of the mark is drawn. ■For mark area A...To make mark area A a blank area, full-surface exposure drawing is performed. That is, the first alignment mark 2 M + is erased to make room for forming the next alignment mark. After drawing as described above and developing the resist 4, the state of the mark areas A and B is as shown in (c), where a resist recess 4-1 is formed in the mark area B, and the mark area A is A resist recess 4-2 is formed in the area. (3) (d) in FIG. 2(a) When the Sing film 2 is etched, all of the SiO□ film 2 in the mark area A is removed, and the S, 0□ film removed portion 2 is removed.
-2 can be done. Further, in the mark area B, an alignment mark 2 Mz is formed corresponding to the resist recess 4-1. (3) (e) in FIG. 2(a) An aluminum film 8 is deposited. alignment mark 2M,
is concave, so the surface of the aluminum film above it is concave. This recess is used as the next alignment mark 8M. A resist 4 is applied onto the aluminum film 8, and a pattern for etching the aluminum film 8 is drawn using an electron beam while aligning with the alignment mark 8 M + as a reference. At the same time, the following drawings are performed for mark areas A and B, respectively. ■For mark area A... To form the alignment mark to be used next, draw the shape of the mark. The alignment mark to be used next is the aluminum film 8.
It is formed by leaving a part of the surface, and its shape becomes prominent. (2) For mark area B... In order to remove all of the aluminum film 8 in mark area B, drawing is performed to expose the entire area. That is, if the aluminum film 8 is completely removed, the alignment mark 2Mz will appear after that, and this can be used as the next alignment mark. (4) (to) in FIG. 2(b) Next, the resist 4 is developed. Regarding mark area A,
A portion of the resist 4 remains in order to form the next alignment mark. (5) FIG. 2(b) (g) It is a top view of the state shown in FIG. 2(b) (f). (6) (h) in FIG. 2(b) After etching the aluminum film 8, the remaining resist 4 is removed. As a result, in the mark area A, there is an alignment mark 8M to be used next. is formed, and in mark area B, alignment mark 2M
g reappears. In this way, in the second embodiment, two mark areas are prepared and these are used alternately to form the next alignment mark to be used when processing the previous layer, so a multilayer structure with three or more layers can be formed. Even in an LSI like this, only two mark areas are required. Although it is assumed that the first alignment mark is not formed in the mark area B (see (a) and (b) in Fig. 2 (a)), it may be formed. is shown in Figure 2 (
When drawing the resist 4 in step (c) of a), it is not necessary to draw the resist 4 so as to form the resist recess 4-1.

【Effect of the invention】

As described above, according to the method for forming alignment marks for electron beam exposure of the present invention, even if the number of LSIs with a multilayer structure is large, the number of mark areas can be one or two. Therefore, the area occupied by the mark region on the surface of the silicon substrate becomes smaller than in the past, and the area that can be used for forming circuit elements can be expanded accordingly.

[Brief explanation of drawings]

Fig. 1(a) to Fig. 1(c)... Diagrams showing the first embodiment of the present invention Fig. 2(a) to Fig. 2(b)... Second embodiment of the present invention Figure 3 shows an example...Figure 4 explains the alignment mark...
・Perspective views of alignment marks Figures 5 and 6...In Figure 7 showing four mark areas, 1 is a silicon substrate;
2 is S, 0□ film, 2-2 is S, 0. Film removal recess, 2M,
2M. 2Mz, 3M, 8M+, 8Mt are alignment marks, 3 is aluminum film, 4 is resist, 4I or 4-
4 is a resist recess, 5 is a first aluminum film, and 7 is a second
Aluminum film 8 is an aluminum film. Patent Applicant Fuji Xerox Co., Ltd. Representative Patent Attorney Tomio Honjo Figure 2 (b) No. 5 No. 6

Claims (3)

[Claims] (1) A step of depositing a material having a high etching selectivity with respect to the SiO_2 film on the SiO_2 film of the silicon substrate, and etching the film of the material to form a first alignment mark in a protruding shape. A method for forming an alignment mark for electron beam exposure, the method comprising the steps of: exposing and etching the entire mark region of the alignment mark when etching the subsequently formed layer. (2) The method for forming alignment marks for electron beam exposure according to claim 1, characterized in that aluminum is used as the material having a high etching selectivity with respect to the SiO_2 film. (3) Setting a first mark area and a second mark area as mark areas, and forming alignment marks by alternately using the first and second mark areas each time the layer to be etched changes. A method for forming alignment marks for electron beam exposure, characterized by: