JPH0350719A - Formation of fine pattern - Google Patents

Formation of fine pattern

Info

Publication number
JPH0350719A
JPH0350719A JP18671089A JP18671089A JPH0350719A JP H0350719 A JPH0350719 A JP H0350719A JP 18671089 A JP18671089 A JP 18671089A JP 18671089 A JP18671089 A JP 18671089A JP H0350719 A JPH0350719 A JP H0350719A
Authority
JP
Japan
Prior art keywords
film
resist
pattern
forming
ion etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18671089A
Other languages
Japanese (ja)
Inventor
Takeo Hashimoto
橋本 武夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18671089A priority Critical patent/JPH0350719A/en
Publication of JPH0350719A publication Critical patent/JPH0350719A/en
Pending legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a more fine slit and a hole like pattern by removing selectively an inclined part on the sidewall of an upper resist pattern or a lower resist film directly below an overexposed dot like pattern part by reactive ion etching in a two-layer resist process. CONSTITUTION:A lower resist film 2 is formed on a semiconductor substrate 1 and an upper resist film 3 is formed on the above resist film and then, they are exposed by irradiating them with light 4 through a mask. Further, they are developed to form a positive type pattern 5 and a sputtering inorganic film 6 consisting of a silicon oxide is deposited and formed. Subsequently, the sputtering inorganic film 6 only at the inclined part of the resist pattern 5 is removed completely by reactive ion etching to expose the surface of a resist material and then, the resist pattern other than an exposed surface is covered with sputtering inorganic film 7 that is left selectively. After that, the resist pattern 5 and the lower resist film 2 are dry-etched by using a reactive ion etching device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の製作における各種半導体基体
への微細パターンの形成方法に関し、特に段差を有する
各種半導体基体への微細パターンの形成方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of forming fine patterns on various semiconductor substrates in the production of semiconductor integrated circuits, and particularly relates to a method of forming fine patterns on various semiconductor substrates having steps. .

〔従来の技術〕[Conventional technology]

従来、微細パターンの形成方法としては、高解像度な露
光機及びレジストを用いるほかに、多層レジスト法が一
般的に知られている0本発明も多層レジスト法と呼ばれ
る方法に属するものであり、最も近い例としては、J、
EIectrochem、Soc。
Conventionally, as a method for forming fine patterns, in addition to using high-resolution exposure equipment and resists, the multilayer resist method is generally known. The present invention also belongs to the method called the multilayer resist method, and is the most A close example is J.
EIectrochem, Soc.

198g、VOl、135  N[Lll、P286に
記載された5pin−On−Glass Image 
Reversal  (S OG I R)法がある。
198g, VOl, 135N[Lll, 5pin-On-Glass Image described in P286
There is a Reversal (SOG I R) method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の多層レジスト法即ち、3層レジスト法や
P CM (Portable Comformabl
e Mask)と呼ばれる2層レジスト法及び5OGI
R法は、段差基板においても、上層に用いるレジスト材
を用いて平坦な基板上にパターン形成する場合と同等の
解像力を維持しパターン形成することができるが、それ
以上の解像力を得ることは不可能であった。
The above-mentioned conventional multilayer resist methods, such as the three-layer resist method and PCM (Portable Conformable
Two-layer resist method called e Mask) and 5OGI
With the R method, it is possible to form a pattern on a stepped substrate while maintaining the same resolution as when forming a pattern on a flat substrate using a resist material used as an upper layer, but it is impossible to obtain higher resolution. It was possible.

上述した従来の多層レジスト法に対し、本発明は2層レ
ジスト法において、上層レジストとしてポジ型レジスト
を用い、過剰露光によりマスク寸法に対しパターン寸法
が小となったパターンを下層レジストへの転写パターン
として用いたり、あるいはレジストパターンの側壁の傾
斜部のみを下層レジストへの転写パターンとして用いる
という相違点を有する。
In contrast to the conventional multilayer resist method described above, the present invention employs a two-layer resist method in which a positive resist is used as the upper layer resist, and a pattern whose pattern size has become smaller than the mask dimension due to overexposure is transferred to the lower layer resist. The difference is that only the sloped portion of the side wall of the resist pattern is used as a pattern to be transferred to the underlying resist.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の微細パターンの形成方法は、半導体基体上に直
接もしくは該基体とは異なる物質膜を介して有機物より
なる第1の被膜を形成する工程と、前記第1の被膜上に
感応性樹脂よりなる第2の被膜を形成する工程と、前記
第2の被膜をマスクを介して露光する工程と、前記第2
の被膜を現像液で現像しパターンを形成する工程と、前
記第2の被膜よりなるパターン上に無機物よりなる第3
の被膜を形成する工程と、前記第3の被膜の一部分のみ
を完全に除去する工程と、平行平板よりなるアクティブ
イオンエツチング装置を用いて選択的に残された第3の
被膜をマスクとして前記第1及び第2の被膜をドライエ
ツチングする工程とを有している。
The method for forming a fine pattern of the present invention includes the steps of forming a first film made of an organic material on a semiconductor substrate directly or through a film of a material different from the substrate, and forming a first film made of an organic material on the first film with a sensitive resin. a step of exposing the second film to light through a mask; and a step of exposing the second film to light through a mask.
A step of developing the film with a developer to form a pattern, and developing a third film made of an inorganic material on the pattern made of the second film.
a step of completely removing only a portion of the third coating; and a step of completely removing only a portion of the third coating, and using the selectively left third coating as a mask using an active ion etching device consisting of parallel plates. and dry etching the first and second coatings.

〔実施例〕〔Example〕

第1図(a)〜(e)は本発明の第1の実゛施例の微細
なスリットパターンを形成する方法を工程順に示した模
式図である。
FIGS. 1(a) to 1(e) are schematic diagrams showing the method of forming a fine slit pattern according to the first embodiment of the present invention in the order of steps.

第1図(a)では、半導体基体1上にポジ型フォトレジ
スト、例えば東京応化製の0FPR800を塗布し、次
いでクリーンオーブンを用い250° 60分の熱処理
条件で加熱処理し厚さ2.0μmの下層レジスト被膜2
を形成し、この上にポジ型フォトレジスト、例えば東京
応化製のTSMR8900を0.8μmの膜厚で塗布し
て上層レジスト被膜3を形成し、マスクを介してg線(
λ=436nm)の照射光4で露光した様子を示しであ
る。
In FIG. 1(a), a positive photoresist, such as 0FPR800 manufactured by Tokyo Ohka Co., Ltd., is coated on a semiconductor substrate 1, and then heat-treated in a clean oven at 250° for 60 minutes to form a 2.0 μm thick film. Lower resist film 2
A positive photoresist, such as TSMR8900 manufactured by Tokyo Ohka Co., Ltd., is applied thereon to a thickness of 0.8 μm to form an upper resist film 3.
This figure shows the state of exposure with irradiation light 4 of λ=436 nm).

その後適当な現像液、例えば東京応化製のNMD−3で
60秒間現像し、ポジ型のレジストパターン5を形成し
たのが第1図(b)である。
Thereafter, development was carried out for 60 seconds using a suitable developer, such as NMD-3 manufactured by Tokyo Ohka Co., Ltd., to form a positive resist pattern 5, as shown in FIG. 1(b).

第1図(C)にはスパッタによりシリコン酸化物よりな
る被膜、すなわちスパッタ無機膜6を膜厚0.3μmで
被着形成した様子を示しである。
FIG. 1C shows a state in which a film made of silicon oxide, ie, a sputtered inorganic film 6, is deposited to a thickness of 0.3 μm by sputtering.

次いで、CHF、と02ガスを用いなりアクティブイオ
ンエツチングによりエッチバックを行ない、レジストパ
ターン5の傾斜部のみシリコン酸化物であるスパッタ無
機膜6を完全に除去し、レジスト材の表面を露出させ、
露出面以外は選択的に残されたスパッタ無機膜7で覆わ
れる。この状態を図示したのが第1図(d)である。
Next, etchback is performed by active ion etching using CHF and 02 gas to completely remove the sputtered inorganic film 6 made of silicon oxide from only the inclined portions of the resist pattern 5 and expose the surface of the resist material.
Areas other than the exposed surface are covered with a selectively left sputtered inorganic film 7. This state is illustrated in FIG. 1(d).

その後、02ガスを用いたりアクティブイオンエツチン
グ装置により、選択的に残されたスパッタ無機膜7をマ
スクとして、レジストパターン5と下層レジスト被膜2
をドライエツチングする。
Thereafter, the resist pattern 5 and the lower resist film 2 are etched using the selectively left sputtered inorganic film 7 as a mask using 02 gas or an active ion etching device.
Dry etching.

以上により通常の多層レジスト法では得られない微細な
スリットパターンが得られる。この様子を第1図(e)
に示す。
Through the above process, a fine slit pattern that cannot be obtained with a normal multilayer resist method can be obtained. This situation is shown in Figure 1(e).
Shown below.

第2図(a)〜(e)は本発明の第2の実施例である微
細な穴パターンを形成する方法を工程順に示した模式図
である。
FIGS. 2(a) to 2(e) are schematic diagrams showing a method for forming a fine hole pattern according to a second embodiment of the present invention in order of steps.

第2図(a)は1.0μmの段差を有する半導体基体1
上に、第1の実施例と同じく膜厚2.0μmの下層レジ
スト被膜2を形成した様子を示しである。
FIG. 2(a) shows a semiconductor substrate 1 having a step of 1.0 μm.
A lower resist film 2 having a film thickness of 2.0 μm is formed on top as in the first example.

次いで矩形形状を与える高解像ポジ型フォトレジスト、
例えば東京応化製のTSMR−V3を1.0μmの膜厚
で塗布し、上層レジスト被膜3を形成し、マスクを介し
て紫外線のg線による照射光4で露光した状態を第2図
(b)に示した。
Next, a high-resolution positive photoresist that gives a rectangular shape;
For example, TSMR-V3 manufactured by Tokyo Ohka Co., Ltd. is applied to a thickness of 1.0 μm to form an upper resist film 3, and the state is exposed to irradiation light 4 of ultraviolet g-rays through a mask as shown in FIG. 2(b). It was shown to.

Po5t Exposure Bake (P 、 E
 、 B )をダイレクトホットプレート上で120℃
、60秒の条件で実施した後、有機アルカリ現像液例え
ば東京応化製のNMD−3を用い、60秒間現像してレ
ジストパターン5を得た。この様子を第2図(C)に示
す。
Po5t Exposure Bake (P, E
, B) directly on a hot plate at 120°C.
, for 60 seconds, and then developed for 60 seconds using an organic alkaline developer such as NMD-3 manufactured by Tokyo Ohka Co., Ltd. to obtain resist pattern 5. This situation is shown in FIG. 2(C).

第2図(c)の平面図が第3図である。第3図に示され
たとおり、第2図(C)のレジストパターン5はドツト
状パターンであり直径0.4μmである。この様な微細
なドツト状パターンは、マスク上0.6μmロ程度のパ
ターンを開口数0.5以上のレンズを搭載したg線ステ
ッパーを用い過剰露光することによって得られた。
FIG. 3 is a plan view of FIG. 2(c). As shown in FIG. 3, the resist pattern 5 in FIG. 2(C) is a dot-like pattern and has a diameter of 0.4 μm. Such a fine dot-like pattern was obtained by overexposing a pattern of approximately 0.6 μm on a mask using a G-line stepper equipped with a lens having a numerical aperture of 0.5 or more.

次いで5i02系塗布膜8、例えば東京応化製0CDT
ype2を0.3μmの膜厚で塗布し、ホットプレート
上で110℃、5分の条件で熱処理を加えたのが第2図
(d)である。
Next, a 5i02-based coating film 8, for example, 0CDT manufactured by Tokyo Ohka Co., Ltd.
FIG. 2(d) shows a case in which YPE2 was applied to a film thickness of 0.3 μm and heat treated on a hot plate at 110° C. for 5 minutes.

0□ガスを用いたりアクティブイオンエツチングにより
、SiO□系塗布膜8をマスクとしてレジストパターン
5と下層レジスト被膜2をドライエツチングし、微細な
穴状パターンを得た状態を示したのが第2図(e)であ
る。
Figure 2 shows a state in which a fine hole-like pattern is obtained by dry etching the resist pattern 5 and the lower resist film 2 using the SiO□-based coating film 8 as a mask using 0□ gas or active ion etching. (e).

なお露光用の照射光4として、遠紫外光、電子線、X線
等を用いることもできる。
Note that far ultraviolet light, electron beams, X-rays, etc. can also be used as the irradiation light 4 for exposure.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、2層レジスト法において
上層レジストパターンの側壁の傾斜部分やあるいは過剰
露光したドツト状パターン部直下の下層レジスト被膜を
選択的にリアクティブイオンエツチングにより除去する
ことにより、従来の多層レジストで得られるパターンと
比較して、より微細なスリットや穴状パターンを形成で
きる効果がある。
As explained above, in the two-layer resist method, the present invention selectively removes the inclined portion of the side wall of the upper resist pattern or the lower resist film directly under the overexposed dot-shaped pattern portion by reactive ion etching. Compared to patterns obtained with conventional multilayer resists, it has the effect of forming finer slit and hole-like patterns.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明の第1の実施例を工程順
に示した模式図、第2図(a)〜(e)は本発明の第2
の実施例を工程順に示した模式図、第3図は第2図(c
)の平面図である。 1・・・半導体基体、2・・・下層レジスト被膜、3・
・・上層レジスト被膜、4・・・照射光、5・・・レジ
ストパターン、6・・・スパッタ無機膜、7・・・選択
的に残されたスパッタ無機膜、8・・・5i02系塗布
膜。
FIGS. 1(a) to (e) are schematic diagrams showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (e) are schematic diagrams showing the second embodiment of the present invention.
Fig. 3 is a schematic diagram showing the example in the process order, and Fig. 2 (c
) is a plan view of DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Lower resist coating, 3...
... Upper resist film, 4... Irradiation light, 5... Resist pattern, 6... Sputtered inorganic film, 7... Sputtered inorganic film selectively left, 8... 5i02-based coating film .

Claims (1)

【特許請求の範囲】[Claims] 半導体基体上にレジスト材よりなる第1の被膜を形成す
る工程と、この第1の被膜上にレジスト材よりなる第2
の被膜を形成する工程と、この第2の被膜をマスクを介
して露光する工程と、この第2の被膜を現像液で現像す
る工程と、この第2の被膜上に無機物よりなる第3の被
膜を形成する工程と、この第3の被膜を一定の膜厚だけ
除去する工程と、平行平板よりなるリアクティブイオン
エッチング装置を用いて選択的に残された第3の被膜を
マスクとして前記第1及び第2の被膜よりなる二層膜を
ドライエッチングする工程を有することを特徴とする微
細パターンの形成方法。
forming a first film made of a resist material on the semiconductor substrate; and forming a second film made of a resist material on the first film.
a step of exposing this second film to light through a mask, a step of developing this second film with a developer, and a step of forming a third film made of an inorganic material on this second film. a step of forming a film, a step of removing this third film by a certain thickness, and a step of removing the third film selectively using the remaining third film as a mask using a reactive ion etching device consisting of parallel plates. A method for forming a fine pattern, comprising the step of dry etching a two-layer film consisting of a first and second film.
JP18671089A 1989-07-18 1989-07-18 Formation of fine pattern Pending JPH0350719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18671089A JPH0350719A (en) 1989-07-18 1989-07-18 Formation of fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18671089A JPH0350719A (en) 1989-07-18 1989-07-18 Formation of fine pattern

Publications (1)

Publication Number Publication Date
JPH0350719A true JPH0350719A (en) 1991-03-05

Family

ID=16193285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18671089A Pending JPH0350719A (en) 1989-07-18 1989-07-18 Formation of fine pattern

Country Status (1)

Country Link
JP (1) JPH0350719A (en)

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