JPS61121332A - Pattern forming method - Google Patents

Pattern forming method

Info

Publication number
JPS61121332A
JPS61121332A JP59242364A JP24236484A JPS61121332A JP S61121332 A JPS61121332 A JP S61121332A JP 59242364 A JP59242364 A JP 59242364A JP 24236484 A JP24236484 A JP 24236484A JP S61121332 A JPS61121332 A JP S61121332A
Authority
JP
Japan
Prior art keywords
resist
pattern
layer resist
upper layer
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59242364A
Other languages
Japanese (ja)
Inventor
Masashi Miyagawa
昌士 宮川
Yasuhiro Yoneda
泰博 米田
Shunichi Fukuyama
俊一 福山
Kota Nishii
耕太 西井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59242364A priority Critical patent/JPS61121332A/en
Publication of JPS61121332A publication Critical patent/JPS61121332A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve productivity reducing the process by suitable combination of an upper layer resist member, a lower layer resist member, developer and liquid rinse as the case may be. CONSTITUTION:A lower resist thick layer made by a resist member not contained an Si, which can be etched by means of plasma treatment and is insoluble to developer using for formation of an upper layer pattern, and an upper resist thin film made by a resist member contained an Si for sensitive ionizing radiation possessed anti-plasma etching are formed by turns on the surface of a member to be produced. For example, which is provided by resoluting polyvinylphenol to cychohexane is spin-coated on an Si substrate 1 and is baked, then a lower layer resist film 2 is provided. The resolution, which is provided by dissolving silylated polymethylsilsesquioxane in toluene, is spin-coated on the lower layer resist film 2 and is baked, then a upper layer resist film 3 is obtained. Subsequently, a latent image is formed to the upper layer resist thin film by projecting an image pattern of ionizing radiation, and latent image is developed, then plasma treatment is performed by means that the upper layer resist pattern is designated as a mask, then the upper layer resist pattern is duplexed to the lower layer resist thin film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、リソグラフィー技術、特に、半導体集積回路
、バブルメモリー素子などの製造時に微細加工を行なう
のに有用な、電子線、X線、遠紫外線、イオンビームな
どの電離放射線を用いたリソグラフィー技術に関する。
Detailed Description of the Invention [Industrial Application Field] The present invention relates to lithography technology, particularly to electron beam, Related to lithography technology using ionizing radiation such as ultraviolet rays and ion beams.

本発明は、さらに詳しく述べると、上述のような電離放
射線の像パターンを二層構造のレジスト膜に照射及び現
像して先ず上層レジストパターンを得、次いでこのレジ
スト・クターンをその下方の下層レジスト厚膜に転写し
て高アスペクト比のレジストパターンを形成する方法に
関する。ここで、′高アスペクト比”とは、形成された
レジスト・々ターンの膜厚とパターン幅の比が大である
こと、換言すると、より高い寸法精度で微細加工を行な
い得ることを意味する。
More specifically, the present invention first obtains an upper layer resist pattern by irradiating and developing an image pattern of ionizing radiation as described above onto a two-layer resist film, and then converts this resist pattern to a thickness of the lower layer resist below. The present invention relates to a method of forming a high aspect ratio resist pattern by transferring it onto a film. Here, ``high aspect ratio'' means that the ratio between the film thickness of each turn of the formed resist and the pattern width is large, in other words, microfabrication can be performed with higher dimensional accuracy.

〔従来の技術〕[Conventional technology]

半導体デバイスの高集積化に伴なって、より微細なレジ
ストパターンを形成する技術が要求されている。この要
求にこたえて提案され念ものが、先にも述べかつ今ここ
でも問題にしようとしている二層構造のレジスト膜を使
用したノーターン形成方法である。二層構造のレソス)
fは、通常、下層に例えばクレゾールーノゴラ、り樹脂
のような耐ドライエ、チ性の大きな樹脂を厚く、上層に
例えばポリメチルメタクリレートのような感電離放射線
レジストを薄く、それぞれ塗布して二層構造となしたも
のでおる。このようなレジスト膜に電子線描画を行なり
て現像すると、上層レジスト膜が薄いので、微細な上層
レジストパターンを得ることができ、また、このレジス
ト14ターンをマスクとしてその下方の樹脂を酸素プラ
ズマでエツチングすると、上層レジストパターンが下層
樹脂に転写されることの結果、微細で厚膜な、すなわち
、高アスペクト比のレゾス)パターンを得ることができ
る。このパターン形成方法によれば、レジスト膜の下地
の段差の問題を解決し得るばかりでなく、従来単層レジ
スト膜で問題となっていた解像性や耐ドライエ、チ性も
改良することができる。
2. Description of the Related Art As semiconductor devices become more highly integrated, techniques for forming finer resist patterns are required. What has been proposed in response to this demand is the no-turn forming method using a two-layered resist film, which was mentioned earlier and which will be discussed here as well. double-layered structure)
Usually, the lower layer is made of a thick resin with high dryness resistance and oxidation properties such as cresol resin, and the upper layer is made of a thin layer of ionizing radiation resist such as polymethyl methacrylate. It is made with a structure. When such a resist film is subjected to electron beam writing and developed, a fine upper resist pattern can be obtained because the upper resist film is thin.Also, using this 14 turns of resist as a mask, the resin underneath is exposed to oxygen plasma. When etching is performed, the upper layer resist pattern is transferred to the lower layer resin, and as a result, a fine and thick resist pattern, that is, a high aspect ratio resist pattern can be obtained. According to this pattern forming method, it is not only possible to solve the problem of the step difference in the base of the resist film, but also to improve the resolution, drying resistance, and chipping properties that were problems with conventional single-layer resist films. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、二層構造のレジスト膜を選択的に工、チング
して高アスペクト比のレジストパターンを形成しようと
する場合、下層レジスト膜として使用する樹脂材料が制
限されるという問題がおる。
By the way, when attempting to form a resist pattern with a high aspect ratio by selectively etching a two-layer resist film, there is a problem in that the resin material used for the lower resist film is limited.

、実際、現在用い得る樹脂は、先に例示したクレゾール
−ツメう、り樹脂のほか、米国シラグレー社。
In fact, the resins that can be used at present include the cresol-claw resin mentioned above, as well as the resin manufactured by Silagray Co., Ltd. in the United States.

からAZシリーズとして市販されているフォトレジスト
、フェノール樹脂などであシ、また、このような樹脂は
、現像工程での溶解を回避するため、その塗布部に20
0℃前後の高温で1時間はどベーキングすることを必須
の要件とする。このようなベーキング工程は、事実、方
法の実用化の障害となっておフ、工程を省略するかもし
くは短縮することが望ましい。
Photoresists, phenolic resins, etc., commercially available as the AZ series from
It is essential to bake at a high temperature of around 0°C for 1 hour. In fact, such a baking step is an impediment to the practical application of the method, and it is desirable to omit or shorten the step.

〔問題点を解決するための手段〕[Means for solving problems]

本発明者らは、との九び、二層構造のレジスト膜を形成
するに当って、引き続いて上層レジストパターンの形成
に用いられる現像液(及び場合によりリンス液)の性質
を考慮してそれぞれの層の材料を選択するならば、換言
すると、上層レジスト材料、下層し・シスト材料、現像
液、そして場合によりリンス液を適宜組み合わせるなら
ば、上記した問題点を解決し得るということを見い出し
た。
In forming a resist film with a two-layer structure, the present inventors took into consideration the properties of the developing solution (and rinsing solution in some cases) used subsequently to form the upper resist pattern. It has been found that the above-mentioned problems can be solved by selecting the material of the layer, in other words, by appropriately combining the upper resist material, the lower layer/cyst material, the developer, and in some cases, the rinsing solution. .

本発明によれば、上層レジスト・母ターンの形成に用い
られる現像液に不溶でちるけれどもプラズマ処理により
エ、チングされ得る珪素不含レジスト材料からなる下層
し・シスト厚膜(膜厚約0.5〜2.0μm)、そして
耐プラズマエッチ性を有する感電離放射線含珪素レジス
ト材料からなる上層レジスト薄膜(膜厚約0.1〜0.
5μm)を例えばシリコン基板のような被加工部材の表
面に順次形成することによって、二層構造のレジスト膜
を形成することができる。
According to the present invention, the lower layer is made of a silicon-free resist material that is insoluble in the developer used to form the upper resist and master turns but can be etched by plasma treatment. 5 to 2.0 μm), and an upper resist thin film (film thickness of approximately 0.1 to 0.0 μm) made of a silicon resist material containing ionizing radiation and having plasma etch resistance.
5 μm) on the surface of a workpiece such as a silicon substrate, a two-layer resist film can be formed.

レジスト膜の形成後、次の工程を順次実施する:電離放
射線の像パターンを照射して上層レゾスト薄膜に前記像
パターンに対応する潜像を形成させ、 前記潜像を現像液で現像して上層レジストパターンを得
、そして必要に応じてリンスを行ない、前記上層レジス
トパターンをマスクとしてプラズマ処理を行ない、前記
上層レジスト14ターンをその下方の下層レジスト薄膜
に転写する。
After forming the resist film, the following steps are performed sequentially: irradiating an image pattern of ionizing radiation to form a latent image corresponding to the image pattern on the upper layer resist thin film, and developing the latent image with a developer to form the upper layer. A resist pattern is obtained, rinsed if necessary, and plasma processing is performed using the upper resist pattern as a mask to transfer the 14 turns of the upper resist to the lower resist thin film below.

上記した一連の工程は、この技術分野において一般的に
用いられている技法を使用して実施することができ、し
たがって、ここでの詳しい説明を省略する。
The above-described series of steps can be performed using techniques commonly used in this technical field, and therefore detailed description thereof will be omitted here.

1多」目とヴi 本発明において有用な、上層レゾスト材料、下層レジス
ト材料、現像液、そしてリンス液の組み合わせ例をいく
つか例示すると、次の通りである。
Some examples of combinations of the upper resist material, the lower resist material, the developer, and the rinsing solution that are useful in the present invention are as follows.

組み合わせI: フェニルシロをサン 〆ラック 組み合わせ■: iv)  リンス液     水 〔実施例〕 添付の第1a図〜第1d図に断面で示されるような順序
で本例を実施した。
Combination I: Phenylsilo with sun-lacquer Combination ■: iv) Rinse liquid Water [Example] This example was carried out in the order shown in the cross sections in the attached Figures 1a to 1d.

ポリビニルフェノール(M、=27000)を7クロヘ
キサンに溶解して得た溶液をシリコン基板1上にスピン
コードした。塗布溶媒である7クロヘキサンを除去する
ために200℃で20分間にわたってベークしたところ
、膜厚2.0μmの下層レジスト膜2が得られた。次い
で、末端ヒドロ命シル基をトリメチルクロルシランでシ
リル化したシIJ )し化ポリメチルシルセスキオキサ
ン(Mw=、、300000)をトルエンに溶解して得
た溶液を先に形成した下層レジスト膜2上にスピンコー
トシた。前記と同様、塗布溶媒を除去するために80℃
で20分間にわたってベークしたところ、膜厚0.1μ
mの上層レジスト膜3が得られた。第1a図は、上記の
ようにして得られた二層レジスト膜付のシリコン基板の
略示断面図である。
A solution obtained by dissolving polyvinylphenol (M, = 27000) in 7 chlorohexane was spin-coded onto a silicon substrate 1. When baking was performed at 200° C. for 20 minutes to remove the coating solvent 7-chlorohexane, a lower resist film 2 with a thickness of 2.0 μm was obtained. Next, a solution obtained by dissolving in toluene polymethylsilsesquioxane (Mw = 300,000), in which the terminal hydrosilyl group was silylated with trimethylchlorosilane, was added to the previously formed lower resist film. 2. Spin coated on top. As above, the temperature was 80°C to remove the coating solvent.
When baked for 20 minutes at
An upper resist film 3 of m was obtained. FIG. 1a is a schematic cross-sectional view of a silicon substrate with a two-layer resist film obtained as described above.

次いで、得られた二層レジスト膜付の°シリコン基板を
電子線露光装置に収容し、加速電圧20kV及び露光量
50μC/α2にて電子線を照射して・リーンを描画し
た(第1b図参照;3aは露光域、3bは未露光域)。
Next, the resulting silicon substrate with the two-layer resist film was placed in an electron beam exposure device, and irradiated with an electron beam at an acceleration voltage of 20 kV and an exposure dose of 50 μC/α2 to draw a lean pattern (see Figure 1b). ; 3a is the exposed area, 3b is the unexposed area).

次いで、露光後のシリコン基板をトルエン浴に30秒間
にわたって浸漬することにより現偉し、さらにn−へキ
サンにてリンス処理した。第46図に示されるように、
露光域の上層レゾスト膜3aのみが上層レジストパター
ンとして下層レゾスト膜2上に残留した。
Next, the exposed silicon substrate was exposed by immersing it in a toluene bath for 30 seconds, and was further rinsed with n-hexane. As shown in Figure 46,
Only the upper resist film 3a in the exposed area remained on the lower resist film 2 as an upper resist pattern.

次いで、現像後のシリコン基板を平行平板型ドライエツ
チング装置に収容し、残留せる上層レジスト膜3aをマ
スクとしてかつカーデンターr。
Next, the developed silicon substrate is placed in a parallel plate type dry etching device, and etched using a cardenter r using the remaining upper resist film 3a as a mask.

トな用いて、酸素プラズマ(、fス圧力15m’l’o
rr。
Using a high pressure oxygen plasma (15 mL,
rr.

印加電圧0.33 w、、’cm2)にて18分間のプ
ラズマエツチングを行なった。このエツチングの結果、
第1d図に示されるように、上層レジストパターン3a
がそのまま下層レジスト膜2&に転写された。
Plasma etching was performed for 18 minutes at an applied voltage of 0.33 W, cm2). As a result of this etching,
As shown in FIG. 1d, upper resist pattern 3a
was directly transferred to the lower resist film 2&.

本例の場合、感度は2μC/cm であシ、0.4μm
のライン&スペースt!ターンが解像された。
In this example, the sensitivity is 2 μC/cm and 0.4 μm.
Line & Space T! Turn resolved.

前記例1に記載のものと同様な手法に従い本例を実施し
た。但し、本例では、次のようにして二層レジストa付
のシリコン基板を製作した:クロロメチル化ポリスチレ
ン(Mw=50000)をトルエンに溶解して得た溶液
をシリコン基板上にスピンコートシ、そしてトルエンを
除去するために80℃で20分間にわたってベークした
。膜厚2.Ottmの下層レジスト膜が得られた。次い
で、末端ヒドロ命シル基を有するポリメチルシルセスキ
オキサンCM、=300000)をイソプロピルアルコ
ールに溶解して得た溶液を先に形成した下層レジスト膜
上にスピンコードシ、そしてイソプロピルアルコールを
除去するために60℃で20分間にわたってベークした
。膜厚0.1μmの上層レジスト膜が得られた。
This example was carried out following a procedure similar to that described in Example 1 above. However, in this example, a silicon substrate with a two-layer resist a was manufactured as follows: A solution obtained by dissolving chloromethylated polystyrene (Mw = 50,000) in toluene was spin-coated onto the silicon substrate. It was then baked at 80° C. for 20 minutes to remove toluene. Film thickness 2. A lower resist film of Ottm was obtained. Next, a solution obtained by dissolving polymethylsilsesquioxane (CM, = 300,000) having a terminal hydrosilyl group in isopropyl alcohol is applied to the previously formed lower resist film by spinning, and the isopropyl alcohol is removed. The mixture was baked at 60° C. for 20 minutes. An upper resist film with a film thickness of 0.1 μm was obtained.

さらに、本例では、前記例1の現像液であるトルエンに
代えてイングロビルアルコー#ヲ、’j’c、リンス液
であるn−ヘキサンに代えて脱イオン水を、それぞれ使
用した。
Further, in this example, Inglobil alcohol #1 and 'j'c were used in place of toluene as the developing solution in Example 1, and deionized water was used in place of n-hexane as the rinsing solution.

本例の場合、感度は5μC/cIn2であり、0.5μ
mのライン&スペース/4’ターンが解像された。
In this example, the sensitivity is 5μC/cIn2 and 0.5μC/cIn2.
m lines and spaces/4' turns were resolved.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、二層構造のレジスト膜の使用に由来し
て高められた感度、解像性、そして耐ドライエツチ性を
得ることができるばかりでなく、下層レジスト膜のベー
ク(熱硬化)を省略するかもしくは短縮することができ
るので、このパターン形成方法をよシ生産性の高いもの
にすることができる。
According to the present invention, it is possible not only to obtain improved sensitivity, resolution, and dry etch resistance due to the use of a two-layer resist film, but also to avoid baking (thermal curing) of the lower resist film. Since it can be omitted or shortened, this pattern forming method can be made highly productive.

【図面の簡単な説明】[Brief explanation of the drawing]

第1a図、第1b図、第1c図及び第1d図は、それぞ
れ、本発明方法の一例を順を追って示した略示断面図で
ある。 図中、1はシリコン基板、2は下層レジスト膜、そして
3は上層レジスト膜である。
FIGS. 1a, 1b, 1c and 1d are schematic sectional views sequentially showing an example of the method of the present invention. In the figure, 1 is a silicon substrate, 2 is a lower resist film, and 3 is an upper resist film.

Claims (1)

【特許請求の範囲】 1、二層構造のレジスト膜を選択的にエッチングしてレ
ジスト・パターンを形成する方法であって、被加工部材
の表面に、上層レジストパターンの形成に用いられる現
像液に不溶であるけれどもプラズマ処理によりエッチン
グされ得る珪素不含レジスト材料からなる下層レジスト
厚膜、そして耐プラズマエッチ性を有する感電離放射線
含珪素レジスト材料からなる上層レジスト薄膜を順次形
成し、 電離放射線の像パターンを照射して前記上層レジスト薄
膜に前記像パターンに対応する潜像を形成させ、 前記潜像を現像液で現像して上層レジストパターンを得
、 前記上層レジストパターンをマスクとしてプラズマ処理
を行ない、前記上層レジストパターンをその下方の下層
レジスト薄膜に転写すること、を特徴とするパターン形
成方法。 2、現像により得た上層レジストパターンをプラズマ処
理工程に先がけてリンスする、特許請求の範囲第1項に
記載のパターン形成方法。
[Claims] 1. A method for forming a resist pattern by selectively etching a resist film having a two-layer structure, wherein a developing solution used for forming an upper resist pattern is applied to the surface of a workpiece. A lower resist thick film made of a silicon-free resist material that is insoluble but can be etched by plasma processing, and an upper resist thin film made of a silicon-containing resist material that has plasma etch resistance and contains ionizing radiation are sequentially formed, and an ionizing radiation image is formed. irradiating the pattern to form a latent image corresponding to the image pattern on the upper resist thin film, developing the latent image with a developer to obtain an upper resist pattern, and performing plasma treatment using the upper resist pattern as a mask; A pattern forming method comprising transferring the upper resist pattern onto a lower resist thin film below the upper resist pattern. 2. The pattern forming method according to claim 1, wherein the upper resist pattern obtained by development is rinsed prior to the plasma treatment step.
JP59242364A 1984-11-19 1984-11-19 Pattern forming method Pending JPS61121332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59242364A JPS61121332A (en) 1984-11-19 1984-11-19 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59242364A JPS61121332A (en) 1984-11-19 1984-11-19 Pattern forming method

Publications (1)

Publication Number Publication Date
JPS61121332A true JPS61121332A (en) 1986-06-09

Family

ID=17088079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59242364A Pending JPS61121332A (en) 1984-11-19 1984-11-19 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS61121332A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210302839A1 (en) * 2020-03-30 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210302839A1 (en) * 2020-03-30 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device

Similar Documents

Publication Publication Date Title
JPS6323657B2 (en)
JPH0210362A (en) Fine pattern forming method
JPH0722156B2 (en) Method for forming pattern of semiconductor device
JPS61121332A (en) Pattern forming method
JPH04176123A (en) Manufacture of semiconductor device
WO1983003485A1 (en) Electron beam-optical hybrid lithographic resist process
JPH02156244A (en) Pattern forming method
JP2692059B2 (en) Method for forming electron beam resist pattern
JPS59141228A (en) Formation of fine pattern
JPS58132927A (en) Formation of pattern
JPS61260242A (en) Formation of resist pattern
JPS646448B2 (en)
JPH0313949A (en) Resist pattern forming method
JPS6152567B2 (en)
JPS6047419A (en) Multilayer level patterning method
JPH0199041A (en) Fine pattern forming method
JPH0513325A (en) Pattern formation method
JPH01304457A (en) Pattern forming method
JPH04250624A (en) Pattern formation
JPS6054775B2 (en) Dry development method
JPH01244447A (en) Pattern forming method and resist material used therefor
JPS60106132A (en) Formation of pattern
JPS61294821A (en) Method for forming fine pattern
JPS62284356A (en) Formation of resist pattern
JPH05291130A (en) Multilayer resist method and manufacture of semiconductor device