JPS6126221A - Manufacture of semiconductor device or the like - Google Patents

Abstract

PURPOSE:To enable a minute process in a multilayer resist process by providing a thin film having a flat surface by spreading a resist whose thickness is thinner than a level difference over an uneven surface followed by exposure, development and softening of the residual resist in the recess at a high temperature. CONSTITUTION:A positive type lower layer resist 20 is spread over a substrate 4 and a film thickness (t) is determined to be thinner than a difference T of projection parts 2 and 3. Exposure and development are done by using a mask 22 to leave a resist 24 in the part except the projection parts 2 and 3. By a treatment at a high temperature, the resist is softened to fill the part except the projection parts flatly. Then the substrate is covered with a negative resist 28 having good dry etching properties. By exposure and development using a mask 30, a resist pattern 32 is formed. Subsequently, a thin resist pattern 26 is removed completely by an RIE method using O2. By this constitution, because a film thickness of a lower layer resist is thin, a minute process becomes possible and if an RIE method is used for etching, it can be done in a short time and mass production is also possible.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a photolithography process for manufacturing ICs such as LSIs and photomasks.

(Prior Art) A multilayer resist process using a two-layer resist or a three-layer resist is used to form a fine pattern on an uneven surface.

In the two-layer resist process, for example, as shown in FIG.
The lower resist 6 is applied thicker than the step T formed by the convex portions 2 and 3, and is flattened so that the step T can be ignored, and then a different type of upper resist 8 is applied thinly onto the lower resist 6. After exposing and developing the upper resist 8, the lower resist 6 is exposed all at once using the upper resist pattern as a mask, and the base 4 is etched using the resulting pattern as a mask.

In the three-layer resist process, as shown in Figure 3,
An inorganic intermediate layer 10 is interposed between the lower resist 6 and the upper resist 8, and the intermediate layer 10 is etched using the pattern of the upper resist 8 as a mask.
The lower resist 6 is etched using the 0 pattern as a mask, and the base 4 is etched using the obtained pattern as a mask.

However, in such a multilayer resist process, the film thickness of the lower resist 6 must absorb the step T on the underlying surface, so the step T also needs to be thick. This step T is usually 1 μm or more in a semiconductor device, and as much as 2 μm in an EFROM using a two-layer polysilicon layer. Considering that it is generally difficult to create submicron patterns in photolithography unless the resist film thickness is 1 μm or less, it is difficult to create submicron patterns in photolithography.
It can be said that the conventional multilayer resist process shown in the figure still has problems with microfabrication.

Furthermore, when attempting to etch the lower resist 6 using, for example, RIE (reactive ion etching), there is a problem in that the lower resist 6 is thick in the conventional multilayer resist process, and etching takes time, making mass production difficult. .

(Purpose) An object of the present invention is to provide a method for manufacturing semiconductor devices, etc., which enables microfabrication and mass production by reducing the thickness of the lower resist layer in a multilayer resist process. .

(Structure) According to the method of the present invention, in the multilayer resist process, a resist having a film thickness equal to or less than the step difference between the concave and convex portions is applied to a surface having concavities and convexities, and exposure and development are performed so that the resist remains in the concave portions. rear.

It includes a process of softening the remaining resist pattern at high temperature to flatten the surface.

When the method of the present invention is applied to a two-layer resist process, a positive resist and a negative resist are combined, one as a lower layer and the other as an upper layer. At that time, after the lower layer resist is flattened by the method described above, the upper layer resist is formed thereon.

In addition, when applying the method of the present invention to a three-layer resist process, after the lower resist layer is flattened by the above method, an intermediate layer is formed on the lower resist layer, and an upper resist layer is further formed on the intermediate layer. I'll do what I do.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 shows one embodiment, and FIG. 1A shows a substrate 4 having patterned convex portions 2 and 3 on its surface, such as a silicon substrate for LSI on which a diffusion layer is formed and covered with an insulating layer. This shows a state in which a positive resist 20 is applied as a lower layer resist. In this case, the film thickness t of the positive resist 2o is set to be thinner than the step T formed by the convex portion 2.3.

The positive resist 2o is exposed using a mask 22 and developed to form a resist pattern 24 in which the positive resist remains in areas excluding the convex portions 2 and 3 (see (B) in the same figure).
), (C)). At this time, in order to prevent any positive resist from remaining on the convex portions 2 and 3, the light transmission pattern of the mask 22 is set to be larger than the pattern of the convex portions 2.3 by an amount corresponding to the alignment error.

Next, baking is performed at a high temperature to soften the positive resist to form a resist pattern 26, and fill the area except for the convex portions 2.3 flatly (FIG. 2(D)).

The baking conditions at this time vary somewhat depending on the type of resist, but for example, in the case of 0FPR-800 type (manufactured by Tokyo Ohka Co., Ltd.), the convection baking method is used to
Expulsion is carried out for approximately 0 minutes.

A negative type resist 28 having good dry etching resistance is applied thereon as an upper layer resist (FIG. 3(E)).

The negative resist 28 is exposed using the mask 30 (FIG. 2(F)) and developed to form a negative resist pattern 3 on the upper layer.
2 ((G) in the same figure). At this time, since the lower layer positive resist pattern 26 has become insoluble in the developer of the negative resist 28 due to high temperature baking, it remains even after the upper layer negative resist pattern 32 is formed.

Using the obtained upper layer negative resist pattern 32 as a protective film, the lower layer positive resist pattern 26 is etched by a complete RIE method using oxygen gas ((H) in the same figure).
. Since the film thickness of the lower layer positive type resist pattern 26 is thin, complete RIE etching is possible.

Using the two-layer resist pattern thus obtained as a mask, the base 4 is completely etched by RIE.

For example, contact holes can be formed by etching.

Although the above embodiment is a case in which the lower layer resist is a positive type and the upper layer resist is a negative type, the lower layer resist can be a negative type and the upper layer resist can be a positive type.

In that case, the exposure mask used has a light transmitting portion and a light shielding portion opposite to those of the above embodiment.

Furthermore, a three-layer resist structure can be obtained by interposing an intermediate layer between the lower resist layer and the upper resist layer.

(Effects) According to the present invention, in a multilayer resist process, the film thickness of the lower resist layer becomes thinner, so microfabrication becomes possible, and when the lower resist layer is etched by the RIE method, it can be performed in a short time. There is an effect that can be done.

[Brief explanation of the drawing]

FIGS. 1A to 1H are cross-sectional views showing a process according to an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views showing a conventional multilayer resist process, respectively. 2.3...Protrusions on the surface, 20...
Lower layer resist, 26... Flattened lower layer resist pattern, 28... Upper layer resist, T.
...Step, t... Film thickness of lower resist layer.

Claims (1)

[Claims] (1) A resist with a film thickness equal to or less than the level difference between the irregularities is applied to a surface with irregularities, and after exposure and development are performed so that the resist remains in the recesses, the remaining resist pattern is softened at high temperature and the resist is removed. A method of manufacturing a semiconductor device, etc., characterized by including a process of flattening a pattern surface.