JPS6126221A - Manufacture of semiconductor device or the like - Google Patents

Manufacture of semiconductor device or the like

Info

Publication number
JPS6126221A
JPS6126221A JP14624684A JP14624684A JPS6126221A JP S6126221 A JPS6126221 A JP S6126221A JP 14624684 A JP14624684 A JP 14624684A JP 14624684 A JP14624684 A JP 14624684A JP S6126221 A JPS6126221 A JP S6126221A
Authority
JP
Japan
Prior art keywords
resist
exposure
development
projection parts
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14624684A
Inventor
Sonoko Shimomichi
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP14624684A priority Critical patent/JPS6126221A/en
Publication of JPS6126221A publication Critical patent/JPS6126221A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To enable a minute process in a multilayer resist process by providing a thin film having a flat surface by spreading a resist whose thickness is thinner than a level difference over an uneven surface followed by exposure, development and softening of the residual resist in the recess at a high temperature.
CONSTITUTION: A positive type lower layer resist 20 is spread over a substrate 4 and a film thickness (t) is determined to be thinner than a difference T of projection parts 2 and 3. Exposure and development are done by using a mask 22 to leave a resist 24 in the part except the projection parts 2 and 3. By a treatment at a high temperature, the resist is softened to fill the part except the projection parts flatly. Then the substrate is covered with a negative resist 28 having good dry etching properties. By exposure and development using a mask 30, a resist pattern 32 is formed. Subsequently, a thin resist pattern 26 is removed completely by an RIE method using O2. By this constitution, because a film thickness of a lower layer resist is thin, a minute process becomes possible and if an RIE method is used for etching, it can be done in a short time and mass production is also possible.
COPYRIGHT: (C)1986,JPO&Japio
JP14624684A 1984-07-14 1984-07-14 Manufacture of semiconductor device or the like Pending JPS6126221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14624684A JPS6126221A (en) 1984-07-14 1984-07-14 Manufacture of semiconductor device or the like

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14624684A JPS6126221A (en) 1984-07-14 1984-07-14 Manufacture of semiconductor device or the like

Publications (1)

Publication Number Publication Date
JPS6126221A true JPS6126221A (en) 1986-02-05

Family

ID=15403393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14624684A Pending JPS6126221A (en) 1984-07-14 1984-07-14 Manufacture of semiconductor device or the like

Country Status (1)

Country Link
JP (1) JPS6126221A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0269755A (en) * 1988-07-28 1990-03-08 Korea Electron Telecommun Formation of fine line width utilizing spacer
JP2005156576A (en) * 2003-09-16 2005-06-16 Macronix Internatl Co Ltd Method for relaxing alignment accuracy condition in manufacturing of integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0269755A (en) * 1988-07-28 1990-03-08 Korea Electron Telecommun Formation of fine line width utilizing spacer
JPH0579980B2 (en) * 1988-07-28 1993-11-05 Korea Electronics Telecomm
JP2005156576A (en) * 2003-09-16 2005-06-16 Macronix Internatl Co Ltd Method for relaxing alignment accuracy condition in manufacturing of integrated circuit

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