JPH0582438A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0582438A
JPH0582438A JP23853291A JP23853291A JPH0582438A JP H0582438 A JPH0582438 A JP H0582438A JP 23853291 A JP23853291 A JP 23853291A JP 23853291 A JP23853291 A JP 23853291A JP H0582438 A JPH0582438 A JP H0582438A
Authority
JP
Japan
Prior art keywords
film
resist
layer
resist film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23853291A
Other languages
Japanese (ja)
Inventor
Tatsuro Tezuka
達朗 手塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23853291A priority Critical patent/JPH0582438A/en
Publication of JPH0582438A publication Critical patent/JPH0582438A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To suppress the intensity variation of light caused by the interference between reflected light from the surface of a semiconductor substrate and incident light by providing a film composed of a material containing a dye below the uppermost resist film in a three-layer resist forming process. CONSTITUTION:After an aluminum film 2 having a film thickness of 1mum is formed on an interlayer insulating film 6 on a semiconductor substrate 1 having projections of lower-layer wiring 10, a resist film containing a dye at a high concentration of >=1% is formed to a film thickness of 2mum on the film 2 as a first-layer film 3 and the resist of the film 3 is changed in quality by UV curing so that the film 3 can withstand heat treatment of about 200-300 deg.C. Then an SOG film is formed on the film 3 to a film thickness of 2,000Angstrom as a second coating layer 4 and, on the film 4, a resist film 5 is formed to a film thickness of 0.8mum. Thereafter, the resist film 5 is patterned and the aluminum film is etched. Therefore, the reflected light from the surface of the semiconductor surface 1 can be reduced and the influence of the reflected light at the interface between the lower resist film and SOG film can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
かかり特に三層レジストプロセスに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a three-layer resist process.

【0002】[0002]

【従来の技術】従来の半導体装置の製造方法を図2に示
す。下層配線10上に層間膜6を形成し、その上にアル
ミ膜2を形成した半導体基板1上に、下層レジスト膜7
を形成し、ハードベーク、UVキュア等の方法でその上
層のスピンオングラスSOG膜8形成時にかかる熱に耐
えられる様にかためる。次にSOG膜8を形成し、その
上に上層レジスト膜9を形成し、フォトリソグラフィー
技術を用いて上層レジスト膜9を所望のパターンにパタ
ーニングした後、上層レジスト膜9をマスクにSOG膜
8を反応性イオンエッチング法を用いてエッチングする
(図2の(A))。次に上層レジスト膜9を除去した
後、SOG膜8をマスクに下層レジスト膜7を反応性イ
オンエッチング法を用いてエッチングする(図2の
(B))。次にSOG膜を除去した後、下層レジスト膜
7をマスクにアルミ膜2をエッチング(図2の(C))
し、その後下層レジスト膜7を除去する(図2の
(D))。
2. Description of the Related Art A conventional method of manufacturing a semiconductor device is shown in FIG. The lower layer resist film 7 is formed on the semiconductor substrate 1 in which the interlayer film 6 is formed on the lower layer wiring 10 and the aluminum film 2 is formed thereon.
Then, it is hardened by a method such as hard baking and UV curing so that it can withstand the heat applied when the upper layer spin-on-glass SOG film 8 is formed. Next, an SOG film 8 is formed, an upper resist film 9 is formed thereon, and the upper resist film 9 is patterned into a desired pattern by using a photolithography technique. Then, the SOG film 8 is formed using the upper resist film 9 as a mask. Etching is performed using the reactive ion etching method (FIG. 2A). Next, after removing the upper resist film 9, the lower resist film 7 is etched using the SOG film 8 as a mask by the reactive ion etching method ((B) of FIG. 2). Next, after removing the SOG film, the aluminum film 2 is etched using the lower resist film 7 as a mask ((C) of FIG. 2).
After that, the lower resist film 7 is removed ((D) of FIG. 2).

【0003】[0003]

【発明が解決しようとする課題】従来の半導体装置の製
造方法は、下層レジスト膜により平坦化されているた
め、上層レジスト膜の膜厚差は小さいが、下層レジスト
膜の光吸収率が低いため半導体基板表面からの反射光と
入射光の干渉により光強度が変動するという問題があっ
た。
In the conventional method for manufacturing a semiconductor device, since the upper resist film is flattened by the lower resist film, the film thickness difference of the upper resist film is small, but the light absorption of the lower resist film is low. There is a problem that the light intensity fluctuates due to the interference between the reflected light from the semiconductor substrate surface and the incident light.

【0004】[0004]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、段差の有る半導体基板表面に染料入り塗布膜
を形成し、その上部にレジスト膜を形成する工程を有す
る。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a coating film containing a dye on a surface of a semiconductor substrate having a step and forming a resist film on the coating film.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の第1の実施例の工程の縦断面図であ
る。従来例と同様に下層配線10の段差が有る半導体基
板1の表面1μmの厚さのにアルミ膜2を層間絶縁膜6
上に形成した後、染料を1%以上の高濃度に含むレジス
ト膜を第1層膜3として、2μmの厚さで形成し、UV
キュアにより200〜300℃程度の熱処理に耐えられ
る様に変質させた後、SOG膜を第2層塗布膜4として
2000オングストロームの厚さで形成する。次にレジ
スト膜5を0.8μmの厚さで形成する(図1)。次に
図2に示すような公知のレジストパターニングを行いア
ルミ膜のエッチングを行なう。
The present invention will be described below with reference to the drawings. FIG. 1 is a vertical cross-sectional view of the process of the first embodiment of the present invention. Similar to the conventional example, the aluminum film 2 and the interlayer insulating film 6 are formed in a thickness of 1 μm on the surface of the semiconductor substrate 1 having the step of the lower layer wiring 10.
After the above formation, a resist film containing a dye in a high concentration of 1% or more is formed as the first layer film 3 to a thickness of 2 μm, and UV is formed.
After being modified by curing to withstand a heat treatment at about 200 to 300 ° C., an SOG film is formed as a second layer coating film 4 with a thickness of 2000 Å. Next, a resist film 5 is formed with a thickness of 0.8 μm (FIG. 1). Next, known resist patterning as shown in FIG. 2 is performed to etch the aluminum film.

【0006】次に本発明の第2の実施例について説明を
行なう。第1の実施例と同様に高濃度に染料を含んだレ
ジスト膜を形成し、UVキュアを用いて固めた後1%以
上の染料入りのSOG膜を第2層塗布膜4として形成す
る。その後、従来例と同様にレジストのパターニングを
行ないエッチングを行なう。本実施例はSOG膜にも染
料が入っているため、半導体基板表面からの反射光がよ
り弱められ又、下部レジスト膜とSOG膜の界面での反
射光の影響も防ぐことが出来る。
Next, a second embodiment of the present invention will be described. Similar to the first embodiment, a resist film containing a high concentration of dye is formed, and after being cured by UV curing, an SOG film containing 1% or more of dye is formed as a second layer coating film 4. After that, the resist is patterned and etching is performed as in the conventional example. In this embodiment, since the SOG film also contains the dye, the reflected light from the surface of the semiconductor substrate is further weakened, and the influence of the reflected light at the interface between the lower resist film and the SOG film can be prevented.

【0007】[0007]

【発明の効果】以上説明した様に本発明は、3層レジス
トプロセスにおいて高濃度に染料を含んだ塗布膜を用い
て半導体基板表面の平坦化を行なうことにより半導体基
板表面からの反射光と入射光の干渉による光強度の変動
をおさえられるという効果を有する。
As described above, according to the present invention, in the three-layer resist process, the light reflected from the semiconductor substrate surface and the incident light are incident by flattening the semiconductor substrate surface by using the coating film containing the dye in high concentration. This has the effect of suppressing fluctuations in light intensity due to light interference.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す縦断面図。FIG. 1 is a vertical sectional view showing an embodiment of the present invention.

【図2】従来の3層レジストプロセスフローを示す縦断
面図である。
FIG. 2 is a vertical sectional view showing a conventional three-layer resist process flow.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 アルミ膜 3 第1層塗布膜 4 第2層塗布膜 5 レジスト膜 6 層間膜 7 下層レジスト膜 8 SOG膜 9 上層レジスト膜 10 下層配線 1 Semiconductor Substrate 2 Aluminum Film 3 First Layer Coating Film 4 Second Layer Coating Film 5 Resist Film 6 Interlayer Film 7 Lower Layer Resist Film 8 SOG Film 9 Upper Layer Resist Film 10 Lower Layer Wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 三層レジストプロセスにおいて、最上層
のレジスト膜の下層に染料入り材料によって形成される
膜を設けることを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, wherein in a three-layer resist process, a film formed of a dye-containing material is provided below a top resist film.
JP23853291A 1991-09-19 1991-09-19 Manufacture of semiconductor device Pending JPH0582438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23853291A JPH0582438A (en) 1991-09-19 1991-09-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23853291A JPH0582438A (en) 1991-09-19 1991-09-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0582438A true JPH0582438A (en) 1993-04-02

Family

ID=17031653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23853291A Pending JPH0582438A (en) 1991-09-19 1991-09-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0582438A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5632721A (en) * 1994-07-29 1997-05-27 Kuan; Yo Mo Massage apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5632721A (en) * 1994-07-29 1997-05-27 Kuan; Yo Mo Massage apparatus

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