JPH0350828A - Method of forming gold wiring - Google Patents
Method of forming gold wiringInfo
- Publication number
- JPH0350828A JPH0350828A JP18775589A JP18775589A JPH0350828A JP H0350828 A JPH0350828 A JP H0350828A JP 18775589 A JP18775589 A JP 18775589A JP 18775589 A JP18775589 A JP 18775589A JP H0350828 A JPH0350828 A JP H0350828A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- etching
- mask
- tungsten
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 239000010931 gold Substances 0.000 title claims abstract description 32
- 229910052737 gold Inorganic materials 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000992 sputter etching Methods 0.000 claims abstract description 12
- 238000001020 plasma etching Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 11
- 229910052721 tungsten Inorganic materials 0.000 abstract description 11
- 239000010937 tungsten Substances 0.000 abstract description 11
- 239000000463 material Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241000416536 Euproctis pseudoconspersa Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に金を用い
た微細配線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming fine interconnections using gold.
ご従来の技術〕
近年における半導体装置の高集積化にともなって、基板
上に形成される配線構造の信頼性がますます重要となっ
てきている。このため高信頼性が要求される用途には、
配線材料として金が用いられる。金の微細配線は、第3
図(a)〜(c)に示すような方法で形成される。以下
工程順に説明する。Background Art] With the recent increase in the degree of integration of semiconductor devices, the reliability of wiring structures formed on substrates has become increasingly important. Therefore, for applications that require high reliability,
Gold is used as the wiring material. The fine gold wiring is the third
It is formed by the method shown in Figures (a) to (c). The steps will be explained below in order.
第3図(a)のように絶縁膜3上に形成した金2にフォ
トレジスト1を1μ程度の厚さに塗布して配線パターン
を形成する。次いで、同図(b)のようにイオンミリン
グ装置を用いてフォトレジスト1をマスクに金2をアル
ゴンによりスパッタエツチングする。最後に同図(C)
のようにフォトレジスト1aを剥離し金配線を形成して
いた。As shown in FIG. 3(a), a photoresist 1 is applied to a thickness of about 1 μm on the gold 2 formed on the insulating film 3 to form a wiring pattern. Next, as shown in FIG. 2B, gold 2 is sputter-etched using argon using the photoresist 1 as a mask using an ion milling apparatus. Finally, the same figure (C)
The photoresist 1a was peeled off to form gold wiring as shown in FIG.
上述した従来の製造方法では、イオンミリング装置での
スパッタエツチングの際に第3図(b)の2bのように
金がフォトレジストのパターン1a側面に再付着し、フ
ォトレジス)laの剥離の際に再付着した金がはがれ、
同図(c)に示すように隣り合った配線と配線を短絡し
半導体装置の信頼性を著しく低下させるという問題があ
る。In the conventional manufacturing method described above, during sputter etching using an ion milling device, gold re-adheres to the side surface of the photoresist pattern 1a as shown in 2b in FIG. The gold that was reattached to the
As shown in FIG. 4(c), there is a problem in that adjacent wirings are short-circuited, significantly reducing the reliability of the semiconductor device.
本発明の金配線の形成方法は、絶縁膜上に金を形成する
工程と、金属膜を形成する工程と、レジストパターンに
より配線パターンを形成する工程と、反応性イオンエツ
チングにより、金属膜をエツチングする工程と、レジス
トを剥離した後、金属膜をマスクにイオンミリングで金
ヲエッチングする工程を有している。The method for forming gold wiring according to the present invention includes a step of forming gold on an insulating film, a step of forming a metal film, a step of forming a wiring pattern using a resist pattern, and a step of etching the metal film by reactive ion etching. and a step of etching the gold by ion milling using the metal film as a mask after removing the resist.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の一実施例を説明するた
めに工程順に示した断面図である。FIGS. 1(a) to 1(d) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention.
まず第1図(a)に示すように絶縁膜3上に金2を0.
5μ形成し、次いでタングステン4を0.15μ形成シ
、フォトレジス)1により配線パターンを形成する。次
いで同図(b)で示すようにCF、ガスを用いた反応性
イオンミリングでタングステンを8分間エツチングし、
同図(C)のごとくフォトレジスト1aを除去してタン
グステンマスク4aを形成する。しかる後、同図(d)
に示すようにイオンミリング装置により、ビームエネル
ギー500eV、ビーム電流1 m A / cfのエ
ツチング条件で金をエツチングする。この場合、エツチ
ング速度は、金が1400人/min 、タングステン
が340人/minであるのでエツチング時間は4分が
最適である。First, as shown in FIG. 1(a), gold 2 is deposited on the insulating film 3 at 0.000.
After that, tungsten (4) is formed to have a thickness of 0.15μ, and a wiring pattern is formed using photoresist (1). Next, as shown in the same figure (b), the tungsten was etched for 8 minutes by reactive ion milling using CF gas.
As shown in FIG. 2C, the photoresist 1a is removed to form a tungsten mask 4a. After that, the same figure (d)
As shown in Figure 2, gold is etched using an ion milling device under etching conditions of beam energy of 500 eV and beam current of 1 mA/cf. In this case, since the etching speed is 1400 etching/min for gold and 340 etching/min for tungsten, the optimum etching time is 4 minutes.
このようにして形成される金配線は厚さ1μ程度のフォ
トレジストをマスクとして使った場合、問題となったレ
ジスト剥離後の再付着した金のはがれが生じない。すな
わち、マスク材として、淳さ0.15μの薄いタングス
テン膜を使用しているため、金のマスク材への再付着量
は、非常に少ない。また、マスク材として使用したタン
グステンは、金属であるため、そのまま配線として使用
可能であり、フォトレジストのように除去する必要がな
い。従って、剥離工程が不要であるため、再付着した金
がはがれることはない。When a photoresist with a thickness of about 1 μm is used as a mask for the gold wiring formed in this manner, the problem of peeling off of redeposited gold after the resist is removed does not occur. That is, since a thin tungsten film with a thickness of 0.15 μm is used as the mask material, the amount of gold redeposited onto the mask material is extremely small. Furthermore, since the tungsten used as the mask material is a metal, it can be used as is as a wiring and does not need to be removed unlike photoresist. Therefore, since there is no need for a stripping process, redeposited gold will not be peeled off.
第2図(a)〜(e)は、本発明の他の実施例の縦断面
である。本実施例では、絶縁膜3上にチタン15を成長
し、更にその上に金を成長している。FIGS. 2(a) to 2(e) are longitudinal sections of other embodiments of the present invention. In this example, titanium 15 is grown on the insulating film 3, and gold is further grown thereon.
また、金のエツチングマスクとしてもチタン14を用い
ている。チタンはイオンミリングでのエツチングレート
は、はぼタングステンと同等である。Titanium 14 is also used as a gold etching mask. The etching rate of titanium in ion milling is about the same as that of tungsten.
本実施例では同図(b)で示す、マスク材のチタン14
のエツチングは、C(14ガスを用いた反応性イオンエ
ツチングで行なう。また同図(e)のチタン15と金2
をマスクにチタンをエツチングする工程もC(14ガス
を用いた反応性イオンエツチングで容易に行なうことが
可能である。In this example, the titanium 14 of the mask material shown in FIG.
The etching is carried out by reactive ion etching using C (14 gas).
The process of etching titanium using a mask can also be easily performed by reactive ion etching using C (14 gas).
その他、反応性イオンエツチングが容易なマスク材とし
ての金属膜は、モリブテン、アルミニウム、クロム、タ
ンタルといったものが挙げられ、これらの材料でも本発
明は実現可能である。Other examples of metal films that can be used as mask materials that can be easily subjected to reactive ion etching include molybdenum, aluminum, chromium, and tantalum, and the present invention can also be implemented using these materials.
以上説明したように、本発明は、金配線のイオンミリン
グの際にマスク材をレジストから、反応性イオンエツチ
ングが可能な、金属膜に置き換えることにより、レジス
トへの金の再付着が防止でき、配線間の短絡を未然に防
止することができ、金配線の信頼性を向上させることが
可能となる。As explained above, the present invention can prevent gold from re-adhering to the resist by replacing the mask material from the resist with a metal film that can be subjected to reactive ion etching during ion milling of gold wiring. Short circuits between wires can be prevented, and the reliability of gold wires can be improved.
第1図(a)〜(d)は本発明の一実施例を示す工程断
面図、第2図(a)〜(e)は本発明の他の実施例の工
程断面図、第3図(a)〜(c)は従来の方法を示す工
程断面図である。
1.1a・・・・・・フォトレジスト、2.2a、2b
・・・・・・金、3・・・・・・絶縁膜、4.4a、4
b・・・・・・タングステン、l 4. 14 a、
14 b−チタン、15゜15a・・・・・・チタン
。1(a) to (d) are process cross-sectional views showing one embodiment of the present invention, FIGS. 2(a) to (e) are process cross-sectional views of another embodiment of the present invention, and FIG. a) to (c) are process cross-sectional views showing a conventional method. 1.1a...Photoresist, 2.2a, 2b
...Gold, 3...Insulating film, 4.4a, 4
b...Tungsten, l 4. 14a,
14 b-titanium, 15° 15a... titanium.
Claims (1)
程と、金属膜を形成する工程と、反応性イオンエッチン
グにより、前記金属膜を選択的にエッチングする工程と
、前記金属膜をマスクにイオンミリングで前記金をエッ
チングする工程とを含むことを特徴とする金配線の形成
方法A method for forming a gold wiring includes a step of forming gold on an insulating film, a step of forming a metal film, a step of selectively etching the metal film by reactive ion etching, and a step of using the metal film as a mask. A method for forming a gold wiring, comprising a step of etching the gold by ion milling.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18775589A JPH0350828A (en) | 1989-07-19 | 1989-07-19 | Method of forming gold wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18775589A JPH0350828A (en) | 1989-07-19 | 1989-07-19 | Method of forming gold wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0350828A true JPH0350828A (en) | 1991-03-05 |
Family
ID=16211637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18775589A Pending JPH0350828A (en) | 1989-07-19 | 1989-07-19 | Method of forming gold wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0350828A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010199182A (en) * | 2009-02-24 | 2010-09-09 | Nippon Telegr & Teleph Corp <Ntt> | Method of manufacturing semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5493970A (en) * | 1978-01-07 | 1979-07-25 | Toshiba Corp | Patttern forming method of multi-layer metallic thin film |
JPS6436024A (en) * | 1987-07-31 | 1989-02-07 | Nec Corp | Formation of wiring of semiconductor device |
JPS6474727A (en) * | 1987-09-17 | 1989-03-20 | Dainippon Printing Co Ltd | Dry etching method |
-
1989
- 1989-07-19 JP JP18775589A patent/JPH0350828A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5493970A (en) * | 1978-01-07 | 1979-07-25 | Toshiba Corp | Patttern forming method of multi-layer metallic thin film |
JPS6436024A (en) * | 1987-07-31 | 1989-02-07 | Nec Corp | Formation of wiring of semiconductor device |
JPS6474727A (en) * | 1987-09-17 | 1989-03-20 | Dainippon Printing Co Ltd | Dry etching method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010199182A (en) * | 2009-02-24 | 2010-09-09 | Nippon Telegr & Teleph Corp <Ntt> | Method of manufacturing semiconductor device |
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