JPS63173331A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63173331A JPS63173331A JP668687A JP668687A JPS63173331A JP S63173331 A JPS63173331 A JP S63173331A JP 668687 A JP668687 A JP 668687A JP 668687 A JP668687 A JP 668687A JP S63173331 A JPS63173331 A JP S63173331A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- etching
- aluminum
- aluminum wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000001020 plasma etching Methods 0.000 claims abstract description 9
- 239000000356 contaminant Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 abstract description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 5
- 238000005260 corrosion Methods 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- -1 Argon ions Chemical class 0.000 abstract description 3
- 239000011261 inert gas Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052786 argon Inorganic materials 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000010884 ion-beam technique Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000001133 acceleration Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 4
- 150000002366 halogen compounds Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
最近の半導体ICの高集積化に伴い、その信頼性要求は
ますます高まり、そのために、製造及び市場での高品質
を保証する金属配線層形成の微細加工技術が重要となっ
てきた。With the recent increase in the degree of integration of semiconductor ICs, their reliability requirements are increasing, and for this reason, microfabrication technology for forming metal wiring layers that guarantees high quality in manufacturing and on the market has become important.
第2図(a)及び(b>は、従来の半導体装置の製造方
法を説明するための工程順に示した半導体チップの断面
図である。FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device.
第2図(a)に示すように、半導体ウェーハ3は、不純
物質を含むシリコンウェーハ1の上にシリコン酸化膜2
を形成した後、前述の不純物層と電気的接続を行うため
の開口部をシリコン酸化膜2に設けている。As shown in FIG. 2(a), the semiconductor wafer 3 has a silicon oxide film 2 on the silicon wafer 1 containing impurity substances.
After forming the silicon oxide film 2, an opening is provided in the silicon oxide film 2 for electrical connection with the impurity layer described above.
次に、半導体ウェーハ3の上にアルミニウム層を堆積し
てから、四塩化炭素などのハロゲン化合物の反応性イオ
ンエツチング法を用いてアルミニウム配線層4を形成し
、続いて有機溶剤を用いてホトレジスト層を剥離する。Next, an aluminum layer is deposited on the semiconductor wafer 3, and then an aluminum wiring layer 4 is formed using a reactive ion etching method using a halogen compound such as carbon tetrachloride, and then a photoresist layer is formed using an organic solvent. Peel off.
次に、第2図(b)に示すように、表面の安定化のため
にシリコン窒化膜5を形成する。Next, as shown in FIG. 2(b), a silicon nitride film 5 is formed to stabilize the surface.
なお、このシリコン窒化膜5は、多層配線の半導体装置
の場合は、眉間絶縁膜にも相当する。Note that this silicon nitride film 5 also corresponds to a glabella insulating film in the case of a semiconductor device with multilayer wiring.
上述した従来の半導体装置の製造方法は、アルミニラム
配線層4を形成する反応性イオンエツチング工程におい
て、ハロゲンやハロゲン化合物が半導体ウェー八3のシ
リコン酸化膜2及びアルミニウム配線層4の表面に付着
し、さらにその後のポトレジス1〜層剥離工程でもハロ
ゲン化合物が十分に除去されず、むしろ剥離用の有機溶
剤中のハロゲン化合物も汚染物質として付着し、残留す
るという問題があった。In the conventional semiconductor device manufacturing method described above, in the reactive ion etching process for forming the aluminum wiring layer 4, halogen or halogen compounds adhere to the surfaces of the silicon oxide film 2 and the aluminum wiring layer 4 of the semiconductor wafer 83. Furthermore, there was a problem in that the halogen compounds were not sufficiently removed in the subsequent Potregis 1 to layer peeling steps, and rather the halogen compounds in the organic solvent for peeling also adhered and remained as contaminants.
特に、最近の半導体ICの金属配線層の設計の微細化が
進むにつれ、その後の熱処理工程および電子回路として
使用中の市場において、この半導体装置内部の汚染物質
が配線金属と反応して金属配線層の腐蝕が進行し、つい
には断線不良などの品質l・ラブル発生の要因となると
いう大きな問題が起ってきた。In particular, as the design of the metal wiring layer of recent semiconductor ICs progresses to miniaturization, contaminants inside the semiconductor device react with the wiring metal during the subsequent heat treatment process and in the market where it is used as an electronic circuit. As the corrosion progresses, a major problem has arisen in that it becomes a factor in quality problems such as disconnection and defects.
本発明の目的は、半導体ウェーハ及び金属配線層の表面
の清浄化を図り、信頼性の高い半導体装置の製造方法を
提供することにある。An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device by cleaning the surfaces of a semiconductor wafer and a metal wiring layer.
本発明の半導体装置の製造方法は、上層の絶縁膜を有す
る半導体ウェーハの上に金属配線層を反応性イオンエツ
チング法を用いて形成する工程と、前記半導体ウェーハ
及び前記金属配線層の表面に付着した汚染物質に希ガス
を使用して非反応性イオンエツチングする工程とを有し
ている。The method for manufacturing a semiconductor device of the present invention includes a step of forming a metal wiring layer on a semiconductor wafer having an upper insulating film using a reactive ion etching method, and adhering to the surface of the semiconductor wafer and the metal wiring layer. The method includes a step of non-reactive ion etching of the contaminated contaminants using a rare gas.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(C)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず、第1図(a)に示すように、半導体ウェー八3お
よびアルミニウム配線層4は、それぞれ第2図(a)の
半導体ウェー八3及びアルミニウム配線層4と同一であ
り、前述の従来の工程で形成される。First, as shown in FIG. 1(a), the semiconductor wafer 3 and the aluminum wiring layer 4 are respectively the same as the semiconductor wafer 3 and the aluminum wiring layer 4 of FIG. Formed during the process.
次に、第1図(b)に示すように、プラズマエツチング
装置を用いてアルゴンイオンを厚さ500nm程度のシ
リコン酸化膜2及び厚さ1μm程度のアルミニウム配線
層4に当てて物理的な等方性スパッタを行い、薄いシリ
コン酸化膜2a及びアルミニウム配線層4aを形成する
。Next, as shown in FIG. 1(b), argon ions are applied to the silicon oxide film 2 with a thickness of about 500 nm and the aluminum interconnection layer 4 with a thickness of about 1 μm using a plasma etching apparatus to achieve physical isotropy. Then, a thin silicon oxide film 2a and an aluminum wiring layer 4a are formed by sputtering.
削除された膜厚の一例として数値を示すと、シリコン酸
化膜2aは5〜1100n、アルミニウム配線層4aは
上面が10〜200nmで側面が5〜1100n程度で
ある。To give numerical values as an example of the removed film thickness, the silicon oxide film 2a has a thickness of 5 to 1100 nm, and the aluminum wiring layer 4a has a top surface of 10 to 200 nm and a side surface of about 5 to 1100 nm.
さらに、第1図(c)に示すように、第2図(b)に説
明した従来と同一工程でシリコン窒化膜5を形成する。Furthermore, as shown in FIG. 1(c), a silicon nitride film 5 is formed in the same process as the conventional process explained in FIG. 2(b).
本発明の半導体装置の製造方法によって製造された半導
体装置を、500℃の温度で30分間の高温加速信頼度
試験の後で、半導体装置内部のアルミニウム配線層4a
の腐蝕状態を従来の方法による半導体装置のアルミニウ
ム配線層4の腐蝕状態と比較したところ、従来はアルミ
ニウム配線層4の総面積に対する腐蝕によるアルミニウ
ムの欠損面積比率が数%であったが、本実施例によれば
欠損面積比率は従来の10分の1以下になった。After the semiconductor device manufactured by the semiconductor device manufacturing method of the present invention was subjected to a high temperature accelerated reliability test at a temperature of 500° C. for 30 minutes, the aluminum wiring layer 4a inside the semiconductor device was tested.
Comparing the corrosion state of the aluminum wiring layer 4 with the corrosion state of the aluminum wiring layer 4 of a semiconductor device according to the conventional method, it was found that in the conventional method, the ratio of aluminum loss area due to corrosion to the total area of the aluminum wiring layer 4 was several percent, but in this method According to the example, the defective area ratio has become less than one-tenth of the conventional ratio.
なお、上述の実施例において、不活性ガスのイオンによ
る等方性のプラズマエツチング装置を用いたが、異方性
エツチングとなる不活性ガスによるイオンビームエツチ
ングでも良い。In the above embodiment, an isotropic plasma etching apparatus using inert gas ions was used, but ion beam etching using an inert gas, which results in anisotropic etching, may also be used.
以上説明したように、本発明によれば、従来の金属配線
層形成のための反応性エツチング工程によって絶縁膜及
び金属配線層表面に付着した汚染物質を物質的に削取る
非反応性イオンによるエツチング工程を従来の金属配線
層形成工程に追加することにより、金属配線層の品質劣
化に起因する半導体装置の信頼性を著しく改善すること
ができる効果がある。As explained above, according to the present invention, etching using non-reactive ions is used to physically remove contaminants attached to the surface of an insulating film and metal wiring layer by the conventional reactive etching process for forming a metal wiring layer. By adding this step to the conventional metal wiring layer forming process, there is an effect that the reliability of the semiconductor device, which is caused by quality deterioration of the metal wiring layer, can be significantly improved.
第1図(a)〜(C)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図(a
>及び(b)は従来の半導体装置の製造方法を説明する
ための工程順に示した半導体チップの断面図である。
1・・・シリコンウェーハ、2,2a・・・シリコン酸
化膜、3.3b・・・半導体装置ウェーハ、4,4a・
・・アルミニウム配線層、5・・・シリコン窒化膜。1(a) to 1(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
> and (b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device. 1... Silicon wafer, 2, 2a... Silicon oxide film, 3.3b... Semiconductor device wafer, 4, 4a...
...Aluminum wiring layer, 5...Silicon nitride film.
Claims (1)
を反応性イオンエッチング法を用いて形成する工程と、
前記半導体ウェーハ及び前記金属配線層の表面に付着し
た汚染物質に希ガスを使用して非反応性イオンエッチン
グする工程とを含むことを特徴とする半導体装置の製造
方法。forming a metal wiring layer on a semiconductor wafer having an upper insulating film using a reactive ion etching method;
A method for manufacturing a semiconductor device, comprising the step of performing non-reactive ion etching on contaminants attached to the surfaces of the semiconductor wafer and the metal wiring layer using a rare gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62006686A JPH0758706B2 (en) | 1987-01-13 | 1987-01-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62006686A JPH0758706B2 (en) | 1987-01-13 | 1987-01-13 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63173331A true JPS63173331A (en) | 1988-07-16 |
JPH0758706B2 JPH0758706B2 (en) | 1995-06-21 |
Family
ID=11645238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62006686A Expired - Fee Related JPH0758706B2 (en) | 1987-01-13 | 1987-01-13 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0758706B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02164036A (en) * | 1988-12-19 | 1990-06-25 | Nec Corp | Formation of aluminum wiring |
JPH02278731A (en) * | 1989-04-19 | 1990-11-15 | Nec Corp | Manufacture of semiconductor device |
EP0602633A3 (en) * | 1992-12-16 | 1997-01-29 | Texas Instruments Inc | Method of clean up of a patterned metal layer. |
US8629688B2 (en) | 2010-09-29 | 2014-01-14 | International Business Machines Corporation | Method for sulfur-based corrosion testing |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5713743A (en) * | 1980-06-30 | 1982-01-23 | Toshiba Corp | Plasma etching apparatus and etching method |
-
1987
- 1987-01-13 JP JP62006686A patent/JPH0758706B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5713743A (en) * | 1980-06-30 | 1982-01-23 | Toshiba Corp | Plasma etching apparatus and etching method |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02164036A (en) * | 1988-12-19 | 1990-06-25 | Nec Corp | Formation of aluminum wiring |
JPH02278731A (en) * | 1989-04-19 | 1990-11-15 | Nec Corp | Manufacture of semiconductor device |
EP0602633A3 (en) * | 1992-12-16 | 1997-01-29 | Texas Instruments Inc | Method of clean up of a patterned metal layer. |
US8629688B2 (en) | 2010-09-29 | 2014-01-14 | International Business Machines Corporation | Method for sulfur-based corrosion testing |
Also Published As
Publication number | Publication date |
---|---|
JPH0758706B2 (en) | 1995-06-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |