CN1610078A - Method for removing stripping of wafer edge - Google Patents
Method for removing stripping of wafer edge Download PDFInfo
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- CN1610078A CN1610078A CN 200310102864 CN200310102864A CN1610078A CN 1610078 A CN1610078 A CN 1610078A CN 200310102864 CN200310102864 CN 200310102864 CN 200310102864 A CN200310102864 A CN 200310102864A CN 1610078 A CN1610078 A CN 1610078A
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Abstract
The present invention is method of eliminating peeled film in the chip edge to form fault. The design of the present invention has one step of clearing the chip edge after forming metal wire layer to eliminate the peeled film in the edge. The eliminated film may contain patterned metal structure. Therefore, the design of the present invention can raise chip quality effectively and reduce pollution to work bench.
Description
(1) technical field
The relevant a kind of semi-conductive processing procedure of the present invention is particularly about a kind of method that prevents that the generation Waffer edge is peeled off behind the plain conductor processing procedure.
(2) background technology
The plain conductor processing procedure is being played the part of considerable role in manufacture of semiconductor.With the copper conductor processing procedure is example, particularly after manufacture of semiconductor enters the deep-sub-micrometer field, the material that is used low-k (low K) with the copper conductor processing procedure is used as the design of intermetallic dielectric layer, can bring into play effectively reducing RC time delay (Resistance Capacitance Time Delay; RC delay) and improve the characteristic of electron transfer (electro-migration).
Fig. 1 is the flow chart of the copper conductor processing procedure in the prior art.With reference to Fig. 1, at first, form a copper conductor layer on a wafer, shown in step 120.Above-mentioned copper conductor layer can be by such as electrochemistry galvanoplastic (electro-chemical plating; ECP) and so on common technology forms.Then, with chemical mechanical milling method (chemical mechanical polishing; CMP), or other technology come the planarization copper conductor layer the surface and remove copper load layer unnecessary on the wafer (overburden layer), shown in step 140.Then, referring to step 160, carry out a wafer and clean and dry step.Next, can enter down processing procedure one, shown in step 180.
In the plain conductor processing procedure, the normal material with reduction ions diffusion effect and so on that uses is used as barrier layer (barrier layer), preventing metal diffusing to other structure, as Ta commonly used in copper plain conductor processing procedure, TaN film material as barrier layer.Yet; because barrier layer is relatively poor for the adhesive ability such as silicon base material; and do not form the zone of metal layer pattern at Waffer edge because of the position; its barrier layer can expose because of the removal of metal level, and piles up with the metal level processing procedure of follow-up repetition, makes also therefore accumulation of stress; so; regular meeting is positioned at Waffer edge in follow-up processing procedure, even the barrier layer of the part that do not covered by metal level of chip back surface peels off together with the structure that is formed at the barrier layer top, and then the generation defective.The phenomenon that above-mentioned barrier layer is peeled off, light then cause the yield of manufacture of semiconductor to reduce, serious meeting causes scrapping of wafer.And the phenomenon that above-mentioned barrier layer is peeled off more can cause the pollution of board.
Therefore, because the various disappearances that derived about the Waffer edge peeling off phenomenon in the prior art, how to provide that a kind of can effectively to solve the phenomenon that Waffer edge peels off be an instant research topic to improve yield and to avoid the contaminated method of board.
(3) summary of the invention
In above-mentioned background of invention, prior art is being eliminated many shortcomings that Waffer edge is produced aspect peeling off, a main purpose of the present invention is for providing one to eliminate the method that Waffer edge is peeled off, by in the plain conductor processing procedure, adding the step remove the film that is positioned at Waffer edge together, to avoid in follow-up processing procedure producing the various defectives in the prior art because Waffer edge peels off.
Another object of the present invention is for providing one to eliminate the method that Waffer edge is peeled off.According to design of the present invention, can be by after forming plain conductor, adding the step that removes the Waffer edge film together, to improve the yield of wafer.
Another purpose of the present invention is for providing one to eliminate the method that Waffer edge is peeled off.The method that above-mentioned elimination Waffer edge is peeled off can be by adding the step that remove the Waffer edge film together after forming plain conductor, with reduce board because of peeling off of Waffer edge contaminated probability.
According to above-described purpose, the invention provides one and eliminate the method that Waffer edge is peeled off.The method that above-mentioned elimination Waffer edge is peeled off can be applicable in the plain conductor processing procedure.According to design of the present invention, form one comprise the structure of metal carbonyl conducting layer after, can add the step of one cleaning Waffer edge, to remove structure or the film that is arranged in Waffer edge and may peels off in successive process.The above-mentioned step that removes the strippable film of the brilliant back of the body and Waffer edge can be by removing (edge bevel removal such as crystal edge; EBR) technology, or the technology that crystal edge grinds removes the strippable film that is positioned at Waffer edge, with the variety of issue of avoiding in successive process, deriving because peeling off phenomenon.
Compared to prior art, the present invention can effectively prevent above-mentioned generation of peeling off phenomenon.According to design of the present invention, by one step that after the formation metal carbonyl conducting layer is on wafer, is added, remove class such as barrier layer and be positioned at Waffer edge and the film that may peel off or the patterned metal layer fully on it, to reach problems such as avoiding the yield decline that causes because of peeling off phenomenon or board pollution.Therefore,, not only can effectively prevent the generation of peeling off phenomenon in the prior art, more can effectively improve the yield of manufacture of semiconductor according to design of the present invention.In addition, more can effectively reduce the contaminated chance of board according to design of the present invention.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Fig. 1 is a flow chart according to the copper conductor processing procedure of prior art;
Fig. 2 is the flow chart of the method peeled off of an elimination Waffer edge according to the present invention;
The flow chart of the method that Fig. 3 A peels off for another elimination Waffer edge according to the present invention;
Fig. 3 B is the flow chart of the method peeled off of another elimination Waffer edge according to the present invention;
The flow chart of the method that Fig. 3 C peels off for an elimination Waffer edge according to the present invention again.
(5) embodiment
Some embodiments of the present invention can be described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment, and scope of the present invention do not limited, its with after claim institute restricted portion be as the criterion.
A preferred embodiment of the present invention is a kind of method that Waffer edge is peeled off of eliminating.In the plain conductor processing procedure, in order to prevent that employed metal diffusing to ground or other are arranged in the structure of metal carbonyl conducting layer below, usually before forming metal carbonyl conducting layer, can form earlier on thin film is positioned at the metal carbonyl conducting layer below in ground or other the structure with as barrier layer (barrier layer).Above-mentioned film can form by membrane deposition method, for example gas phase physical deposition (Physical VaporDeposition).Design according to present embodiment, after forming metal carbonyl conducting layer, part barrier layer in Waffer edge will the mode with film expose because of the removal of metal carbonyl conducting layer on it, this can remove the film that may peel off by the step of clearing up Waffer edge together in successive process, for example Waffer edge or chip back surface residual unnecessary barrier layer, and then can effectively overcome in prior art because Waffer edge takes place and peeled off and the various defectives of deriving.
Method according to present embodiment comprises formation one barrier layer and the step of a metal-layer structure on a wafer at least, with the step that removes the strippable film that is positioned at above-mentioned Waffer edge.The above-mentioned step that is positioned at the Waffer edge strippable film that removes mainly is meant to remove and is positioned at the Waffer edge or the brilliant back of the body, and not by film that metal level covered.In the example according to present embodiment, above-mentioned removing is positioned at the step of the strippable film of Waffer edge can remove (edge bevel removal by crystal edge; EBR) technology realizes.In this example, be arranged in Waffer edge or the strippable film of the brilliant back of the body can use an acidic aqueous solution to remove by the process at EBR.
In another example according to present embodiment, the above-mentioned strippable film that is positioned at Waffer edge or is positioned at the brilliant back of the body can remove by the method for edge grinding (edge polishing).In the step of above-mentioned edge grinding, the lapping liquid that can use an alkalescence is to assist to remove above-mentioned unnecessary structure.
Another preferred embodiment of the present invention is a kind of method that Waffer edge is peeled off of eliminating.In the present embodiment, can be by forming metal carbonyl conducting layer to adding the step that removes the brilliant back of the body and Waffer edge barrier layer together between following one manufacture of semiconductor, preventing that above-mentioned strippable film from peeling off in follow-up manufacture of semiconductor, and then cause the puzzlement on the successive process and the defective of wafer.
Fig. 2 is a flow chart according to the plain conductor processing procedure of present embodiment.With reference to Fig. 2, at first, form a metal carbonyl conducting layer on a wafer, shown in step 220.The composition of above-mentioned metal carbonyl conducting layer can comprise copper, aluminium or other plain conductor material.Above-mentioned metal carbonyl conducting layer can form by a common method, for example electrochemistry galvanoplastic (electro-chemical plating; ECP).Then, above-mentioned metal carbonyl conducting layer is carried out the step of a planarization to remove metal load layer unnecessary on the wafer (overburden layer), shown in step 240.Above-mentioned step of carrying out a planarization can be finished by the common mode of CMP and so on.
Next, shown in step 260, remove and be positioned at flaky film on Waffer edge or the chip back surface, for example unnecessary barrier layer.Wherein, above-mentioned film comprises barrier layer and the metal-layer structure on it that may peel off in successive process.In the example according to present embodiment, above-mentioned step 260 can be finished by the technology of EBR.In this example, above-mentioned EBR can use an acid solution hydro-peening Waffer edge and chip back surface respectively, to remove unnecessary barrier layer or other easy exfoliated structure.One of prescription of above-mentioned acid solution can be the aqueous solution that comprises nitric acid (HNO3) and hydrofluoric acid (HF) at least.In the above-mentioned aqueous solution, the concentration of nitric acid is between 5 ~ 45%, and the concentration of hydrofluoric acid is between 0.1 ~ 5%.The operating temperature of above-mentioned EBR is about 20 ~ 70 ℃.
In another example according to present embodiment, the unnecessary barrier layer or other structures that are positioned at Waffer edge also can remove by the mode that a crystal edge grinds.According to this example, can use the lapping liquid of an alkalescence to carry out crystal edge and grind reaching the purpose that removes the film that is positioned at Waffer edge, wherein above-mentioned film comprises the barrier layer that may peel off or the metal-layer structure on it in successive process.In the process that above-mentioned crystal edge grinds, the Silica lapping liquid that employed alkaline lapping liquid can be an alkalescence.The pH value of the Silica lapping liquid of above-mentioned alkalescence is 7 ~ 12.The acid solution of it should be noted that in the present embodiment to be narrated and the composition of alkaline solution, ratio, and other parameter only is the implementation of each preferable example, is not in order to limit the scope of the invention.
Above-mentioned wafer can enter down manufacture of semiconductor one, shown in step 280 after through the above-mentioned step (step 260) that removes the brilliant back of the body and Waffer edge film.In according to another example of the present invention, between the step 280 of descending manufacture of semiconductor, the step (not being shown among Fig. 2) that also can add one cleaning and drying crystal wafer is to remove the residue of wafer surface in the above-mentioned step 260 that removes the brilliant back of the body and Waffer edge film.
Another preferred embodiment of the present invention is a kind of method that Waffer edge is peeled off of eliminating.Fig. 3 A to Fig. 3 C is respectively three kinds of methods of peeling off according to the elimination Waffer edge of present embodiment.With reference to Fig. 3 A, in a plain conductor processing procedure, usually comprise at least and form the step (as step 320) of a metal carbonyl conducting layer on a wafer, one tempering step (as step 340), use such as cmp (CMP) or other technology are carried out the planarization of plain conductor laminar surface and are removed metal carbonyl conducting layer unnecessary on the wafer (as step 360), enter down one processing procedure (as step 380) afterwards again.Wherein, above-mentioned metal carbonyl conducting layer can be by copper, aluminium, or other metal is formed.Above-mentioned metal carbonyl conducting layer can common method form such as the electrochemistry galvanoplastic.
Before forming metal carbonyl conducting layer; for fear of employed metal diffusing to other structures that are positioned at metal carbonyl conducting layer below; for example silicon base material and dielectric layer (dielectric layer); usually can first use can reduce the material of ions diffusion effect (such as Ta; TaN, TiN and TiW) formation one barrier layer on wafer.Yet, the above-mentioned barrier layer and the structure of some material, for example naked crystal silicon (bare Si), between adhesive ability relatively poor, so many problems might be peeled off and derive to the processing procedure of barrier layer after forming metal carbonyl conducting layer that is arranged in Waffer edge.
In order to solve the variety of issue that produces because the barrier layer of Waffer edge peels off in the prior art, the design of present embodiment is after forming metal carbonyl conducting layer (as step 320), to descending one processing procedure (as step 380) before, add the step (as step 400) that removes easy stripping film together.Its objective is to remove and be positioned at Waffer edge or chip back surface, and do not form unnecessary barrier layer or other structures (as formed incomplete patterning metal-layer structure on the barrier layer) of pattern, with the variety of issue of avoiding in follow-up processing procedure, producing because above-mentioned unnecessary barrier layer or other structures peel off.
With reference to Fig. 3 A, in according to one example of the present invention, can carry out tempering step (step 340) before, carry out the above-mentioned step (step 400) that removes easy stripping film earlier.In the above-mentioned step that removes easy stripping film, can come hydro-peening and remove to be positioned at Waffer edge or chip back surface with an acid solution by the technology of EBR, do not form barrier layer or other structures of pattern.Wherein, above-mentioned acid solution can be the aqueous solution that comprises nitric acid (about 5 ~ 45%) and hydrofluoric acid (about 0.1 ~ 5%).
Except the technology of using EBR, the above-mentioned Waffer edge or the barrier layer of chip back surface or other structures of being positioned at also can use the crystal edge grinding technique of alkaline lapping liquid to remove by one.Wherein, above-mentioned alkaline lapping liquid can be that a pH value is 7 ~ 12 Silica lapping liquid.
In another example, the above-mentioned step (step 400) that removes unnecessary formation thing also can be carried out the planarization of plain conductor laminar surface and remove the brilliant back of the body and Waffer edge excess metal conductor layer step (step 360) is carried out before above-mentioned, shown in Fig. 3 B.As noted before, in the above-mentioned step that removes easy stripping film (step 400), the barrier layer or other structures that are positioned at Waffer edge or chip back surface and do not form pattern can remove with acid solution by the hydro-peening mode of EBR, or remove with the crystal edge grinding technique that uses alkaline lapping liquid.
In another example according to present embodiment, the above-mentioned step (step 400) that removes easy stripping film also can be carried out afterwards in the planarization of carrying out the plain conductor laminar surface and the step (as step 360) that remove the brilliant back of the body and Waffer edge excess metal conductor layer, shown in Fig. 3 C.Same, can be by such as using acid solution EBR hydro-peening mode for the position in the barrier layer of Waffer edge or chip back surface or other structures, or the technology of using the crystal edge of alkaline lapping liquid to grind and so on removes.
It should be noted that in the present embodiment, above-mentioned composition about acid solution and alkaline solution, ratio, and the narration of other parameter is not in order to limit the scope of the invention only as the explanation usefulness of preferred embodiment of the present invention.
In the plain conductor processing procedure of prior art,, can before forming metal carbonyl conducting layer, form one deck barrier layer earlier on wafer usually in order to prevent employed metal diffusing to other structure.But the barrier layer that has part to be positioned at Waffer edge will be exposed to the open air out because of the removal of metal carbonyl conducting layer.Because the adhesive force between the structure sheaf (for example naked crystal silicon) on barrier layer and some wafer is relatively poor, so, the above-mentioned Waffer edge that is positioned at, even barrier layer former because of some thereby that be formed at chip back surface can be peeled off in follow-up processing procedure most probably.Above-mentioned barrier layer peel off the defective that will cause wafer.The meeting that extent of exfoliation is lighter causes the reduction of yield, and extent of exfoliation more serious in addition can cause scrapping of wafer.And the fragment that is stripped down more can cause the pollution of board.It should be noted that the above-mentioned phenomenon of peeling off does not have the adequate solution scheme in prior art, particularly in the copper conductor processing procedure, above-mentioned problem still can't be by adequate solution.
Shortcoming in the above-mentioned prior art in design of the present invention, can remove brilliant the back of the body and the barrier layer of Waffer edge or the step of other structures by adding, together to prevent above-mentioned generation of peeling off phenomenon after forming plain conductor.In other words, in design according to the present invention, by one step that after the formation metal carbonyl conducting layer is on wafer, is added, remove and be positioned at Waffer edge and the film that may peel off or structure, for example above-mentioned not by the barrier layer that metal carbonyl conducting layer covered, descend or problem such as board pollution with the yield avoiding causing because of peeling off phenomenon.Therefore,, not only can effectively improve yield, more can reduce the contaminated chance of board according to design of the present invention.
Comprehensively above-mentioned, the invention provides one and eliminate the method that Waffer edge is peeled off, wherein above-mentioned method can be applied in the plain conductor processing procedure.The method that above-mentioned elimination Waffer edge is peeled off comprises at least: form the step of structure on a wafer that comprises a barrier layer and a metal carbonyl conducting layer, with the step that removes the easy stripping film that is positioned at the Waffer edge or the brilliant back of the body.The above-mentioned step that removes the easy stripping film that is positioned at the Waffer edge or the brilliant back of the body comprises not remove and is covered by above-mentioned metal carbonyl conducting layer, and the film that may peel off (for example barrier layer) or the metal-layer structure on it.The above-mentioned step that removes the easy stripping film that is positioned at the Waffer edge or the brilliant back of the body can be by an EBR technology, or the technology of grinding by crystal edge removes.Therefore, not only can avoid in the prior art more can significantly improving the yield of wafer by design of the present invention because peel off the various defectives that phenomenon causes.Be more preferably, more can significantly reduce the contaminated chance of board according to design of the present invention.
Though the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, should understand and wherein can make variations and modifications and do not break away from the present invention in a broad sense, so be not as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the distortion of the above embodiment.
Claims (29)
1. eliminate the method that Waffer edge is peeled off for one kind, comprise:
Form a film on wafer;
Form a graphical metal structure on wafer;
The planarization wafer surface is to remove this unnecessary on the wafer graphical metal structure, and wherein this planarisation step exposes this film of part of Waffer edge; And
Remove this film of part that exposes.
2. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that this film comprises in order to prevent a barrier layer of metal ion diffusion.
3. the method that elimination Waffer edge as claimed in claim 2 is peeled off is characterized in that the material of this barrier layer is selected from Ta, TaN, TiN or TiW.
4. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that the formation method of described film comprises the method that is formed uniformly film with membrane deposition method.
5. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that described graphical metal-layer structure comprises a metal carbonyl conducting layer.
6. the method that elimination Waffer edge as claimed in claim 5 is peeled off is characterized in that the material of described graphical metal carbonyl conducting layer is selected from copper or aluminium.
7. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that described planarisation step comprises use etching and chemical and mechanical grinding method.
8. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that the described step that removes comprises this residual graphical metal structure that removes after this planarisation step.
9. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that described this film of the part that exposes is to be positioned at Waffer edge.
10. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that described what expose partly is the crystalline substance back of the body of this thin film wafers.
11. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that the described technology that step is to use a crystal edge to remove that removes.
12., it is characterized in that the described step that removes is to use an acid solution as the method that the elimination Waffer edge of claim 11 is peeled off.
13. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that the described technology that step is to use a crystal edge to grind that removes.
14., it is characterized in that the described step that removes is to use an alkaline lapping liquid as the method that the elimination Waffer edge of claim 13 is peeled off.
15. the method that elimination Waffer edge as claimed in claim 1 is peeled off is characterized in that also comprising drying crystal wafer.
16. eliminate the method that Waffer edge is peeled off, comprise for one kind:
Form a barrier layer on a wafer;
Form a metal carbonyl conducting layer on this barrier layer, wherein, this barrier layer of part that is covered by this metal carbonyl conducting layer is not exposed;
Remove this barrier layer of part that exposes;
Carry out tempering step in this wafer; And
Carry out planarisation step to remove this unnecessary on this wafer metal carbonyl conducting layer.
17. the method that elimination Waffer edge as claimed in claim 16 is peeled off, the material that it is characterized in that described barrier layer are to be Ta.
18. the method that elimination Waffer edge as claimed in claim 16 is peeled off, the material that it is characterized in that described barrier layer are to be TaN.
19. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that described metal carbonyl conducting layer is a copper conductor layer.
20. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that described metal carbonyl conducting layer comprises this barrier layer and is positioned at the part that the brilliant back of the body exposes.
21. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that also comprising this barrier layer of part of the crystalline substance back of the body that removes this wafer that exposes.
22. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that the described step that removes comprises not this metal carbonyl conducting layer of complete patterning that removes on this barrier layer.
23. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that the described step that removes comprises use one crystal edge clearance technique.
24. the method that elimination Waffer edge as claimed in claim 23 is peeled off is characterized in that the described step that removes is to use an acid solution.
25. the method that elimination Waffer edge as claimed in claim 24 is peeled off is characterized in that described acid solution is one to comprise the aqueous solution of nitric acid and hydrofluoric acid.
26. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that the described step that removes comprises use one crystal edge grinding technique.
27. the method that elimination Waffer edge as claimed in claim 26 is peeled off is characterized in that the described step that removes is to use an alkaline solution.
28. the method that elimination Waffer edge as claimed in claim 27 is peeled off, the pH value that it is characterized in that described alkaline lapping liquid is 7～12.
29. the method that elimination Waffer edge as claimed in claim 16 is peeled off is characterized in that described planarisation step comprises etching and the chemical and mechanical grinding method that uses planarization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310102864 CN1610078A (en) | 2003-10-22 | 2003-10-22 | Method for removing stripping of wafer edge |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200310102864 CN1610078A (en) | 2003-10-22 | 2003-10-22 | Method for removing stripping of wafer edge |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423193C (en) * | 2005-09-15 | 2008-10-01 | 联华电子股份有限公司 | Semiconductor producing method for preventing crystal border film layer from stripping and interconnection wire producing method |
| US7595211B2 (en) | 2005-12-29 | 2009-09-29 | Dongbu Hitek Co., Ltd. | Method of manufacturing a complementary metal oxide silicon image sensor |
| CN104241129A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal grid transistor |
| CN104241131A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal grid transistor |
| CN110473775A (en) * | 2019-08-29 | 2019-11-19 | 上海华力集成电路制造有限公司 | Improve the method for film removing |
-
2003
- 2003-10-22 CN CN 200310102864 patent/CN1610078A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423193C (en) * | 2005-09-15 | 2008-10-01 | 联华电子股份有限公司 | Semiconductor producing method for preventing crystal border film layer from stripping and interconnection wire producing method |
| US7595211B2 (en) | 2005-12-29 | 2009-09-29 | Dongbu Hitek Co., Ltd. | Method of manufacturing a complementary metal oxide silicon image sensor |
| CN104241129A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal grid transistor |
| CN104241131A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal grid transistor |
| CN104241131B (en) * | 2013-06-09 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | The forming method of metal gate transistor |
| CN110473775A (en) * | 2019-08-29 | 2019-11-19 | 上海华力集成电路制造有限公司 | Improve the method for film removing |
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