US20050085163A1 - Method for preventing edge peeling defect - Google Patents
Method for preventing edge peeling defect Download PDFInfo
- Publication number
- US20050085163A1 US20050085163A1 US10/685,588 US68558803A US2005085163A1 US 20050085163 A1 US20050085163 A1 US 20050085163A1 US 68558803 A US68558803 A US 68558803A US 2005085163 A1 US2005085163 A1 US 2005085163A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- thin film
- barrier layer
- metal interconnect
- interconnect layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 69
- 230000007547 defect Effects 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000010409 thin film Substances 0.000 claims description 47
- 230000004888 barrier function Effects 0.000 claims description 40
- 238000005516 engineering process Methods 0.000 claims description 17
- 238000005498 polishing Methods 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 239000002253 acid Substances 0.000 claims description 12
- 239000002002 slurry Substances 0.000 claims description 12
- 230000003340 mental effect Effects 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 5
- 229910017604 nitric acid Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 27
- 239000004065 semiconductor Substances 0.000 abstract description 24
- 239000002313 adhesive film Substances 0.000 abstract description 8
- 239000000853 adhesive Substances 0.000 description 13
- 230000001070 adhesive effect Effects 0.000 description 13
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 239000012634 fragment Substances 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/0209—Cleaning of wafer backside
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/02087—Cleaning of wafer edges
Definitions
- This present invention relates to a semiconductor manufacturing, and more particularly, to a method for preventing the edge peeling defect after an interconnect process.
- Interconnect plays an important role in a semiconductor structure. For instance of copper interconnect, particularly for the semiconductor manufacture of deep sub-micron (DSM), by employing Copper interconnect process and the low-K material as the dielectric layer, the RC delay (resistance capacitance time delay) and the electro-migration effect can be reduced.
- DSM deep sub-micron
- FIG. 1 depicts a flowchart of a copper interconnect structure in the prior art.
- a Copper interconnect layer is formed on a wafer, as the step 120 .
- the Copper interconnect layer can be formed by electro-chemical plating (ECP) or other well-known technology.
- ECP electro-chemical plating
- CMP chemical mechanical polishing
- a wafer cleaning and drying step is performed. Afterward the wafer can be sent to the next process as shown in the step 180 .
- a barrier layer which is consisted of Ta, TaN, or the like materials, is employed for keeping the metal from diffusing into the other elements under the metal interconnect layer.
- the adhesion of the barrier layer to some structure, such as the bare Si is not good enough, the peeling of portions of the barrier layer at the wafer edge, even including the structure on the barrier layer at the wafer edge, may happen during the following process.
- the above-mentioned peeling will cause many defects in the semiconductor manufacture. For example, the yield of the wafer manufacture may be reduced by the above-mentioned peeling. If the peeling is serious, the wafer will become useless and waste. Moreover, the chamber(s) of the semiconductor manufacture will be polluted by the above-mentioned peeling.
- a method for preventing edge peeling defect is provided for preventing the peeling defects by introducing a step for removing the structure or thin film at the wafer edge in an interconnect manufacture, so that the peeling defects in the prior art can be efficiently prevented.
- the invention provides a method for preventing edge peeling defect.
- the above-mentioned method can be applied in an interconnect manufacture.
- a step is introduced for removing the structure or thin film at the wafer edge, wherein the structure or thin film is not covered by the metal interconnect layer and may be peeling in the following process.
- the above-mentioned structure or thin film can be removed by the edge bevel removal technology, or the edge polishing technology. Therefore, according to this invention, it is efficiently for preventing the peeling defects in the prior art, and the yield of the semiconductor manufacture can be efficiently improved.
- the pollution, due to the peeling fragment, of the chamber(s) of the semiconductor manufacture can be decreased by the design of this invention.
- FIG. 1 is a flowchart for manufacturing a Copper interconnect according to the prior art
- FIG. 2 is a flowchart of the method for preventing edge peeling defect according to this presented invention
- FIG. 3A is a flowchart of another method for preventing edge peeling defect of this present invention.
- FIG. 3B is another flowchart of the method for preventing edge peeling defect according to this present invention.
- FIG. 3C is still another flowchart of the method for preventing edge peeling defect according to this invention.
- One preferred embodiment of this invention is a method for preventing edge peeling defect.
- a thin film is usually formed on the substrate or the structure under the metal interconnect layer to be the barrier layer before forming the metal interconnect layer.
- the thin film can be formed by deposition, i.e. Physical Vapor Deposition.
- the barrier layer at the edge bevel on the wafer would appeal as a thin film because the removal of the part of upper interconnect layer.
- a step for cleaning the edge bevel of the wafer is introduced, and thus the defects caused by the edge peeling in the prior art can be efficiently prevented by the method of this embodiment.
- the method of this embodiment at least comprises the steps of forming a barrier layer and forming a mental layer structure on a wafer, and removing the weakly adhesive film at the wafer edge.
- the step of removing the weakly adhesive film at the wafer edge is employed for removing the thin film at the wafer edge or wafer backside not covered by the metal layer.
- an edge bevel removal (EBR) technology may be employed in the above-mentioned step for removing the weakly adhesive film at the wafer edge.
- the weakly adhesive film at the wafer edge or at the wafer backside can be removed by the EBR technology with an acid aqueous.
- the weakly adhesive film at the wafer edge or at the wafer backside can be removed by the edge polishing technology.
- a base slurry is employed in the above-mentioned step during removing the weakly adhesive film with the edge polishing technology.
- Another preferred embodiment of this present invention is a method for preventing edge peeling defect. According to this embodiment, between the steps of manufacturing the metal interconnect layer and going to the next semiconductor process, a step for removing weakly adhesive film at the edge bevel or at the wafer backside is performed for preventing the peeling defects in the prior art.
- FIG. 2 shows a flowchart of an interconnect manufacture of this embodiment.
- a metal interconnect layer is formed on a wafer, as the step 220 .
- the metal interconnect layer is consisted of Copper, Aluminum, or other metal materials.
- the metal interconnect layer may be formed by electro-chemical plating (ECP) or other well-known technology.
- ECP electro-chemical plating
- step 240 for planarizing the metal interconnect layer and removing the redundant metal on the wafer is performed with an usual technology, such as chemical mechanical polishing (CMP), edge bevel removal (EBR), or the likes.
- CMP chemical mechanical polishing
- EBR edge bevel removal
- the structure or thin film at the wafer edge or at the wafer backside such as the barrier layer or the upper mental layer structure at the wafer edge, is removed.
- the above-mentioned structure or thin film at the wafer edge is not covered by the metal interconnect layer and may be peeling in the following processes.
- the EBR technology may be employed in the step 260 for removing the structure or thin film.
- An acid aqueous may be used in the EBR treatment for removing the weakly adhesive structure at the wafer edge or at the wafer backside.
- One of the formulas of the above-mentioned acid aqueous comprises nitric acid (HNO 3 ) and hydrofluoric acid (HF). In the mentioned formula, the concentration of HNO 3 is about 5 ⁇ 45%, and the concentration of HF is about 0.1 ⁇ 5%.
- the EBR treatment can be performed at 20 ⁇ 70° C.
- the barrier layer or other structure at the wafer edge or at the wafer backside can be removed by the edge polishing technology.
- a base slurry may be used for removing the structure.
- the mentioned base slurry may be a base Silica slurry, and the pH of the slurry is about 7 ⁇ 12. It should be noted that all the descriptions of the treatment of the step 260 and the acid/base solution, such as the formulas, the ratio, and other parameters, are employed for the explanation of the embodiment, and this invention is not limited by the above-mentioned descriptions.
- the next semiconductor process can be performed onto the wafer, as the step 280 .
- a treatment of wafer cleaning and drying may be employed for removing the residue on the surface of the wafer, not shown in FIG. 2 .
- FIG. 3A to 3 C respectively depicts three applications of the method for preventing edge peeling defect according to this embodiment.
- an interconnect manufacturing usually comprises the steps of forming an interconnect layer on a wafer (as the step 320 ); annealing (as the step 340 ); palanarizing the metal interconnect layer and removing the metal at the edge bevel or at the wafer backside by CMP or other treatment (as the step 360 ); and going to the next semiconductor process (as the step 380 ).
- the metal interconnect layer may be consisted of Copper, Aluminum, or other metal materials, and formed by ECP or other well-known technology.
- a conformal barrier layer is formed on the wafer before forming the metal interconnect layer.
- the barrier layer is consisted of TaN, Ta, TiN, TiW, or the like materials.
- the adhesion of the barrier layer to some semiconductor structure, such as bare Si is not good enough, and thus many defects caused by the peeling of the redundant barrier layer at the wafer edge or at the wafer backside will happen at the following semiconductor processes.
- a step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside is performed between the steps of forming the metal interconnect layer (as the step 320 ) and going to the next semiconductor process (as the step 380 ) in this embodiment.
- the above-mentioned step for removing the weakly adhesive thin film at the wafer edge or at the wafer backside is employed for removing the redundant barrier layer or other unwanted structure not covered by the metal interconnect layer (the redundant barrier layer and other unwanted structure are not patterned), wherein the above-mentioned redundant barrier layer or the unwanted structure might be peeling in the following processes.
- the peeling defects in the prior art can be efficiently prevented by the design of this embodiment.
- the step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside can be performed before the annealing step (as the step 340 ).
- the EBR treatment may be employed for removing the redundant barrier layer or the unwanted structure at the wafer edge or at the wafer backside, wherein the barrier layer or the unwanted structure or thin film is not covered by the metal interconnect layer.
- the EBR treatment may be performed with an acid solution.
- the acid solution is an aqueous comprising HNO 3 (about 5 ⁇ 45%) and HF (about 0.1 ⁇ 5%).
- the edge polishing technology can be employed in the above-mentioned step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside (as the step 400 ) to remove the redundant barrier layer or unwanted structure at the wafer edge or at the wafer backside.
- a base slurry may be employed for removing the weakly adhesive thin film at the edge bevel or at the wafer backside.
- the base slurry may be a Silica slurry, and the pH of the slurry is about 7 ⁇ 12.
- the above-mentioned step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside is performed between the step of annealing (as the step 340 ) and the step for removing the metal at the edge bevel or at the wafer backside (as the step 360 ).
- the unwanted structure or thin film can be removed by employing the EBR treatment with the acid solution, or by employing the edge polishing treatment with the base slurry.
- the above-mentioned unwanted structure is the incompletely patterned part of mental interconnect layer at the wafer edge or at the wafer backside, and is not covered by the metal interconnect layer.
- the above-mentioned unwanted structure may be peeling in the following process.
- the above-mentioned step 400 of removing the weakly adhesive thin film at the edge bevel or at the wafer backside can be performed after the step for removing the metal at the edge bevel or at the wafer backside (as the step 360 ).
- the unwanted structure or thin film also can be removed by the EBR treatment with the acid solution, or by the edge polishing with the base slurry.
- a barrier layer is usually formed on the wafer before forming the metal interconnect layer. After forming the metal interconnect layer, portions of the barrier layer at the wafer edge will not be covered by the metal interconnect layer, and be exposed. Because the adhesion of the barrier layer to some semiconductor structure, such as the bare Si, is not good enough, the exposed barrier layer at the wafer edge will be possibly peeling in the next processes following the interconnect manufacture. The above-mentioned peeling will cause many defects, for example, the decreasing of the yield of the wafer. Particularly, if the peeling is serious, the wafer will become useless.
- the chamber(s) of the semiconductor manufacture will be polluted by the fragments of the above-mentioned peeling. It should be noted that there is still no suitable way for resolving the peeling defects in the prior art, particularly in the Copper interconnect manufacture.
- the above-mentioned peeling defects can be efficiently prevented by introducing a step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside after forming the metal interconnect layer. That is, the above-mentioned step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside is performed between the step of forming the metal interconnect layer and the step of going to the next process.
- the above-mentioned step of this invention is employed for removing the unwanted structure at the wafer edge or at the wafer backside, wherein the structure or thin film may be peeling in the following processes.
- the above-mentioned structure or film is not covered by the metal interconnect layer and removed by the design of this invention.
- the defects caused by the above-mentioned peeling such as the decreasing of the yield, the pollution of the chamber(s), and the likes, can be efficiently resolved. Therefore, according to the design of this invention, the yield can be efficiently raised, and the pollution chance of the chamber(s) can be lowered.
- this invention discloses a method for preventing edge peeling defect.
- the above-mentioned method can applied in an interconnect manufacture.
- the method for preventing edge peeling defect at least comprises the steps of forming a structure comprising a metal interconnect layer on a wafer, and a step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside.
- the unwanted structure comprising the barrier layer at the wafer edge, is not covered by the metal interconnect layer, and may be peeling in the following processes.
- the unwanted structure or thin film can be removed by an EBR treatment, or by an edge polishing treatment.
- this present invention can efficiently prevent the defects caused by the peeling of the unwanted structure or thin film in the prior art.
- the yield of the semiconductor manufacture can be efficiently raised.
- the chamber(s) of the semiconductor manufacture can be kept from the pollution of the peeling fragments in the prior art, and the pollution chance of the chamber(s) can be decreased.
Abstract
A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.
Description
- 1. Field of the Invention
- This present invention relates to a semiconductor manufacturing, and more particularly, to a method for preventing the edge peeling defect after an interconnect process.
- 2. Description of the Prior Art
- Interconnect plays an important role in a semiconductor structure. For instance of copper interconnect, particularly for the semiconductor manufacture of deep sub-micron (DSM), by employing Copper interconnect process and the low-K material as the dielectric layer, the RC delay (resistance capacitance time delay) and the electro-migration effect can be reduced.
- For example,
FIG. 1 depicts a flowchart of a copper interconnect structure in the prior art. Referring toFIG. 1 , first of all, a Copper interconnect layer is formed on a wafer, as thestep 120. The Copper interconnect layer can be formed by electro-chemical plating (ECP) or other well-known technology. Subsequently, a step is performed for planarizing the surface of the Copper interconnect layer and removing the redundant Copper on the wafer by chemical mechanical polishing (CMP) or the like technology, as thestep 140. Next, referring to thestep 160, a wafer cleaning and drying step is performed. Afterward the wafer can be sent to the next process as shown in thestep 180. - In a metal (Copper) interconnect manufacturing process, a barrier layer, which is consisted of Ta, TaN, or the like materials, is employed for keeping the metal from diffusing into the other elements under the metal interconnect layer. However, because the adhesion of the barrier layer to some structure, such as the bare Si, is not good enough, the peeling of portions of the barrier layer at the wafer edge, even including the structure on the barrier layer at the wafer edge, may happen during the following process. The above-mentioned peeling will cause many defects in the semiconductor manufacture. For example, the yield of the wafer manufacture may be reduced by the above-mentioned peeling. If the peeling is serious, the wafer will become useless and waste. Moreover, the chamber(s) of the semiconductor manufacture will be polluted by the above-mentioned peeling.
- Hence, for improving the yield of the semiconductor manufacture and reducing the pollution of the chambers, it is an important object to provide a method for preventing edge peeling defect.
- In accordance with the present invention, a method for preventing edge peeling defect is provided for preventing the peeling defects by introducing a step for removing the structure or thin film at the wafer edge in an interconnect manufacture, so that the peeling defects in the prior art can be efficiently prevented.
- It is another object of this invention to raising the yield of the semiconductor manufacture by performing a step for removing the thin film at the wafer edge and at the wafer backside.
- It is still another object of this present invention to decrease the pollution source of the chamber(s) of the semiconductor manufacture by performing a step for removing the thin film at the wafer edge and at the wafer-backside after forming an interconnect layer on the wafer, wherein the structure may be peeling in the following process, and thus the pollution chance of the chamber(s) will be lowered by this invention.
- In accordance with the above-mentioned objects, the invention provides a method for preventing edge peeling defect. The above-mentioned method can be applied in an interconnect manufacture. According to this prevent invention, after forming a structure comprising an interconnect layer on a wafer, a step is introduced for removing the structure or thin film at the wafer edge, wherein the structure or thin film is not covered by the metal interconnect layer and may be peeling in the following process. The above-mentioned structure or thin film can be removed by the edge bevel removal technology, or the edge polishing technology. Therefore, according to this invention, it is efficiently for preventing the peeling defects in the prior art, and the yield of the semiconductor manufacture can be efficiently improved. Moreover, the pollution, due to the peeling fragment, of the chamber(s) of the semiconductor manufacture can be decreased by the design of this invention.
- The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
-
FIG. 1 is a flowchart for manufacturing a Copper interconnect according to the prior art; -
FIG. 2 is a flowchart of the method for preventing edge peeling defect according to this presented invention; -
FIG. 3A is a flowchart of another method for preventing edge peeling defect of this present invention; -
FIG. 3B is another flowchart of the method for preventing edge peeling defect according to this present invention; and -
FIG. 3C is still another flowchart of the method for preventing edge peeling defect according to this invention. - Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims.
- One preferred embodiment of this invention is a method for preventing edge peeling defect. In a metal interconnect manufacturing, in order to keeping the metal diffusing into the substrate or other structure under the metal interconnect layer, a thin film is usually formed on the substrate or the structure under the metal interconnect layer to be the barrier layer before forming the metal interconnect layer. The thin film can be formed by deposition, i.e. Physical Vapor Deposition. After the metal interconnect layer is formed, the barrier layer at the edge bevel on the wafer would appeal as a thin film because the removal of the part of upper interconnect layer. According to this embodiment, a step for cleaning the edge bevel of the wafer is introduced, and thus the defects caused by the edge peeling in the prior art can be efficiently prevented by the method of this embodiment.
- The method of this embodiment at least comprises the steps of forming a barrier layer and forming a mental layer structure on a wafer, and removing the weakly adhesive film at the wafer edge. The step of removing the weakly adhesive film at the wafer edge is employed for removing the thin film at the wafer edge or wafer backside not covered by the metal layer. In one case of this present embodiment, an edge bevel removal (EBR) technology may be employed in the above-mentioned step for removing the weakly adhesive film at the wafer edge. In this case, the weakly adhesive film at the wafer edge or at the wafer backside can be removed by the EBR technology with an acid aqueous.
- In another case of this embodiment, the weakly adhesive film at the wafer edge or at the wafer backside can be removed by the edge polishing technology. In this case, a base slurry is employed in the above-mentioned step during removing the weakly adhesive film with the edge polishing technology.
- Another preferred embodiment of this present invention is a method for preventing edge peeling defect. According to this embodiment, between the steps of manufacturing the metal interconnect layer and going to the next semiconductor process, a step for removing weakly adhesive film at the edge bevel or at the wafer backside is performed for preventing the peeling defects in the prior art.
-
FIG. 2 shows a flowchart of an interconnect manufacture of this embodiment. Referring toFIG. 2 , first of all, a metal interconnect layer is formed on a wafer, as thestep 220. The metal interconnect layer is consisted of Copper, Aluminum, or other metal materials. The metal interconnect layer may be formed by electro-chemical plating (ECP) or other well-known technology. Next,step 240 for planarizing the metal interconnect layer and removing the redundant metal on the wafer is performed with an usual technology, such as chemical mechanical polishing (CMP), edge bevel removal (EBR), or the likes. - Subsequently, as shown in the
step 260, the structure or thin film at the wafer edge or at the wafer backside, such as the barrier layer or the upper mental layer structure at the wafer edge, is removed. The above-mentioned structure or thin film at the wafer edge is not covered by the metal interconnect layer and may be peeling in the following processes. In one case of this embodiment, the EBR technology may be employed in thestep 260 for removing the structure or thin film. An acid aqueous may be used in the EBR treatment for removing the weakly adhesive structure at the wafer edge or at the wafer backside. One of the formulas of the above-mentioned acid aqueous comprises nitric acid (HNO3) and hydrofluoric acid (HF). In the mentioned formula, the concentration of HNO3 is about 5˜45%, and the concentration of HF is about 0.1˜5%. The EBR treatment can be performed at 20˜70° C. - In another case of this embodiment, the barrier layer or other structure at the wafer edge or at the wafer backside can be removed by the edge polishing technology. During the edge polishing treatment, a base slurry may be used for removing the structure. The mentioned base slurry may be a base Silica slurry, and the pH of the slurry is about 7˜12. It should be noted that all the descriptions of the treatment of the
step 260 and the acid/base solution, such as the formulas, the ratio, and other parameters, are employed for the explanation of the embodiment, and this invention is not limited by the above-mentioned descriptions. - After removing weakly adhesive thin film at the edge bevel or at the wafer backside (as the
step 260 inFIG. 2 ), the next semiconductor process can be performed onto the wafer, as thestep 280. In another case of this embodiment, before performing the next semiconductor process, a treatment of wafer cleaning and drying may be employed for removing the residue on the surface of the wafer, not shown inFIG. 2 . - Another preferred embodiment according to this present invention is a method for preventing edge peeling defect.
FIG. 3A to 3C respectively depicts three applications of the method for preventing edge peeling defect according to this embodiment. Referred toFIG. 3A , an interconnect manufacturing usually comprises the steps of forming an interconnect layer on a wafer (as the step 320); annealing (as the step 340); palanarizing the metal interconnect layer and removing the metal at the edge bevel or at the wafer backside by CMP or other treatment (as the step 360); and going to the next semiconductor process (as the step 380). The metal interconnect layer may be consisted of Copper, Aluminum, or other metal materials, and formed by ECP or other well-known technology. - In order to keeping the metal of the metal interconnect layer from diffusing into other structure under the metal interconnect layer, such as the substrate or the dielectric layer, a conformal barrier layer is formed on the wafer before forming the metal interconnect layer. The barrier layer is consisted of TaN, Ta, TiN, TiW, or the like materials. However, the adhesion of the barrier layer to some semiconductor structure, such as bare Si, is not good enough, and thus many defects caused by the peeling of the redundant barrier layer at the wafer edge or at the wafer backside will happen at the following semiconductor processes.
- In order to resolve the above-mentioned peeling defects, a step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside (as the step 400) is performed between the steps of forming the metal interconnect layer (as the step 320) and going to the next semiconductor process (as the step 380) in this embodiment. The above-mentioned step for removing the weakly adhesive thin film at the wafer edge or at the wafer backside is employed for removing the redundant barrier layer or other unwanted structure not covered by the metal interconnect layer (the redundant barrier layer and other unwanted structure are not patterned), wherein the above-mentioned redundant barrier layer or the unwanted structure might be peeling in the following processes. Thus, the peeling defects in the prior art can be efficiently prevented by the design of this embodiment.
- Referring to
FIG. 3A , showing a flowchart of one case of the method for preventing edge defect according to this embodiment, the step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside (as the step 400) can be performed before the annealing step (as the step 340). In the above-mentionedstep 400, the EBR treatment may be employed for removing the redundant barrier layer or the unwanted structure at the wafer edge or at the wafer backside, wherein the barrier layer or the unwanted structure or thin film is not covered by the metal interconnect layer. The EBR treatment may be performed with an acid solution. In one case of this embodiment, the acid solution is an aqueous comprising HNO3 (about 5˜45%) and HF (about 0.1˜5%). - Instead of the EBR technology, the edge polishing technology can be employed in the above-mentioned step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside (as the step 400) to remove the redundant barrier layer or unwanted structure at the wafer edge or at the wafer backside. In the edge polishing treatment, a base slurry may be employed for removing the weakly adhesive thin film at the edge bevel or at the wafer backside. In one case of this embodiment, the base slurry may be a Silica slurry, and the pH of the slurry is about 7˜12.
- In another case of this embodiment, referring to
FIG. 3B , the above-mentioned step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside (the step 400) is performed between the step of annealing (as the step 340) and the step for removing the metal at the edge bevel or at the wafer backside (as the step 360). In this case, the unwanted structure or thin film can be removed by employing the EBR treatment with the acid solution, or by employing the edge polishing treatment with the base slurry. The above-mentioned unwanted structure is the incompletely patterned part of mental interconnect layer at the wafer edge or at the wafer backside, and is not covered by the metal interconnect layer. The above-mentioned unwanted structure may be peeling in the following process. - In still another case of this embodiment, referring to
FIG. 3C , the above-mentionedstep 400 of removing the weakly adhesive thin film at the edge bevel or at the wafer backside can be performed after the step for removing the metal at the edge bevel or at the wafer backside (as the step 360). In this case, the unwanted structure or thin film also can be removed by the EBR treatment with the acid solution, or by the edge polishing with the base slurry. - It should be noted that all the above-mentioned description about the step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside, including the parameters of the acid and the base solutions, such as the formulas, the ratio, and the others, are employed for explanation this embodiment, and this invention should not be limited to the descriptions.
- In the semiconductor manufacture in the prior art, in order to keeping the metal of the metal interconnect layer from diffusing into other structure under the metal interconnect layer, a barrier layer is usually formed on the wafer before forming the metal interconnect layer. After forming the metal interconnect layer, portions of the barrier layer at the wafer edge will not be covered by the metal interconnect layer, and be exposed. Because the adhesion of the barrier layer to some semiconductor structure, such as the bare Si, is not good enough, the exposed barrier layer at the wafer edge will be possibly peeling in the next processes following the interconnect manufacture. The above-mentioned peeling will cause many defects, for example, the decreasing of the yield of the wafer. Particularly, if the peeling is serious, the wafer will become useless. Moreover, the chamber(s) of the semiconductor manufacture will be polluted by the fragments of the above-mentioned peeling. It should be noted that there is still no suitable way for resolving the peeling defects in the prior art, particularly in the Copper interconnect manufacture.
- However, according to this present invention, the above-mentioned peeling defects can be efficiently prevented by introducing a step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside after forming the metal interconnect layer. That is, the above-mentioned step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside is performed between the step of forming the metal interconnect layer and the step of going to the next process. The above-mentioned step of this invention is employed for removing the unwanted structure at the wafer edge or at the wafer backside, wherein the structure or thin film may be peeling in the following processes. The above-mentioned structure or film is not covered by the metal interconnect layer and removed by the design of this invention. Thus, the defects caused by the above-mentioned peeling, such as the decreasing of the yield, the pollution of the chamber(s), and the likes, can be efficiently resolved. Therefore, according to the design of this invention, the yield can be efficiently raised, and the pollution chance of the chamber(s) can be lowered.
- According to the preferred embodiments, this invention discloses a method for preventing edge peeling defect. The above-mentioned method can applied in an interconnect manufacture. In this present invention, the method for preventing edge peeling defect at least comprises the steps of forming a structure comprising a metal interconnect layer on a wafer, and a step for removing the weakly adhesive thin film at the edge bevel or at the wafer backside. The unwanted structure, comprising the barrier layer at the wafer edge, is not covered by the metal interconnect layer, and may be peeling in the following processes. In the above-mentioned step of this invention, the unwanted structure or thin film can be removed by an EBR treatment, or by an edge polishing treatment. Therefore, this present invention can efficiently prevent the defects caused by the peeling of the unwanted structure or thin film in the prior art. According to the design of this invention, the yield of the semiconductor manufacture can be efficiently raised. Preferably, the chamber(s) of the semiconductor manufacture can be kept from the pollution of the peeling fragments in the prior art, and the pollution chance of the chamber(s) can be decreased.
- Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.
Claims (29)
1. A method for preventing edge peeling defect, comprising:
forming a thin film on a wafer;
forming a patterned mental structure on said wafer;
planarizing the surface of said wafer to remove redundant patterned mental structure, wherein a explored part of said thin film is explored after planarizing; and
removing said explored part of said thin film.
2. The method according to claim 1 , wherein said thin film comprises a barrier layer for preventing mental diffusion.
3. The method according to claim 1 , wherein the material of said barrier layer is chosen from the group comprising the following: Ta, TaN, TiN and TiW.
4. The method according to claim 1 , wherein said thin film is formed by physical vapor deposition.
5. The method according to claim 1 , wherein said patterned mental structure comprises an interconnect layer.
6. The method according to claim 5 , wherein said patterned mental structure is chosen from the group comprising the following:
copper and aluminum.
7. The method according to claim 1 , wherein the step for removing said explored part of said thin film comprises etching and chemical mechanical polishing.
8. The method according to claim 1 , wherein said step for removing said explored part of said thin film explored comprises removing the residual of said patterned mental structure by planarizing.
9. The method according to claim 1 , wherein said step for removing said explored part of said thin film is at the edge bevel of said wafer.
10. The method according to claim 1 , wherein said step for removing said explored part of said thin film is at the backside of said wafer.
11. The method according to claim 1 , wherein said step for removing said explored part of said thin film employs an edge bevel removal technology.
12. The method according to claim 11 , wherein said step for removing said explored part of said thin film employs an acid solution.
13. The method according to claim 11 , wherein said step for removing said explored part of said thin film employs an edge polishing technology.
14. The method according to claim 13 , wherein said step for removing said explored part of said thin film employs a base slurry.
15. The method according to claim 13 , wherein said step for removing said explored part of said thin film comprises a treatment of wafer drying.
16. A method for preventing edge peeling defect, comprising:
forming a barrier layer on a wafer;
forming a metal interconnect layer onto said barrier layer, wherein said barrier layer at said wafer edge is not covered by said metal interconnect layer; and
removing said barrier layer not covered by said metal interconnect layer.
annealing; and
planarizing the metal interconnect layer and removing the redundant metal on the wafer.
17. The method according to claim 16 , wherein the material of said barrier layer is Ta.
18. The method according to claim 16 , wherein the material of said barrier layer is TaN.
19. The method according to claim 16 , wherein said metal interconnect layer is a Copper interconnect layer.
20. The method according to claim 16 , wherein said metal interconnect comprises said thin film explored at the wafer backside.
21. The method according to claim 16 , wherein said step for removing said barrier layer not covered by said metal interconnect layer comprises removing said thin film explored at the wafer backside.
22. The method according to claim 16 , wherein said step for removing said barrier layer not covered by said metal interconnect layer comprises removing the incompletely patterned part of said mental interconnect layer upper said barrier layer.
23. The method according to claim 16 , wherein said step for removing said barrier layer not covered by said metal interconnect layer comprises an edge bevel removal treatment.
24. The method according to claim 23 , wherein said step for removing said barrier layer not covered by said metal interconnect layer employs an acid solution.
25. The method according to claim 23 , wherein said step for removing said barrier layer not covered by said metal interconnect layer employs an acid solution comprising nitric acid and hydrofluoric acid.
26. The method according to claim 9 , wherein said step for removing said barrier layer not covered by said metal interconnect layer comprises an edge polishing treatment.
27. The method according to claim 13 , wherein said step for removing said barrier layer not covered by said metal interconnect layer employs a base slurry.
28. The method according to claim 25 , wherein the pH of said base slurry is pH 7˜12.
29. The method according to claim 27 , wherein said step for planarizing the metal interconnect layer and removing the redundant metal on the wafer comprises etching for planarizing and chemical mechanical polishing.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/685,588 US20050085163A1 (en) | 2003-10-16 | 2003-10-16 | Method for preventing edge peeling defect |
US11/331,361 US20060172526A1 (en) | 2003-10-16 | 2006-01-13 | Method for preventing edge peeling defect |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/685,588 US20050085163A1 (en) | 2003-10-16 | 2003-10-16 | Method for preventing edge peeling defect |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/331,361 Continuation-In-Part US20060172526A1 (en) | 2003-10-16 | 2006-01-13 | Method for preventing edge peeling defect |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050085163A1 true US20050085163A1 (en) | 2005-04-21 |
Family
ID=34520639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/685,588 Abandoned US20050085163A1 (en) | 2003-10-16 | 2003-10-16 | Method for preventing edge peeling defect |
Country Status (1)
Country | Link |
---|---|
US (1) | US20050085163A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110159687A1 (en) * | 2009-12-30 | 2011-06-30 | Hae-Jung Lee | Method for fabricating semiconductor device |
US9064770B2 (en) * | 2012-07-17 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for minimizing edge peeling in the manufacturing of BSI chips |
CN105047535A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Method for preventing peeling defect of wafer edges |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6048789A (en) * | 1997-02-27 | 2000-04-11 | Vlsi Technology, Inc. | IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids |
US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
US6309981B1 (en) * | 1999-10-01 | 2001-10-30 | Novellus Systems, Inc. | Edge bevel removal of copper from silicon wafers |
US20040009671A1 (en) * | 1998-03-18 | 2004-01-15 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper substrates |
US6857941B2 (en) * | 2001-06-01 | 2005-02-22 | Applied Materials, Inc. | Multi-phase polishing pad |
-
2003
- 2003-10-16 US US10/685,588 patent/US20050085163A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6048789A (en) * | 1997-02-27 | 2000-04-11 | Vlsi Technology, Inc. | IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids |
US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
US20040009671A1 (en) * | 1998-03-18 | 2004-01-15 | Cabot Microelectronics Corporation | Chemical mechanical polishing slurry useful for copper substrates |
US6309981B1 (en) * | 1999-10-01 | 2001-10-30 | Novellus Systems, Inc. | Edge bevel removal of copper from silicon wafers |
US6857941B2 (en) * | 2001-06-01 | 2005-02-22 | Applied Materials, Inc. | Multi-phase polishing pad |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110159687A1 (en) * | 2009-12-30 | 2011-06-30 | Hae-Jung Lee | Method for fabricating semiconductor device |
US8268726B2 (en) * | 2009-12-30 | 2012-09-18 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
US9064770B2 (en) * | 2012-07-17 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for minimizing edge peeling in the manufacturing of BSI chips |
CN105047535A (en) * | 2015-06-30 | 2015-11-11 | 上海华力微电子有限公司 | Method for preventing peeling defect of wafer edges |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7192878B2 (en) | Method for removing post-etch residue from wafer surface | |
US7259091B2 (en) | Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer | |
US6350694B1 (en) | Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials | |
EP1041614A1 (en) | Plasma cleaning process for openings formed in one or more low dielectric constant insulation layers over copper metallization integrated circuit structures | |
JP2001210630A (en) | Copper oxide film forming method, copper film etching method, semiconductor manufacturing method, semiconductor manufacturing apparatus and the semiconductor device | |
JP2006210921A (en) | Method of forming metal wiring of semiconductor device | |
US7820536B2 (en) | Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer | |
US6171405B1 (en) | Methods of removing contaminants from integrated circuit substrates using cleaning solutions | |
US20090029543A1 (en) | Cleaning process for microelectronic dielectric and metal structures | |
US6693040B2 (en) | Method for cleaning the contact area of a metal line | |
US20060266383A1 (en) | Systems and methods for removing wafer edge residue and debris using a wafer clean solution | |
US7001641B2 (en) | Seed layer treatment | |
JP2003023072A (en) | Manufacturing method for semiconductor device, and manufacturing apparatus for the semiconductor device | |
US20050085163A1 (en) | Method for preventing edge peeling defect | |
US20060172526A1 (en) | Method for preventing edge peeling defect | |
KR20070042887A (en) | Method for forming feature definitions | |
US7368383B2 (en) | Hillock reduction in copper films | |
CN116798952B (en) | Method for manufacturing semiconductor device and semiconductor device | |
JP2001176872A (en) | Method for manufacturing semiconductor device | |
US7820544B2 (en) | Method for forming metal wiring of semiconductor device and a semiconductor device manufactured by the same | |
JP2008041977A (en) | Manufacturing method of semiconductor circuit device | |
JP2991176B2 (en) | Method for manufacturing semiconductor device | |
KR100272311B1 (en) | Semiconductor device making method | |
US20100167530A1 (en) | Method for forming metal line of semiconductor device | |
US6183819B1 (en) | Method for processing a poly defect |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, CHIA-LIN;LEE, SHU-HSIEN;TSAI, CHIEN-CHIEN;AND OTHERS;REEL/FRAME:014613/0884 Effective date: 20031007 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |