KR100272311B1 - Semiconductor device making method - Google Patents
Semiconductor device making method Download PDFInfo
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- KR100272311B1 KR100272311B1 KR1019980053007A KR19980053007A KR100272311B1 KR 100272311 B1 KR100272311 B1 KR 100272311B1 KR 1019980053007 A KR1019980053007 A KR 1019980053007A KR 19980053007 A KR19980053007 A KR 19980053007A KR 100272311 B1 KR100272311 B1 KR 100272311B1
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004140 cleaning Methods 0.000 claims abstract description 38
- 239000007789 gas Substances 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 23
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000004381 surface treatment Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000003870 refractory metal Substances 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 239000000126 substance Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 239000000356 contaminant Substances 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- VJDVOZLYDLHLSM-UHFFFAOYSA-N diethylazanide;titanium(4+) Chemical group [Ti+4].CC[N-]CC.CC[N-]CC.CC[N-]CC.CC[N-]CC VJDVOZLYDLHLSM-UHFFFAOYSA-N 0.000 description 1
- 238000005108 dry cleaning Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
반도체 소자 제조공정중에 발생한 불순물을 사전 제거함으로써, 형성되는 막질의 특성을 개선시킬 수 있는 반도체 소자 제조방법에 대해 개시한다. 본 발명에 의하면, 반도체 기판 상에 배선박막을 형성하기 전에, 오존에 의한 표면처리 공정, 불화물 기체 플라즈마를 이용한 세정 공정을 수행한 후에 배선박막을 증착시킨다. 이에 따라, 사전 처리에 의해 형성되는 막질의 특성을 개선할 수 있고, 표면처리 공정과 세정 공정 및 박막형성 공정이 일괄적으로 한 반응기 또는 저산소 분위기에서 다른 반응기로 이동하여 처리되므로 제품의 수율과 신뢰성을 향상시킬 수 있다는 장점이 있다.Disclosed is a method of manufacturing a semiconductor device capable of improving characteristics of a film quality formed by removing impurities previously generated during a semiconductor device manufacturing process. According to the present invention, before forming the wiring thin film on the semiconductor substrate, the wiring thin film is deposited after performing the surface treatment process by ozone and the cleaning process using fluoride gas plasma. Accordingly, the quality of the film formed by the pretreatment can be improved, and the surface treatment process, the cleaning process, and the thin film formation process are processed in one reactor or in a low oxygen atmosphere, and then processed in a different reactor. There is an advantage that can be improved.
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 배선박막 증착전에 오존을 사용하여 반도체 기판 표면상의 불순물을 제거함으로써 형성되는 막질의 특성을 개선시킬 수 있는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the characteristics of a film formed by removing impurities on the surface of a semiconductor substrate using ozone prior to wiring thin film deposition.
최근, 반도체 소자의 회로패턴이 계속 미세화될 뿐 아니라, 고밀도, 고집적화됨에 따라 유기물, 다중합체 부산물 및 오염입자 등으로 대표되는 오염(contamination)이 제품의 수율과 신뢰성에 큰 영향을 미치게 되었다. 이 때문에 반도체 소자의 제조에 있어서 초 LSI공정에서 청정화는 매우 중요한 요인이다.In recent years, as circuit patterns of semiconductor devices continue to be miniaturized, as high density and high integration, contamination represented by organic materials, polypolymer by-products, and contaminant particles has a great influence on yield and reliability of products. For this reason, in the manufacture of semiconductor devices, cleaning is very important factor in the ultra LSI process.
공정중에 발생하는 이러한 오염물질을 제거하기 위해서, 종래에는 주로 화학적 습식 세정을 행하였다. 그 예로서, 실리콘 웨이퍼나 형성된 막상의 표면에 흡착된 오염입자를 제거하는 세정방법으로 SC1(NH4OH + H2O2+ H2O의 혼합액)과 불산(HF)용액을 반복해서 사용하여 세정하는 방법 등이 사용되었으나, 최근에는 건식 세정방법도 많이 이용되고 있다.In order to remove such contaminants generated during the process, conventionally, chemical wet cleaning is mainly performed. As an example, SC1 (a mixture of NH 4 OH + H 2 O 2 + H 2 O) and hydrofluoric acid (HF) solution are repeatedly used as a cleaning method to remove contaminated particles adsorbed on the surface of a silicon wafer or the formed film. A washing method or the like has been used, but recently, a dry cleaning method is also widely used.
한편, 각 소자간 전기적 신호를 전달하는 금속배선의 측면에서는, 미세화에 따라 단면적 감소에 의한 배선 저항 증가 및 배선 간격 축소에 의한 기생 캐퍼시턴스가 증가하게 된다. 이러한 저항 증가 및 캐퍼시터 증가는 RC 지연시간을 유발시켜 향후의 로직(logic) 공정이 추구하는 고속 반도체소자를 제조하는데 장벽요인이 될 것이다. 고속 반도체 소자를 제조하기 위하여, 금속 배선간 기생 캐퍼시터를 줄이는 목적으로, 저 유전율 절연막을 사용하거나 저 저항 금속 배선 사용이 필요하게 되는데 특히, 저 저항 금속 배선 공정 기술은 아직 공정 및 장비상의 개선의 여지가 많아 고속 반도체 제조기술 수립에 중요한 열쇠로서 많은 연구가 진행되고 있다.On the other hand, in terms of metal wirings that transmit electrical signals between the devices, as the microstructure becomes smaller, the parasitic capacitance increases due to an increase in wiring resistance due to a decrease in cross-sectional area and a reduction in wiring spacing. The increase in resistance and the increase in capacitor will cause RC delay, which will be a barrier to manufacturing high-speed semiconductor devices pursued by future logic processes. In order to reduce parasitic capacitors between metal wirings, a low dielectric insulating film or a low resistance metal wiring is required to manufacture a high-speed semiconductor device. In particular, the low resistance metal wiring process technology still has room for improvement in process and equipment. Many studies have been conducted as an important key for establishing high-speed semiconductor manufacturing technology.
종래의 금속 배선 공정은 알루미늄(Al) 등의 금속을 PVD(Physical Vapor Deposition)의 방법으로 형성하는 것이 일반적이나 높은 종횡비(aspect ratio)를 갖는 콘택 홀 또는 비아에서의 단차피복성(step coverage) 문제를 해결할 수 없다. 따라서, 알루미늄 리플로우(reflow) 또는 알루미늄 CVD(Chemical Vapor Deposition) 등의 제조 공정이 대두되었는데, 알루미늄 리플로우 공정의 경우는 종횡비가 3.0 이상의 콘택 홀을 채우기에는 역부족이다. 따라서 알루미늄 CVD 공정이 향후 유력한 대안으로 대두되고 있다. 또한 금속 배선의 선폭이 좁아짐에 따라 알루미늄 자체의 고유 저항으로는 RC 지연의 개선이 어려우므로 고유저항이 알루미늄에 비해 2/3정도로 낮은 구리(Cu) CVD가 최근 본격 연구되고 있다. 이러한 알루미늄이나 구리 CVD의 경우는 막이 형성될 하부층에 대한 의존성이 심하며, 핵 생성 밀도가 낮은 반면 일단 형성된 핵은 빠르게 성장되므로 콘택이나 비아의 좁은 구멍을 메꾸지 못하고 보이드(void)를 형성하는 등 오버-행(over-hang)이 발생하고, 전면 증착시 표면이 거칠어 반사도가 나쁘고 단차피복성이 열악한 문제가 있다. 즉, 알루미늄 혹은 구리의 표면 거칠기의 증가 및 반사도의 감소 그리고 이로 인한 노광 작업시 정렬(align) 및 오버레이(overlay) 측정의 불량, 그리고 콘택에서 돌출된 알루미늄 결정립이 서로 브리지(bridge)되면서 콘택을 막게 됨에 따라 보이드를 형성하는 문제 등이 발생한다. CVD-알루미늄의 표면 거칠기의 증가와 콘택의 측벽에서 발생하는 브리지 형성에 의한 보이드의 형성 등의 문제로 인해서 기존의 방법에서는 알루미늄 혹은 구리 CVD를 매립금속(filling metal)으로 사용하지 못하고 알루미늄 혹은 구리를 씨앗층(seed layer)으로만 사용한 후 스퍼터링방법에 의한 PVD-알루미늄 혹은 PVD-구리로 비아나 콘택을 메꾸는 CVD-PVD 공정을 사용한다.Conventional metal wiring processes generally use a method of physical vapor deposition (PVD) to form a metal such as aluminum (Al), but there is a step coverage problem in contact holes or vias having a high aspect ratio. Can not solve. Therefore, a manufacturing process such as aluminum reflow or aluminum chemical vapor deposition (CVD) has emerged. In the case of the aluminum reflow process, the aspect ratio is insufficient to fill contact holes of 3.0 or more. Therefore, aluminum CVD process is emerging as a viable alternative in the future. In addition, as the line width of the metal wiring is narrowed, it is difficult to improve the RC delay with the resistivity of aluminum itself, and thus, copper CVD (Cu) CVD, which has a resistivity of about 2/3 lower than that of aluminum, has recently been studied. In the case of aluminum or copper CVD, the dependence on the underlying layer on which the film is to be formed is severe, and the nucleation density is low while the nucleus formed once grows rapidly, thus forming voids without filling the narrow holes of contacts or vias. Overhang occurs and the surface is rough during surface deposition, resulting in poor reflectivity and poor step coverage. That is, an increase in surface roughness and a decrease in reflectivity of aluminum or copper, and thus a result of poor alignment and overlay measurement during exposure, and aluminum grains protruding from the contact can be bridged to prevent contact. As a result, problems such as forming voids occur. Due to problems such as the increase in the surface roughness of CVD-aluminum and the formation of voids due to the formation of bridges on the sidewalls of the contacts, conventional methods do not use aluminum or copper CVD as a filling metal, The CVD-PVD process is used to fill vias or contacts with PVD-aluminum or PVD-copper by the sputtering method after use only as a seed layer.
이러한 CVD와 PVD 집적 장치는 CVD 반응과 PVD 반응의 공정 영역과 장치 제어 영역이 상이하여 격리수단에 의해 오염이 되지 않도록 장치를 구성 제어하여야 한다. 이 밖에 핵 생성 밀도를 증가시키기 위한 증착전 표면처리 방법에 대한 연구와 전구체 개발 등이 이루어지고 있으나 아직도 표면 거칠기와 낮은 증착속도 등 개선의 여지가 많고, 그 자체 해결점이 되지 못하고 있는 실정이다.Such CVD and PVD integrated devices must be configured and controlled so that the process area and the device control area of the CVD reaction and the PVD reaction are different from each other so that they are not contaminated by the isolation means. In addition, research on the surface treatment method before deposition to increase the nucleation density and development of precursors have been made, but there is still a lot of room for improvement such as surface roughness and low deposition rate, and it is not a solution in itself.
상기한 바와 같이, 반도체 소자의 성능은 자연산화막 등의 계면물질, 불순물, 식각 잔류물 등이 큰 악영향을 끼치므로 이를 제거하기 위하여, 실리콘 웨이퍼를 습식조(wet bath)에서 세정하고 증착 장치에 장착한 후 아르곤(Ar) 등을 이용하여 스퍼터 에치(sputter etch)하고 있다. 이 경우 콘택에서는 콘택 바닥의 실리콘 접합부도 식각이 되어, 얕은 접합의 실리콘 손실로 인한 정션 스파이킹(junction spiking)의 문제가 심각해 진다. 한편, 자연산화막 등의 계면물질, 불순물, 식각 잔류물 등을 제거하기 위해 담금 등의 습식 화학 세정시에는 습식조로부터 반도체 기판이 불순물과 입자에 오염되기 쉬울 뿐아니라, 점점더 종횡비가 커지므로 좁은 콘택이나 비아 등의 깊은 바닥에 존재하는 불순물(에치후의 유기물이나 자연산화막 등)까지 효과적으로 제거할 수 없게 된다. 즉, 습식 세정 공정에서는, 산화막이 완전히 제거되지 않을 뿐만 아니라 불순물에 의해 오염되는 문제점이 있다.As described above, since the performance of the semiconductor device has a great adverse effect on interfacial materials such as a natural oxide film, impurities, and etching residues, the silicon wafer is cleaned in a wet bath and mounted on a deposition apparatus in order to remove it. After the sputter etch using argon (Ar) or the like. In this case, the silicon junction at the bottom of the contact is also etched at the contact, which causes a serious problem of junction spiking due to the silicon loss of the shallow junction. On the other hand, when wet chemical cleaning such as immersion to remove interfacial substances such as natural oxide films, impurities, and etching residues, the semiconductor substrate is not only easily contaminated with impurities and particles from the wet bath, but also has a narrower aspect ratio. Impurities (such as organic substances or natural oxide films after etching) that exist in deep bottoms such as contacts and vias cannot be effectively removed. That is, in the wet cleaning process, not only the oxide film is not completely removed but also has a problem of being contaminated by impurities.
또한, 알루미늄이나 구리 등을 CVD 증착할 때, 낮은 핵 생성 밀도에서 급속히 확산 제어영역(mass controlled regime)으로 반응이 진행되어 표면이 거칠고 콘택이나 비아의 입구가 막히는 문제가 있다.In addition, when CVD deposition of aluminum, copper, or the like, the reaction proceeds rapidly to a mass controlled regime at a low nucleation density, resulting in a rough surface and clogging of contacts or vias.
따라서, 본 발명의 기술적 과제는 반도체 기판 상에 배선박막을 형성함에 있어 사전 표면처리를 행함으로써 형성되는 막질의 특성을 향상시킬 수 있는 반도체 소자 제조방법을 제공하는데 있다.Accordingly, the technical problem of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the characteristics of the film formed by performing a pre-surface treatment in forming a wiring thin film on a semiconductor substrate.
본 발명의 다른 기술적 과제는 배선박막의 하부층에 대한 손상을 유발하지 않는 반도체 소자 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device that does not cause damage to the lower layer of the wiring thin film.
도 1은 본 발명의 방법을 실시하기 위한 반도체 소자 제조장치를 나타낸 개략도,1 is a schematic view showing a semiconductor device manufacturing apparatus for carrying out the method of the present invention;
도 2는 본 발명의 일 실시예에 따른 배선박막 증착공정의 순서를 나타낸 흐름도이다.2 is a flowchart showing a procedure of a wiring thin film deposition process according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 반응챔버 20 : 세정챔버10: reaction chamber 20: cleaning chamber
30 : 중앙챔버 40 : 오존발생기30: central chamber 40: ozone generator
상기한 기술적 과제들을 달성하기 위한 본 발명에 의한 반도체 소자 제조방법은, 적어도 하나 이상의 반응기 모듈을 가지는 반도체 공정 처리장치에서 적용된다. 그 반도체 소자를 제조하는 방법은, 상기 처리장치의 반응기 내에, 소정 공정을 거친 반도체 기판을 위치시키는 단계와; 상기 반도체 기판에 오존가스를 이용하여 표면처리하는 단계와; 상기 표면처리 단계에서 형성된 산화막을 불화물 기체 플라즈마로 세정하는 단계와; 상기 세정이 행해진 반도체 기판에 화학기상 증착공정을 적용하여 배선박막을 형성시키는 단계를 포함하는 것을 특징으로 한다.The semiconductor device manufacturing method according to the present invention for achieving the above technical problem is applied in a semiconductor processing apparatus having at least one reactor module. The method of manufacturing the semiconductor device comprises the steps of: placing a semiconductor substrate undergoing a predetermined process in a reactor of the processing apparatus; Surface-treating the semiconductor substrate using ozone gas; Cleaning the oxide film formed in the surface treatment step with a fluoride gas plasma; And applying a chemical vapor deposition process to the cleaned semiconductor substrate to form a wiring thin film.
이 때, 상기 표면처리 단계에서 오존가스 자체를 이용할 수 있으나, 더 바람직하기로는 오존가스에 플라즈마를 적용한 오존 플라즈마를 이용할 수 있다.At this time, ozone gas itself may be used in the surface treatment step, but more preferably, ozone plasma may be used in which plasma is applied to ozone gas.
또한, 상기 세정 단계에서 사용되는 불화물 기체는 SF6, NF3, ClF3으로 구성된 기체군으로부터 선택된 어느 하나인 것이 바람직하다.In addition, the fluoride gas used in the washing step is preferably any one selected from the group of gases consisting of SF 6 , NF 3 , ClF 3 .
한편, 상기 배선박막 형성 단계에서 형성시키는 배선박막은; 알루미늄, 텅스텐, 구리, 금, 백금, 은으로 구성된 금속군으로부터 선택된 어느 하나의 재질로 이루어진 것이 바람직하다.On the other hand, the wiring thin film formed in the wiring thin film forming step; It is preferably made of any one material selected from the group of metals consisting of aluminum, tungsten, copper, gold, platinum and silver.
또한, 상기 배선박막 형성 단계에서, 내화물금속 함유화합물 기체를 더 첨가하여 증착하는 것도 좋다. 이 때, 상기의 내화물금속 함유화합물 기체는; TiCl4, TDMAT, TDEAT로 구성된 기체군으로부터 선택된 어느 하나인 것이 바람직하다.In the wiring thin film forming step, the refractory metal-containing compound gas may be further added and deposited. At this time, the refractory metal-containing compound gas is; It is preferably one selected from the group of gases consisting of TiCl 4 , TDMAT, and TDEAT.
그리고, 상기 배선박막을 형성하는 단계전에 표면처리 단계를 더 포함하며, 상기 표면처리 단계에서는 수소 함유기체 플라즈마 또는 내화물금속 함유기체 플라즈마를 이용하는 것이 바람직하다. 이 때, 상기 수소 및 내화물금속 함유기체는; H2, SiH4, Si2H6, B2H6, PH3, GeH4, TiCl4, TDMAT, TDEAT로 구성된 기체군으로부터 선택된 어느 하나인 것이 더욱 바람직하다. 여기서, TDMAT는 테트라키스(디메틸아미노)티타늄으로서 그 화학식은 Ti[N(CH3)2]4이고, TDEAT는 테트라키스(디에틸아미노)티타늄으로서 그 화학식은 Ti[N(C2H5)2]4이다.The method may further include a surface treatment step before forming the wiring thin film. In the surface treatment step, it is preferable to use a hydrogen-containing gas plasma or a refractory metal-containing gas plasma. At this time, the hydrogen and refractory metal-containing gas; More preferably, it is any one selected from the group of gases consisting of H 2 , SiH 4 , Si 2 H 6 , B 2 H 6 , PH 3 , GeH 4 , TiCl 4 , TDMAT, TDEAT. Wherein TDMAT is tetrakis (dimethylamino) titanium and its chemical formula is Ti [N (CH 3 ) 2 ] 4 , TDEAT is tetrakis (diethylamino) titanium and its chemical formula is Ti [N (C 2 H 5 ) 2 ] 4 .
한편, 적어도 하나 이상의 반응기 모듈을 가지는 반도체 공정 처리장치에서 반도체 소자를 제조하는 방법에 있어서, 상기 처리장치의 반응기 내에, 소정 공정을 거친 반도체 기판을 위치시키는 단계와; 상기 반도체 기판을 오존가스를 사용하여 표면처리하는 단계와; 상기 표면처리 단계에서 형성된 산화막을 불화물 기체 플라즈마로 세정하는 단계와; 상기 세정이 행해진 반도체 기판 상에 배선박막을 형성시키는 단계를 포함하되, 상기 표면처리 단계, 세정 단계, 배선박막 형성 단계를 동일 반응기에서 진행하거나 저산소 분위기를 통해 서로 다른 반응기로 이동하여 진행하는 것을 특징으로 한다.On the other hand, a method for manufacturing a semiconductor device in a semiconductor processing apparatus having at least one reactor module, comprising the steps of: positioning a semiconductor substrate having undergone a predetermined process in the reactor of the processing apparatus; Surface-treating the semiconductor substrate using ozone gas; Cleaning the oxide film formed in the surface treatment step with a fluoride gas plasma; Forming a wiring thin film on the semiconductor substrate on which the cleaning is performed, wherein the surface treatment step, the cleaning step, and the wiring thin film forming step are performed in the same reactor or are moved to different reactors through a low oxygen atmosphere. It is done.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.
도 1은 반도체 소자 제조장치를 나타낸 개략도이다. 도 1을 참조하면, 소정의 공정을 수행한 실리콘 웨이퍼를 외부와 격리시켜 진공상태에서 일부 또는 전체 공정(물리화학증착, 화학기상증착, 전기도금, 화학물리연마, 식각, 에싱)을 수행하는 반응챔버(10)가 다수 구비되어 있다.1 is a schematic view showing a semiconductor device manufacturing apparatus. Referring to FIG. 1, a silicon wafer having a predetermined process is isolated from the outside to perform a partial or entire process (physical chemical vapor deposition, chemical vapor deposition, electroplating, chemical physical polishing, etching, ashing) in a vacuum state. The chamber 10 is provided with many.
반응챔버(10)에서 반응을 수행한 전·후에, 그 공정 수행결과에서 생성된 오염물질을 세정하기 위한 세정챔버(20)가 반응챔버(10)와 인접하여 설치되어 있다.Before and after the reaction is carried out in the reaction chamber 10, a cleaning chamber 20 for cleaning the contaminants generated in the result of the process is provided adjacent to the reaction chamber 10.
본 실시예에서는 반응챔버(10)와 세정챔버(20)를 각각 3개와 1개로 구성하였으나, 반응챔버(10)와 세정챔버(20)의 개수는 공정처리의 속도를 증대시키기 위해 임의로 조절하여 최대화할 수 있다. 또한, 반응챔버(10)와 세정챔버(20)는 효율적으로 공정을 수행하기 위해 자유롭게 배치할 수 있다.In this embodiment, the reaction chamber 10 and the cleaning chamber 20 are composed of three and one, respectively, but the number of the reaction chamber 10 and the cleaning chamber 20 is arbitrarily adjusted and maximized to increase the speed of processing. can do. In addition, the reaction chamber 10 and the cleaning chamber 20 may be freely arranged in order to perform the process efficiently.
또한, 본 실시예에서는 반응챔버(10)와 세정챔버(20)를 각각 구비시켰으나, 일부 또는 전체 공정과 그 각각에 대한 세정 공정을 하나의 챔버에서 모두 수행하기 위해 반응챔버(10)와 세정챔버(20)를 집적화한 하나의 집적챔버로 시스템을 구성할 수도 있다. 이러한 직접챔버는 단계별 공정 수행을 위해 다수 구비되는 것이 바람직하다.In addition, in the present embodiment, the reaction chamber 10 and the cleaning chamber 20 are provided, respectively, but the reaction chamber 10 and the cleaning chamber are performed to perform all or part of the process and the cleaning process for each of them in one chamber. The system may be constituted by one integrated chamber in which 20 is integrated. Such a direct chamber is preferably provided with a plurality for the step-by-step process.
이 반응챔버(10)와 세정챔버(20)는 진공상태를 유지하기 위해 외부와 격리되며, 실리콘 웨이퍼가 저산소 분위기에서 이동하기 위해 공동 공간을 형성시킨 중앙챔버(30)를 반응챔버(10)와 세정챔버(20)의 사이에 위치시키고 있다. 또한, 반응을 수행하기 위해 실리콘 웨이퍼를 대기중에서 반응챔버(10)로 들여보내는 반입용 로드락(Load Lock)챔버(31)와 반응이 완료된 실리콘 웨이퍼를 대기중으로 내보내는 반출용 로드락챔버(32)가 반응챔버(10)와 세정챔버(20) 사이에 마련되어 있다.The reaction chamber 10 and the cleaning chamber 20 are isolated from the outside in order to maintain a vacuum state, and the central chamber 30 in which the silicon wafer is formed to move in a low oxygen atmosphere is formed with the reaction chamber 10. It is located between the cleaning chambers 20. In addition, a load lock chamber 31 for introducing a silicon wafer into the reaction chamber 10 in the air to perform the reaction and a load lock chamber 32 for ejecting the silicon wafer after the reaction is completed into the atmosphere Is provided between the reaction chamber 10 and the cleaning chamber 20.
세정챔버(20) 내에는 오존을 발생시키는 오존발생기(O3generator, 40)가 설치되어 있다. 본 실시예에서는 오존 세정을 효과적으로 수행하기 위해 오존발생기(40)를 포함하는 별도의 세정챔버(20)를 마련하였으나, 이 오존발생기(40)는 세정챔버(20) 외부에 위치시켜 공급라인을 통해 세정챔버(20)로 오존을 공급할 수도 있다.In the cleaning chamber 20 has an ozone generator (O 3 generator, 40) for generating the ozone is provided. In this embodiment, in order to effectively perform the ozone cleaning, a separate cleaning chamber 20 including the ozone generator 40 is provided, but the ozone generator 40 is located outside the cleaning chamber 20 through a supply line. Ozone may be supplied to the cleaning chamber 20.
상기와 같이 이루어진 반도체 소자 제조장치를 이용한 반도체 소자 제조방법을 도 2를 참조하여 설명하면 다음과 같다. 도 2는 본 발명의 일실시예로서, 반도체 소자 제조방법에서 배선박막을 증착할 경우의 공정순서를 나타낸 흐름도이다.A semiconductor device manufacturing method using the semiconductor device manufacturing apparatus made as described above will be described with reference to FIG. 2. FIG. 2 is a flowchart illustrating a process sequence when the wiring thin film is deposited in the method of manufacturing a semiconductor device according to one embodiment of the present invention.
도 2를 참조하면, 먼저, 소정 공정을 거친 실리콘 웨이퍼가 반입용 로드락챔버(31)를 통해 반입되면 중앙챔버(30)를 거쳐 세정챔버(20)로 저산소 분위기에서 이송시킨다. 이후, 오존(O3) 기체 플라즈마를 세정챔버(20)로 공급하여 실리콘 웨이퍼 표면을 처리한다(S1). 이 때, 오존이 표면에 잔류물, 특히 유기물을 제거하는 효과가 있으며 일부 불순물은 산화되기도 한다.Referring to FIG. 2, first, when a silicon wafer that has been subjected to a predetermined process is loaded through the load lock chamber 31 for carrying in, the silicon wafer is transferred to the cleaning chamber 20 through the central chamber 30 in a low oxygen atmosphere. Thereafter, ozone (O 3 ) gas plasma is supplied to the cleaning chamber 20 to process the silicon wafer surface (S1). At this time, ozone has the effect of removing residues, especially organic matter, from the surface and some impurities are oxidized.
상기 실리콘 웨이퍼의 오존 플라즈마 처리 단계(S1)에서, 발생할 수 있는 산화막이나 표면에 존재하는 자연산화막을 제거하기 위해 세정공정이 행해진다(S2). 상기 산화막의 제거를 위해 SF6, NF3, ClF3으로 구성된 기체군으로부터 선택된 어느 하나를 이용하여 세정한다. 또한, 산화막 세정공정시에는 상기한 SF6, NF3, ClF3와 Ar, H2, He를 혼합한 혼합기체를 사용하여 실행할 수도 있다. 본 실시예에서는 SF6를 사용하였다.In the ozone plasma treatment step (S1) of the silicon wafer, a cleaning process is performed to remove the oxide film or the natural oxide film present on the surface (S2). In order to remove the oxide film, it is cleaned using any one selected from a gas group consisting of SF 6 , NF 3 , and ClF 3 . In the oxide film cleaning step, the above-mentioned SF 6 , NF 3 , ClF 3 and Ar, H 2 , He may be mixed using a mixed gas. In this example, SF 6 was used.
상기 실리콘 웨이퍼 표면의 처리 및 산화막 세정이 완료되면 수소 함유기체 플라즈마 또는 내화물금속 함유기체 플라즈마를 이용하여 실리콘 웨이퍼의 표면처리를 한 번 더 수행한다(S3). 상기 수소 함유기체 플라즈마로는 구체적으로 H2, SiH4, Si2H6, B2H6, PH3, GeH4등이 사용되고, 상기 내화물금속 함유기체 플라즈마로는 구체적으로 TiCl4, TDMAT, TDEAT 등이 사용된다. 본 실시예에서는 H2를 사용하였다.When the silicon wafer surface treatment and oxide film cleaning are completed, the silicon wafer surface treatment is performed once more using hydrogen-containing gas plasma or refractory metal-containing gas plasma (S3). Specifically, the hydrogen-containing gas plasma may be H 2 , SiH 4 , Si 2 H 6 , B 2 H 6 , PH 3 , GeH 4 , and the like, and the refractory metal-containing gas plasma may specifically include TiCl 4 , TDMAT, and TDEAT. Etc. are used. In this example, H 2 was used.
그 다음, 배선박막을 증착한다(S4). 상기 배선 재료로서, 알루미늄, 텅스텐, 구리, 금, 백금, 은으로 구성된 금속군으로부터 선택된 어느 하나를 사용하여 배선박막을 증착한다. 그리고, TiCl4, TDMAT, TDEAT로 구성된 기체군으로부터 선택된 어느 하나의 내화물금속 함유화합물 기체를 첨가하여 상기 배선박막을 형성시킨다.Next, a wiring thin film is deposited (S4). As the wiring material, a wiring thin film is deposited using any one selected from the group of metals consisting of aluminum, tungsten, copper, gold, platinum and silver. Then, any one refractory metal-containing compound gas selected from the group consisting of TiCl 4 , TDMAT, and TDEAT is added to form the wiring thin film.
본 실시예에서는 배선박막 증착전에 오존 플라즈마를 이용하여 실리콘 웨이퍼 표면을 처리하여 불순물을 제거하였으나, 이러한 불순물 제거방법은 반도체 소자 제조를 위한 모든 공정에 적용할 수도 있다.In the present exemplary embodiment, impurities are removed by treating the surface of the silicon wafer using ozone plasma prior to the deposition of the wiring thin film. However, the method of removing impurities may be applied to all processes for manufacturing a semiconductor device.
상술한 바와 같이, 본 발명에 따른 반도체 소자 제조방법에 의하면, 하부층에 대한 손상 없이 배선박막을 형성할 수 있다. 또한, 형성되는 배선박막의 막질도 개선되므로 우수한 전기적 특성을 갖는 반도체 소자를 제조할 수 있다.As described above, according to the semiconductor device manufacturing method according to the present invention, it is possible to form a wiring thin film without damaging the lower layer. In addition, since the film quality of the formed wiring thin film is also improved, a semiconductor device having excellent electrical characteristics can be manufactured.
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