JP2740675B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A semiconductor device having a substrate formed by a laminating method can be manufactured at low cost and has an object of improving the manufacturing yield, and has an LTV of 2 μm / 1.5 cm ^2. And a wafer having a maximum slope angle of the depression of 0.4 ° or less.

[Industrial Application Field] The present invention relates to a semiconductor device having a substrate formed using a bonding method.

For example, after oxidizing two silicon wafers, they are bonded by annealing, and one side is polished to expose one silicon wafer.
r) is known, but in general, a slight dent exists on the surface of the silicon wafer, and that portion remains as an unbonded area at the time of lamination, and during subsequent processes such as patterning and etching. May cause peeling. Therefore, in order to produce a semiconductor device having a good production yield, an appropriate standard for the flatness of a wafer is required.

[Conventional technology]

FIG. 2 shows a manufacturing process diagram of a general SOI. Figure (A)
In the silicon oxide film 3 ₁ around the two silicon wafers 1 and 2 respectively oxidized to, 3 ₂ is formed, as shown in FIG. (B), is laminated two wafers 1 and 2. Thereafter, one side is polished along the broken line to expose one of the wafers 1 to obtain the SOI shown in FIG. In this case, generally, a slight dent is present on the surface of the silicon wafer, and if a dent 4 is present in the silicon wafer 2, for example, as shown in FIG. Also remains.
This unbonded area 5 causes peeling during subsequent processing,
Not only this portion becomes defective, but also the peeled silicon pieces adhere to other regions, and that region also becomes defective.

FIG. 4 is a diagram showing the relationship between the number of depressions and the frequency of peeling of a size of 1 μm or more. In the figure, the white portions indicate the characteristics when the pulse voltage is not used for bonding, and the portions where the white portions and the hatched portions are added indicate the characteristics when the pulse voltage is used for the bonding. The diameter of the depression is 2 μm to 10 μm.
μm. As is clear from the figure, the peeling frequency increases exponentially from a certain number of depressions. This is because the large number of depressions means that the slope is steep (the slope angle θ shown in FIG. 5 is small). It is considered that there are many depressions and the diameter is large. That is, the reason why the frequency of peeling suddenly increases from a certain point of the number of depressions is that the shape of the depressions becomes worse. Accordingly, in FIG. 4, the number of depressions is shown on the horizontal axis with respect to the peeling frequency, but the peeling frequency is also a function of the size (diameter) of the depression and the slope angle.

Therefore, current wafer standards define "there are no pits visible to the naked eye", and semiconductor devices currently manufactured generally use wafers based on this standard. When a substrate is manufactured, reliable bonding cannot be performed with such a standard. For this reason, at present, the standard of the wafer is strict or the production yield is lowered.

[Problems to be solved by the invention]

That is, when the bonding method is used, the LTV (local thichness value) is 0.5 based on the strict wafer standard.
μm / 1.5cm ² (The height difference between the dents in 1.5cm ² is 0.
5 μm)
This is a specially processed ultra-high flatness wafer. Such an ultra-high flatness wafer is not a device used in a general wafer manufacturing process, but uses a device specially managed as a dedicated machine, so that there is a problem that the cost is high and mass production is not possible. Further, even if an attempt is made to obtain a wafer based on the stricter wafer standard using an apparatus used in a general wafer manufacturing process, it can be obtained only at a very low ratio of about one in twenty. Not only does it cost extra,
There is a problem that dust easily adheres at the time of inspection and the production yield is reduced.

An object of the present invention is to provide a semiconductor device that can be manufactured at low cost and that can improve the manufacturing yield.

[Means for solving the problem]

The present invention uses a wafer having an LTV of 2 μm / 1.5 cm ² or less and a maximum slope angle of the depression of 0.4 ° or less.

[Action]

The excess wafer standard defined conventionally is relaxed as much as possible, and an appropriate standard is set for a wafer applied to the bonding method. As is clear from FIG. 1 (A), when the flatness of the wafer is 2 μm / cm or more, the yield is extremely deteriorated in the laminating process. On the other hand, as is clear from FIG. If the slope angle is 0.4 or more (slope of the slope is steep), the frequency of peeling becomes extremely high, and even if the pit has a small diameter, the rate of peeling is large if the slope is steep.

In the present invention, since the LTV is 2 μm / 1.5 cm ² or less, and the maximum slope angle of the depression is 0.4 or less, a special machine is used without specially machined ultra-high flatness wafers. A low-cost, high-yield substrate can be obtained.

〔Example〕

The above-mentioned specially processed ultra-high flatness wafer has an LTV of 0.5μ.
This is a wafer having no depression at m / 1.5 cm ² or less, but a substrate with a sufficiently high yield can be obtained even with a wafer that does not meet such a strict standard. FIG. 1A is a diagram showing the relationship between the SOI substrate yield and the flatness, and the SOI is created by the method described below. The flatness indicates the ratio of the height difference (μm) for each 1 cm of the wafer, and corresponds to LTV.

As a first example, after oxidizing two silicon wafers, they are superimposed, placed on a heater and heated to 500 ° C. to 800 ° C., and a pulse voltage of 100 V to 500 V is applied in this state (in this case, 1 torr) Vacuum may be used). Next, the temperature of the heater is lowered to take out the wafer, and the wafer is put into a furnace and annealed at a temperature of 1000 ° C. to 1250 ° C. for 30 minutes or more. After annealing, one side is polished to a predetermined silicon thickness. In this case, silicon wafers having various flatnesses are prepared as silicon wafers before bonding, and the yield obtained when a pulse voltage is applied and not applied at the time of bonding is the first.
FIG. The solid line is a method using a pulse voltage, and the broken line is a method using no pulse voltage.

As is clear from FIG. 1 (A), especially when bonding is performed using a pulse voltage, a yield of nearly 100% can be obtained up to a flatness of about 2 μm / cm.
Even if LTV is not excessively set to 0.5 μm / 1.5 cm ² or less, a sufficiently good yield can be obtained by using a wafer whose LTV is set to 2 μm / 1.5 cm ² or less. Incidentally, in a method not using a pulse voltage, it is sufficient to use a wafer whose LTV is set to 1.5 μm / 1.5 cm ² or less.

On the other hand, as described above with reference to FIG. 4, since the peeling frequency is related to the slope angle of the depression, it is not sufficient to consider only the LTV as described in FIG. 1 (A). . That is, even if the LTV is 2 μm / 1.5 cm ² or less, if the depression has a very small slope angle, it may cause peeling. An experiment was conducted on the relationship between the maximum slope angle of the dent at the peeled portion and the number of the dents (corresponding to the frequency of peeling) in those bonded together using a pulse voltage, and the results shown in FIG. 1 (B) were obtained. I got As is clear from FIG. 1 (B), when the slope angle is 0.4 ° or less, the peeling frequency is small, and together with the results shown in FIG. 1 (A), when the LTV is 2 μm / 1.5 cm ² or less. If a wafer having a maximum slope angle of 0.4 ° or less is bonded, a semiconductor substrate that does not peel off can be produced.

Therefore, even without providing excessive standard called LTV as in the prior art there is no depression at 0.5 [mu] m / 1.5 cm ² or less, LTV is 2 [mu] m /
If the standard is 1.5 cm ² or less and the maximum slope angle is 0.4 ° or less, a semiconductor substrate with low cost and good yield can be obtained.

In addition, if the wafer is warped to an appropriate state, the bonding strength increases and the unbonded area decreases. Therefore, in the past, the wafer was deliberately warped and bonded. I can't do that). However, in the present invention, since the bonding can be performed reliably, the wafer may not be warped as much as in the prior art, and therefore, no problem occurs in the exposure processing and the heat treatment.

As a second example, one silicon wafer is oxidized to grow polycrystalline silicon on the oxide film by a CVD method (in this case,
Instead of polycrystalline silicon, amorphous silicon may be used), and the polycrystalline silicon surface is polished so as to be within the standard defined by the present invention. On the other hand, one side of a separately prepared silicon wafer is polished so as to be within the above standard. The polished surfaces of these two silicon wafers are bonded together in the same manner as in the first example, and the surfaces on which the elements are formed are polished.

As a third example, vapor deposition or CV on one silicon wafer
The refractory metal is grown by the method D, and the refractory metal surface is polished so as to be within the standard defined by the present invention. On the other hand, one side of a separately prepared silicon wafer is polished so as to be within the above standard. A separately prepared silicon wafer is placed on the polished surface of the refractory metal so that the polished surfaces are in contact with each other, and annealed within the melting point temperature of this metal (in this annealing, rapid annealing (short-time heat treatment) is used. May be polished).

In each of the first to third examples, a compound semiconductor wafer or an insulator wafer such as silicon oxide or alumina may be used instead of the silicon wafer.

〔The invention's effect〕

As described above, according to the present invention, a substrate can be manufactured at low cost and with high yield by bonding using a wafer of the above-mentioned standard without using an ultra-high flatness wafer. Also, since no peeling occurs, there is no problem of contamination during the wafer process, and the chip yield can be improved.
Further, since the bonding can be performed reliably, the wafer may not be warped so much that the exposure processing and the heat treatment can be performed reliably.

[Brief description of the drawings]

FIG. 1 is a view for explaining the standard according to the present invention, FIG. 2 is a view showing a manufacturing process of a general SOI, FIG. 3 is a view for explaining peeling due to an unbonded area, and FIG. FIG. 5 is a diagram illustrating the relationship, and FIG. 5 is a diagram illustrating the slope angle of the depression. In the figure, 1 and 2 indicate a silicon wafer, 3 indicates a silicon oxide film, 4 indicates a depression, and 5 indicates an unbonded area.

Claims (1)

(57) [Claims] 1. A semiconductor device having a substrate formed by laminating two wafers using a bonding method, wherein the LTV (local thickness value) is 2 μm / 1.5 cm ² or less,
A semiconductor device comprising a wafer having a maximum slope angle of a depression of 0.4 ° or less.