JP3632531B2 - Manufacturing method of semiconductor substrate - Google Patents

Manufacturing method of semiconductor substrate Download PDF

Info

Publication number
JP3632531B2
JP3632531B2 JP32693599A JP32693599A JP3632531B2 JP 3632531 B2 JP3632531 B2 JP 3632531B2 JP 32693599 A JP32693599 A JP 32693599A JP 32693599 A JP32693599 A JP 32693599A JP 3632531 B2 JP3632531 B2 JP 3632531B2
Authority
JP
Japan
Prior art keywords
wafer
oxide film
manufacturing
semiconductor substrate
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32693599A
Other languages
Japanese (ja)
Other versions
JP2001144274A (en
Inventor
誠二 藤野
啓明 氷見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP32693599A priority Critical patent/JP3632531B2/en
Publication of JP2001144274A publication Critical patent/JP2001144274A/en
Application granted granted Critical
Publication of JP3632531B2 publication Critical patent/JP3632531B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、複合IC、LSIを含む半導体装置一般に用いられる半導体基板の製造方法に関する。
【0002】
【従来の技術】
半導体基板上に中間絶縁膜を介して半導体層が配設されるSOI(シリコンオンインシュレータ)半導体装置は、バイポーラ、MOS、パワー素子等の複数の種類の素子を1チップに搭載するもの、例えば複合ICや高耐圧ICおよび高速低消費電力が要求される携帯機器用LSIに用いるのに好適である。
【0003】
SOI半導体装置を製造するには、基板としてSiOのような絶縁物からなる非常に抵抗の高い層の上に高品質の結晶性半導体層が形成されたいわゆるSOI基板が必要である。このようなSOI基板の製造方法としては、従来、貼り合わせ法が知られていた。この方法は、少なくとも主面側が鏡面研磨された第1の半導体基板よりなるベースウェハと、少なくとも主面側が鏡面研磨された第2の半導体基板よりなるボンドウェハを用い、両者のうち少なくともいずれか一方の主面に酸化膜を形成したのち、該2枚のウェハの主面同士を清浄雰囲気中で接着し、さらに、高温の結合熱処理を行って2枚のウェハを結合させたのち、結合ウェハのボンド側裏面を平面研削および鏡面研磨してデバイス特性上必要な所定のSOI層厚さにすることでSOI基板を製造している。
【0004】
【発明が解決しようとする課題】
しかしながら、従来の貼り合わせSOI基板の製造方法においては、図6に示すように、予め狙いのウェハ径に成形された2枚のミラーウェハ51、52を酸化膜53を介して貼り合わせた後(図6(a))、ボンド側ウェハ52の周辺から数mmの端部をエッジ研削により接合界面近傍まで除去し(図6(b))、しかる後、NaOH等のアルカリ溶液中に浸漬し酸化膜53(SiO)面を露出させ(図6(c))、ボンド側ウェハ52を平面研削(図6(d))、及び鏡面研磨(図6(e))していた。しかしこの方法では、エッジ研削、アルカリエッチという工程が必要であり、SOI基板の製造工程における工数の増加、スループットの低下によるコスト増加の要因となっていた。
【0005】
また図7に示す別の従来技術によるSOI基板の製造方法では、予め狙いのウェハ径に成形された2枚のミラーウェハ61、62を酸化膜63を介して貼り合わせた後(図7(a))、一方のウェハ62を所定のSOI厚さ近傍まで平面研削を行い(図7図(b))、ウェハ外周から数mmを残して、SOI側表面を耐酸性のマスキングテープ64で覆いフッ酸硝酸混液中に浸して端部のSiを除去し酸化膜63(SiO)面を露出させ(図7(c))、鏡面研磨(図7(d))を行っていた。しかしこの方法では、マスキングテープ貼付け等が必要とされ、先の図6に示した方法と同様、SOI基板の製造工程における工数の増加、スループットの低下によるコスト増加の要因となっていた。
【0006】
さらに、これら従来の方法で製造したSOIウェハは、外周部においてベースウェハが外側に突出したテラス構造となる。これは、デバイス形成用に使用できるボンドウェハ側の有効領域が減少するという問題があるのみならず、デバイス形成プロセス途中でテラス構造部に残留した種々の堆積膜に起因して、又は素子間分離のためのトレンチエッチング時にベースウェハ端部のSiが露出してブラックシリコンの発生を誘発させたりして、甚だしい場合は、後工程でそれらが剥離し、汚染源、パーティクル源となって歩留まり低下を引き起こす原因になるという問題がある。
【0007】
本発明は上記問題点に鑑みなされたもので、SOIウェハの製造コスト削減を図るとともに、デバイス形成プロセス途中のパーティクルの発生等の原因で歩留まりを低下させてしまうのを抑制することのできるSOI半導体基板の製造方法を提供することを目的とするものである。
【0008】
【課題を解決するための手段】
上記目的を達成するため、請求項1に記載の発明では、少なくとも主面が鏡面研磨された第1の半導体基板よりなるベースウェハ(1)と、少なくとも主面が鏡面研磨された第2の半導体基板よりなるボンドウェハ(2)とを用意し、ベースウェハ及びボンドウェハのうち少なくともいずれか一方の主面に酸化膜(3)を形成する工程と、ベースウェハ及びボンドウェハの主面同士が向かい合うように、酸化膜を介してベースウェハ及びボンドウェハを結合させ結合ウェハを形成する工程と、結合ウェハのうちボンドウェハ側の裏面を平面研削および鏡面研磨して所定のSOI層厚さにする工程と、を含む貼り合わせSOIウェハの製造方法において、結合工程を終了した後に、ベースウェハ及びボンドウェハのうち少なくともいずれか一方の端部に形成された酸化膜を希フッ酸にて除去する工程と、この酸化膜を除去する工程の後に、結合ウェハの端部にベベリング処理を施す工程とを有し、さらに、酸化膜を除去する工程で、ベースウェハ及び前記ボンドウェハのうち少なくともいずれか一方の裏面に形成された酸化膜が残るようにすることを特徴としている。
【0009】
このように、結合熱処理終了後にベベリング処理を行うことで、従来の貼り合わせSOIウェハの製造工程で必要であったエッジ研削またはマスキングテープ貼りとアルカリエッチングの工程を削減することができ、SOIウェハの製造コスト削減を図ることが出来る。また、従来のSOIウェハの製造方法では避けることのできなかったウェハ外周部におけるテラス構造をなくすことができ、デバイス形成プロセス途中においてテラス構造部の存在に起因した汚染あるいはパーティクルの発生は抑制され、歩留まりの低下を防ぐことができるという効果がある。また、ベベリング処理の前に、ベースウェハ及びボンドウェハのうち少なくともいずれか一方の端部に形成された酸化膜を取り除いておくことにより、砥石の焼き付きや磨耗を防ぐことができる。 さらに、酸化膜を除去する工程で、ベースウェハ及び前記ボンドウェハのうち少なくともいずれか一方の裏面に形成された酸化膜が残るようにすれば、両ウェハの間の酸化膜の応力の影響でウェハに反りが生じることを抑制できる。
【0010】
なお、請求項2に示すように、第1及び第2の半導体基板として、その外径が最終的に出来上がるSOIウェハの外径よりも大きな外径を持つ半導体基板を用いれば、ベベリング加工による径の縮小を見込むことができる。
【0011】
例えば、請求項3に示すように、結合ウェハの端部に施すベベリング処理は、結合工程を終了した後、平面研削前に行うことができる。また、請求項4に示すように、平面研削終了後、鏡面研磨前に行うことができる。また、請求項5に示すように、鏡面研磨終了後に行ってもよい。
【0015】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。
【0016】
【発明の実施の形態】
(第1実施形態)
本発明の第1実施形態を図に基づいて説明する。図1は、SOI基板の製造工程を示している。以下、図1に基づいて本実施形態におけるSOI基板の製造方法を説明する。
【0017】
〔図1(a)に示す工程〕
まず、少なくとも一方の主面が鏡面研磨された第1の半導体基板としてのベースウェハ1と、少なくとも一方の主面が鏡面研磨された第2の半導体基板としてのボンドウェハ2を用意する。そして、両ウェハのうち少なくともいずれか一方の主面に例えば酸化性雰囲気中1050℃の熱処理を行って1μm程度の酸化膜(SiO)3を形成した後、2枚のウェハの主面同士が向かい合うように清浄雰囲気中で接着し、例えば酸化性もしくは窒素雰囲気中で1100℃,1Hr程度の結合熱処理を行い結合ウェハ4を作成する。
【0018】
〔図1(b)に示す工程〕
次に、上記結合ウェハ4のうちボンド側ウェハ2の裏面(接合面と反対側の主面)から平面研削を行い、狙いのSOI厚近傍の厚さまで薄く削る。この時、研削は荒研削から仕上げ研削へと適宜砥石の番手を変えて研削し、なるべく研削による破砕層が深くまで残らないようにすることが望ましい。
【0019】
〔図1(c)に示す工程〕
次に、上記平面研削を終了した結合ウェハ4の端部を砥石を使ってベベリング処理(面取り加工)する。このベベリング処理は、図2に示すような略円形状の凹部を有する砥石5を用いて行われる。この時、酸化膜3のうち結合ウェハ4の端部および裏面に位置する部分は、砥石5の焼き付きや摩耗を防ぐ目的で、予め希フッ酸溶液ディップ等の手段で取り除いておく。ただし、結合界面の埋め込み部分の酸化膜3が厚い場合には応力の影響でウェハ4に反りが生ずるので、裏面の酸化膜3を意図的に残すようにするのが望ましい。このためには例えばポットチャックのような冶具を用いる等で、酸化膜3のうちベースウェハ2の端部に位置する部分のみを除去し裏面の酸化膜を残すようにしても良い。
【0020】
〔図1(d)に示す工程〕
ベベリング処理が終了したならば、次に鏡面研磨を行う。これにより、SOIウェハが構成される。なお、この鏡面研磨は通常行われているように、1次研磨、2次研磨、仕上げ研磨の順に行い所定のSOI厚でデバイスグレードの鏡面を得る。最後に洗浄を行ってSOI基板が完成する。
【0021】
上記実施形態において、最初に用いる第1および第2の半導体基板としてのベースウェハ1及びボンドウェハ2の外径は、出来上がりの(結合ウェハ4をベベリング処理した後に要求される)SOIウェハの外径よりも大きい半導体基板を用いることが望ましい。何故ならば、ベベリング処理(図1(c)参照)においては、ウェハ端部の面取りを行う結果、ウェハの外径も小さくなる場合があるからである。
【0022】
また、上記実施形態においては、最初に用いる第1および第2の半導体基板としてのベースウェハ1及びボンドウェハ2の端部にはベベリング処理を行っていないものを使用している。すなわち、インゴットからスライシングしたウェハにラッピング、エッチング、洗浄を行った状態のウェハを用い、2枚のウェハ1、2を結合した後、結合ウェハ4を一体としてベベリングする。これにより、従来行われていた第1および第2の半導体基板それぞれのベベリング工程を削減することができる。
【0023】
また、上記実施形態においては、ウェハ接合後にベベリング処理を行い、最終的に出来あがるSOI基板の略半分の厚みのところで径が最大となるように、ボンドウェハ、ベースウェハ共に面取り加工される。従って、平面研削、鏡面研磨によって薄膜化された後の貼り合わせSOI基板は、その断面形状が特にその表面の研磨面において一枚の鏡面ウェハと同じになると共に、周縁部には外見的にもなだらかな面取りがなされ、いわゆるテラス構造が形成されない。また、同構造のSOI基板を略同径のボンドウェハ、ベースウェハを用いて形成することができる。
【0024】
このように、本実施形態によれば、結合熱処理終了後にベベリング処理を行うことで、従来の貼り合わせSOIウェハの製造工程で必要であったエッジ研削またはマスキングテープ貼りとアルカリエッチングの工程を削減することができ、SOIウェハの製造コスト削減を図ることが出来る。また、従来のSOIウェハの製造方法では避けることのできなかったウェハ外周部におけるテラス構造をなくすことができる。これにより、実際にボンドウェハ側にデバイス形成を行う際にテラス構造部の存在に起因して従来発生していたテラス構造部からの堆積膜剥離やテラス構造部でのブラックシリコンの発生等によるパーティクルの発生等を抑制でき、歩留まりの低下を防ぐことができるという効果がある。
【0025】
(第2実施形態)
図3に、本発明の第2実施形態におけるSOI基板の製造工程を示す。本実施形態のうち第1実施形態と異なる点は、図3(b)に示す工程であり、結合後のベベリング処理を結合熱処理終了後、平面研削前に行うことである。この場合、最終的に出来上がるSOI基板の略半分の厚みのところで径が最大になるような形状にベベリングする。このようにしても第1実施形態と同様の効果が得られる。
【0026】
なお、図3(a)に示す工程は図1(a)に示すウェハ貼り合わせ工程に相当し、図3(c)、(d)に示す工程は各々図1(b)の平面研削、図1(d)の鏡面研磨の各工程に相当している。
【0027】
(第3実施形態)
図4に、本発明の第3実施形態におけるSOI基板の製造工程を示す。本実施形態のうち第1実施形態と異なる点は、図4(d)に示す工程であり、結合後のベベリング処理を鏡面研磨終了後に行う点である。このようにしても第1実施形態と同様の効果が得られる。
【0028】
なお、図4に示す各工程は、図1に示す各工程のうち、図1(c)に示す工程と図1(d)に示す工程の順序を入れ替えたものに相当する。
【0029】
(第4実施形態)
図5に、本発明の第4実施形態におけるSOI基板の製造工程を示す。本実施形態のうち第1実施形態と異なる点は、図5(a)に示す工程であり、最初に用いる第1および第2の半導体基板として、通常と同様ベベリング処理が施されている基板を用いている点である。予めベベリング処理が行われていてもウェハの外径が大きければ、結合熱処理後に結合ウェハを一体としてベベリング処理を行うことで、上記第1実施形態と同じ効果を実現することができる。なお、図5(b)以降の工程については図1(b)以降の工程と同様であるが、もちろん第2〜第4実施形態のごとくベベリング処理,平面研削,鏡面研磨の各工程の順序を入れ替えるようにしてもよい。
【図面の簡単な説明】
【図1】本発明の第1実施形態におけるSOI基板の製造工程を示す図である。
【図2】ベベリング処理の様子を示す図である。
【図3】本発明の第2実施形態におけるSOI基板の製造工程を示す図である。
【図4】本発明の第3実施形態におけるSOI基板の製造工程を示す図である。
【図5】本発明の第4実施形態におけるSOI基板の製造工程を示す図である。
【図6】従来のSOI基板の製造工程を示す図である。
【図7】従来のSOI基板の製造工程を示す図である。
【符号の説明】
1…ベースウェハ、2…ボンドウェハ、3…酸化膜、4…結合ウェハ。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor substrate that is generally used for semiconductor devices including composite ICs and LSIs.
[0002]
[Prior art]
2. Description of the Related Art An SOI (silicon on insulator) semiconductor device in which a semiconductor layer is disposed on a semiconductor substrate via an intermediate insulating film is a device in which a plurality of types of elements such as bipolar, MOS, and power elements are mounted on a single chip, for example, a composite It is suitable for use in ICs, high voltage ICs, and LSIs for portable devices that require high speed and low power consumption.
[0003]
In order to manufacture an SOI semiconductor device, a so-called SOI substrate in which a high-quality crystalline semiconductor layer is formed on a very high resistance layer made of an insulator such as SiO 2 is required as a substrate. Conventionally, a bonding method has been known as a method for manufacturing such an SOI substrate. This method uses a base wafer made of a first semiconductor substrate having at least a main surface mirror-polished and a bond wafer made of a second semiconductor substrate having at least a main surface mirror-polished, and at least one of the two is used. After forming an oxide film on the main surface, the main surfaces of the two wafers are bonded together in a clean atmosphere, and after bonding the two wafers by performing high-temperature bonding heat treatment, bonding of the bonded wafers The SOI substrate is manufactured by surface grinding and mirror polishing the side and back surfaces to obtain a predetermined SOI layer thickness required for device characteristics.
[0004]
[Problems to be solved by the invention]
However, in the conventional method for manufacturing a bonded SOI substrate, as shown in FIG. 6, after two mirror wafers 51 and 52 that have been previously molded to a target wafer diameter are bonded via an oxide film 53 ( 6 (a)), an edge of several mm from the periphery of the bond side wafer 52 is removed to the vicinity of the bonding interface by edge grinding (FIG. 6 (b)), and then immersed in an alkaline solution such as NaOH for oxidation. The film 53 (SiO 2 ) surface was exposed (FIG. 6C), and the bond-side wafer 52 was surface ground (FIG. 6D) and mirror-polished (FIG. 6E). However, this method requires steps such as edge grinding and alkali etching, which increase the number of steps in the manufacturing process of the SOI substrate and increase the cost due to a decrease in throughput.
[0005]
In another SOI substrate manufacturing method according to the prior art shown in FIG. 7, two mirror wafers 61 and 62 previously formed to have a target wafer diameter are bonded together via an oxide film 63 (FIG. )), One of the wafers 62 is ground to the vicinity of a predetermined SOI thickness (FIG. 7B), leaving a few millimeters from the outer periphery of the wafer, and covering the SOI side surface with an acid-resistant masking tape 64. It was immersed in a mixed solution of oxynitric acid to remove Si at the end to expose the surface of the oxide film 63 (SiO 2 ) (FIG. 7C), and mirror polishing (FIG. 7D) was performed. However, in this method, masking tape sticking or the like is required, and, like the method shown in FIG. 6, the man-hours in the manufacturing process of the SOI substrate are increased, and the cost is increased due to the decrease in throughput.
[0006]
Furthermore, SOI wafers manufactured by these conventional methods have a terrace structure in which the base wafer protrudes outward at the outer periphery. This is not only a problem that the effective area on the bond wafer side that can be used for device formation is reduced, but also due to various deposited films remaining in the terrace structure part during the device formation process or due to element isolation. When the trench etching is performed, the silicon at the edge of the base wafer is exposed to induce the generation of black silicon. If it is severe, they will be peeled off in a later process, causing contamination and particle sources to reduce the yield. There is a problem of becoming.
[0007]
The present invention has been made in view of the above problems, and an SOI semiconductor capable of reducing the manufacturing cost of an SOI wafer and suppressing a decrease in yield due to generation of particles during the device formation process. An object of the present invention is to provide a method for manufacturing a substrate.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a base wafer (1) comprising a first semiconductor substrate having at least a main surface mirror-polished, and a second semiconductor having at least a main surface mirror-polished. A bond wafer (2) made of a substrate is prepared, and a step of forming an oxide film (3) on at least one main surface of the base wafer and the bond wafer is arranged so that the main surfaces of the base wafer and the bond wafer face each other. A bonding process including a step of bonding a base wafer and a bond wafer through an oxide film to form a bonded wafer, and a step of surface grinding and mirror polishing the back surface of the bonded wafer on the bond wafer side to obtain a predetermined SOI layer thickness. In the method for manufacturing a bonded SOI wafer, after the bonding step is completed, at least one of a base wafer and a bond wafer And removing at the end dilute hydrofluoric acid formed oxide film, after the step of removing the oxide film, possess a step of subjecting the beveling process to the end of the bond wafer, further, the oxide film In the removing step, an oxide film formed on the back surface of at least one of the base wafer and the bond wafer is left.
[0009]
In this way, by performing the beveling process after the end of the bonding heat treatment, it is possible to reduce the steps of edge grinding or masking tape application and alkali etching, which are necessary in the manufacturing process of the conventional bonded SOI wafer. Manufacturing costs can be reduced. Further, it is possible to eliminate the terrace structure at the outer periphery of the wafer, which was unavoidable with the conventional SOI wafer manufacturing method, and the occurrence of contamination or particles due to the presence of the terrace structure during the device formation process is suppressed. There is an effect that a decrease in yield can be prevented. Further, by removing the oxide film formed on at least one of the base wafer and the bond wafer before the beveling treatment, it is possible to prevent the grindstone from being seized or worn. Further, if the oxide film formed on the back surface of at least one of the base wafer and the bond wafer is left in the step of removing the oxide film, the wafer is affected by the stress of the oxide film between the two wafers. The occurrence of warping can be suppressed.
[0010]
In addition, as shown in claim 2, if a semiconductor substrate having an outer diameter larger than the outer diameter of the finally obtained SOI wafer is used as the first and second semiconductor substrates, the diameter by beveling processing is used. Can be expected to shrink.
[0011]
For example, as shown in claim 3, the beveling process applied to the end portion of the bonded wafer can be performed after the bonding process and before the surface grinding. Moreover, as shown in Claim 4, it can carry out after a surface grinding and before mirror polishing. Further, as shown in claim 5, it may be performed after the completion of mirror polishing.
[0015]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a manufacturing process of an SOI substrate. Hereinafter, a method for manufacturing an SOI substrate according to the present embodiment will be described with reference to FIG.
[0017]
[Step shown in FIG. 1 (a)]
First, a base wafer 1 as a first semiconductor substrate having at least one main surface mirror-polished and a bond wafer 2 as a second semiconductor substrate having at least one main surface mirror-polished are prepared. Then, after heat treatment at, for example, 1050 ° C. in an oxidizing atmosphere is performed on at least one main surface of both wafers to form an oxide film (SiO 2 ) 3 of about 1 μm, the main surfaces of the two wafers are Bonding is performed in a clean atmosphere so as to face each other, and for example, bonding heat treatment is performed at about 1100 ° C. and about 1 Hr in an oxidizing or nitrogen atmosphere to form a bonded wafer 4.
[0018]
[Step shown in FIG. 1B]
Next, surface grinding is performed from the back surface (main surface on the side opposite to the bonding surface) of the bond-side wafer 2 in the bonded wafer 4, and the surface is thinned to a thickness near the target SOI thickness. At this time, it is desirable that the grinding is performed by appropriately changing the count of the grindstone from rough grinding to finish grinding so that the crushed layer is not left as deep as possible.
[0019]
[Step shown in FIG. 1 (c)]
Next, beveling processing (chamfering processing) is performed on the end of the bonded wafer 4 after the surface grinding using a grindstone. This beveling process is performed using a grindstone 5 having a substantially circular recess as shown in FIG. At this time, the portions of the oxide film 3 located at the end and back surface of the bonded wafer 4 are previously removed by means such as dilute hydrofluoric acid solution dipping in order to prevent the grindstone 5 from being seized or worn. However, when the oxide film 3 in the buried portion of the bonding interface is thick, the wafer 4 is warped due to the influence of stress. Therefore, it is desirable to intentionally leave the oxide film 3 on the back surface. For this purpose, for example, a jig such as a pot chuck may be used to remove only a portion of the oxide film 3 located at the end of the base wafer 2 and leave the oxide film on the back surface.
[0020]
[Step shown in FIG. 1 (d)]
When the beveling process is completed, mirror polishing is performed next. Thereby, an SOI wafer is formed. In addition, as usual, this mirror polishing is performed in the order of primary polishing, secondary polishing, and finish polishing to obtain a device-grade mirror surface with a predetermined SOI thickness. Finally, cleaning is performed to complete the SOI substrate.
[0021]
In the above embodiment, the outer diameters of the base wafer 1 and the bond wafer 2 as the first and second semiconductor substrates to be used first are larger than the outer diameter of the completed SOI wafer (required after the bonding wafer 4 is beveled). It is desirable to use a large semiconductor substrate. This is because in the beveling process (see FIG. 1C), the wafer outer diameter may be reduced as a result of chamfering the wafer edge.
[0022]
Moreover, in the said embodiment, what has not performed the beveling process is used for the edge part of the base wafer 1 and the bond wafer 2 as a 1st and 2nd semiconductor substrate used initially. That is, using a wafer that has been lapped, etched, and washed on a wafer sliced from an ingot, the two wafers 1 and 2 are bonded together, and then the combined wafer 4 is integrally beveled. Thereby, the beveling process of each of the first and second semiconductor substrates which has been conventionally performed can be reduced.
[0023]
Further, in the above embodiment, the beveling process is performed after the wafer bonding, and both the bond wafer and the base wafer are chamfered so that the diameter becomes maximum at about half the thickness of the finally obtained SOI substrate. Therefore, the bonded SOI substrate that has been thinned by surface grinding or mirror polishing has the same cross-sectional shape as that of a single mirror wafer, particularly on the polishing surface of the surface, and the peripheral portion also has an appearance. A gentle chamfering is made and a so-called terrace structure is not formed. In addition, an SOI substrate having the same structure can be formed using a bond wafer and a base wafer having substantially the same diameter.
[0024]
As described above, according to the present embodiment, by performing the beveling process after the end of the bonding heat treatment, the steps of edge grinding or masking tape application and alkali etching, which are necessary in the manufacturing process of the conventional bonded SOI wafer, are reduced. Therefore, the manufacturing cost of the SOI wafer can be reduced. Further, it is possible to eliminate the terrace structure on the outer periphery of the wafer, which cannot be avoided by the conventional SOI wafer manufacturing method. As a result, when the device is actually formed on the bond wafer side, particles deposited due to the peeling of the deposited film from the terrace structure part or the generation of black silicon in the terrace structure part due to the presence of the terrace structure part are generated. Generation | occurrence | production etc. can be suppressed and there exists an effect that the fall of a yield can be prevented.
[0025]
(Second Embodiment)
FIG. 3 shows a manufacturing process of the SOI substrate in the second embodiment of the present invention. The difference of this embodiment from the first embodiment is the step shown in FIG. 3B, in which the beveling process after bonding is performed after the bonding heat treatment and before surface grinding. In this case, beveling is performed in such a shape that the diameter becomes maximum at about half the thickness of the finally obtained SOI substrate. Even if it does in this way, the effect similar to 1st Embodiment is acquired.
[0026]
The process shown in FIG. 3A corresponds to the wafer bonding process shown in FIG. 1A, and the processes shown in FIGS. 3C and 3D are the surface grinding and FIG. This corresponds to each step of mirror polishing 1 (d).
[0027]
(Third embodiment)
FIG. 4 shows a manufacturing process of an SOI substrate in the third embodiment of the present invention. The difference of the present embodiment from the first embodiment is the step shown in FIG. 4D, in which the beveling process after bonding is performed after the mirror polishing is completed. Even if it does in this way, the effect similar to 1st Embodiment is acquired.
[0028]
Each process shown in FIG. 4 corresponds to the process shown in FIG. 1 in which the order of the process shown in FIG. 1C and the process shown in FIG.
[0029]
(Fourth embodiment)
FIG. 5 shows an SOI substrate manufacturing process according to the fourth embodiment of the present invention. In this embodiment, the difference from the first embodiment is the process shown in FIG. 5A. As the first and second semiconductor substrates to be used first, a substrate that has been subjected to a beveling process as usual is used. It is a point to use. Even if the beveling process has been performed in advance, if the outer diameter of the wafer is large, the same effect as in the first embodiment can be realized by performing the beveling process with the bonded wafer as a unit after the bonding heat treatment. The steps after FIG. 5B are the same as the steps after FIG. 1B, but of course the order of the steps of beveling, surface grinding, and mirror polishing as in the second to fourth embodiments. You may make it replace.
[Brief description of the drawings]
FIG. 1 is a diagram showing a manufacturing process of an SOI substrate in a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a state of a beveling process.
FIG. 3 is a diagram showing a manufacturing process of an SOI substrate in a second embodiment of the present invention.
FIG. 4 is a diagram showing a manufacturing process of an SOI substrate in a third embodiment of the present invention.
FIG. 5 is a diagram showing a manufacturing process of an SOI substrate in a fourth embodiment of the present invention.
FIG. 6 is a diagram showing a manufacturing process of a conventional SOI substrate.
FIG. 7 is a diagram showing a manufacturing process of a conventional SOI substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base wafer, 2 ... Bond wafer, 3 ... Oxide film, 4 ... Bonded wafer.

Claims (5)

少なくとも主面が鏡面研磨された第1の半導体基板よりなるベースウェハ(1)と、少なくとも主面が鏡面研磨された第2の半導体基板よりなるボンドウェハ(2)とを用意し、前記ベースウェハ及び前記ボンドウェハのうち少なくともいずれか一方の主面および端部に酸化膜(3)を形成する工程と、 前記ベースウェハ及び前記ボンドウェハの主面同士が向かい合うように、前記酸化膜を介して前記ベースウェハ及び前記ボンドウェハを結合させ結合ウェハを形成する工程と、
前記結合ウェハのうち前記ボンドウェハ側の裏面を平面研削および鏡面研磨して所定のSOI層厚さにする工程と、を含む貼り合わせSOIウェハの製造方法において、
前記結合工程を終了した後に、前記ベースウェハ及び前記ボンドウェハのうち少なくともいずれか一方の端部に形成された前記酸化膜を希フッ酸にて除去する工程と、
この酸化膜を除去する工程の後に、前記結合ウェハの端部にベベリング処理を施す工程とを有し、
さらに、前記酸化膜を形成する工程では、前記ベースウェハ及び前記ボンドウェハのうち少なくともいずれか一方の裏面にも前記酸化膜を形成し、
前記酸化膜を除去する工程では、前記裏面に形成された前記酸化膜を残すことを特徴とする半導体基板の製造方法。
A base wafer (1) made of a first semiconductor substrate having at least a main surface mirror-polished and a bond wafer (2) made of a second semiconductor substrate having at least a main surface mirror-polished are prepared, and the base wafer and A step of forming an oxide film (3) on at least one main surface and an end of the bond wafer; and the base wafer via the oxide film so that the main surfaces of the base wafer and the bond wafer face each other. And bonding the bond wafer to form a bonded wafer;
In the manufacturing method of the bonded SOI wafer, including a step of performing a surface grinding and mirror polishing the back surface on the bond wafer side of the bonded wafer to a predetermined SOI layer thickness,
Removing the oxide film formed at the end of at least one of the base wafer and the bond wafer with dilute hydrofluoric acid after finishing the bonding step;
After the step of removing the oxide film, it possesses a step of subjecting the beveling process to an end of the coupling wafer,
Furthermore, in the step of forming the oxide film, the oxide film is also formed on the back surface of at least one of the base wafer and the bond wafer,
In the step of removing the oxide film, the oxide film formed on the back surface is left .
前記第1及び第2の半導体基板として、その外径が最終的に出来上がるSOIウェハの外径よりも大きな外径を持つ半導体基板を用いることを特徴とする請求項1に記載の半導体基板の製造方法。2. The semiconductor substrate manufacturing method according to claim 1, wherein the first and second semiconductor substrates are semiconductor substrates having an outer diameter larger than an outer diameter of an SOI wafer finally obtained. Method. 前記結合ウェハの端部に施すベベリング処理は、結合工程を終了した後、前記平面研削前に行うことを特徴とする請求項1又は2に記載の半導体基板の製造方法。3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the beveling process performed on the end portion of the bonded wafer is performed after the bonding process and before the surface grinding. 4. 前記結合ウェハの端部に施すベベリング処理は、前記平面研削終了後、前記鏡面研磨前に行うことを特徴とする請求項1又は2に記載の半導体基板の製造方法。3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the beveling process applied to the end portion of the bonded wafer is performed after the surface grinding and before the mirror polishing. 4. 前記結合ウェハの端部に施すベベリング処理は、前記鏡面研磨終了後に行うことを特徴とする請求項1又は2に記載の半導体基板の製造方法。The method for manufacturing a semiconductor substrate according to claim 1, wherein the beveling process performed on the end portion of the bonded wafer is performed after the mirror polishing is completed.
JP32693599A 1999-11-17 1999-11-17 Manufacturing method of semiconductor substrate Expired - Fee Related JP3632531B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32693599A JP3632531B2 (en) 1999-11-17 1999-11-17 Manufacturing method of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32693599A JP3632531B2 (en) 1999-11-17 1999-11-17 Manufacturing method of semiconductor substrate

Publications (2)

Publication Number Publication Date
JP2001144274A JP2001144274A (en) 2001-05-25
JP3632531B2 true JP3632531B2 (en) 2005-03-23

Family

ID=18193424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32693599A Expired - Fee Related JP3632531B2 (en) 1999-11-17 1999-11-17 Manufacturing method of semiconductor substrate

Country Status (1)

Country Link
JP (1) JP3632531B2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2899594A1 (en) 2006-04-10 2007-10-12 Commissariat Energie Atomique METHOD FOR ASSEMBLING SUBSTRATES WITH THERMAL TREATMENTS AT LOW TEMPERATURES
JP5028845B2 (en) 2006-04-14 2012-09-19 株式会社Sumco Bonded wafer and manufacturing method thereof
FR2935536B1 (en) 2008-09-02 2010-09-24 Soitec Silicon On Insulator PROGRESSIVE DETOURING METHOD
KR101550433B1 (en) 2009-01-30 2015-09-07 삼성전자주식회사 Method for fabricating semiconductor device
FR2957189B1 (en) 2010-03-02 2012-04-27 Soitec Silicon On Insulator METHOD OF MAKING A MULTILAYER STRUCTURE WITH POST GRINDING.
FR2961630B1 (en) 2010-06-22 2013-03-29 Soitec Silicon On Insulator Technologies APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICES
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
FR2964193A1 (en) 2010-08-24 2012-03-02 Soitec Silicon On Insulator METHOD FOR MEASURING ADHESION ENERGY, AND ASSOCIATED SUBSTRATES
CN106158580B (en) * 2015-03-25 2020-02-07 中芯国际集成电路制造(上海)有限公司 Wafer thinning method
JP6696473B2 (en) * 2017-04-17 2020-05-20 株式会社Sumco Multilayer SOI wafer and method of manufacturing the same
JP6292704B1 (en) * 2017-10-17 2018-03-14 株式会社松風 Cutting object for dental CADCAM and its adapter connecting the CAM holding part with the resin part

Also Published As

Publication number Publication date
JP2001144274A (en) 2001-05-25

Similar Documents

Publication Publication Date Title
EP1156531B1 (en) Method for reclaiming a delaminated wafer
KR101151458B1 (en) Method for manufacturing bonded wafer and bonded wafer
WO2007069442A1 (en) Method for manufacturing bonded substrate
US5918139A (en) Method of manufacturing a bonding substrate
JPH11354760A (en) Soi wafer and its production
JP6168143B2 (en) Method for manufacturing hybrid substrate
JP5292642B2 (en) Layer lamination and transfer process
JP4277469B2 (en) Method for producing bonded wafer and bonded wafer
JP3632531B2 (en) Manufacturing method of semiconductor substrate
JP2006270039A (en) Laminated wafer and manufacturing method thereof
JP2662495B2 (en) Method for manufacturing bonded semiconductor substrate
JP3480480B2 (en) Method for manufacturing SOI substrate
JPH08107091A (en) Manufacture of soi substrate
JPH10270298A (en) Manufacture of lamination substrate
JPH05109678A (en) Manufacture of soi substrate
JPH10335195A (en) Production of pasted board
JPH0964319A (en) Soi substrate and its manufacture
JP2003151939A (en) Method of manufacturing soi substrate
JP3945130B2 (en) Manufacturing method of bonded dielectric isolation wafer
JP3165735B2 (en) Semiconductor substrate manufacturing method
JP4440810B2 (en) Manufacturing method of bonded wafer
JPH07161948A (en) Semiconductor substrate and its manufacture
JP3524009B2 (en) SOI wafer and method for manufacturing the same
JP2003046071A (en) Production method for semiconductor device
JPH11163307A (en) Manufacture of laminated substrate

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040914

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041104

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20041130

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041213

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080107

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110107

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120107

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130107

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140107

Year of fee payment: 9

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees