JPS60175425A - Selective etching method - Google Patents
Selective etching methodInfo
- Publication number
- JPS60175425A JPS60175425A JP3058084A JP3058084A JPS60175425A JP S60175425 A JPS60175425 A JP S60175425A JP 3058084 A JP3058084 A JP 3058084A JP 3058084 A JP3058084 A JP 3058084A JP S60175425 A JPS60175425 A JP S60175425A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- resist
- pattern
- etched
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は金属、半導体などの選択エツチング方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for selectively etching metals, semiconductors, etc.
従来例の構成とその問題点
従来、金属や半導体の選択エツチングに用いられてきた
酸、アルカリ等によるウェットエツチング法はサイドエ
ツチング量の制御の困難さや、被エツチング物との濡れ
の不均一による加工形状の再現性の悪さなどのため、高
密度化、微細化プロセスには不向きである。特にショッ
トキー電極で有用なチタンやモリブデンのウェットエツ
チングはエツチングレートがエツチング時間と共に指数
関数的に増大するため、エツチング終点の確認が極めて
難しく、再現性よくウェットエツチングすることはでき
なかった。またラジカル・ガスによるドライエツチング
法においては、マスクとなる高分子有機化合物もエツチ
ングされるので、長時間のエツチングではマスク効果が
無くなってし1つたり、プラズマ中でレジストが硬化す
るだめエツチング後のレジスト除去が難しいなどの問題
があった。Conventional structure and its problems Wet etching methods using acids, alkalis, etc., which have been conventionally used for selective etching of metals and semiconductors, have difficulty controlling the amount of side etching and processing problems due to uneven wettability with the object to be etched. Due to poor shape reproducibility, it is unsuitable for high-density and miniaturization processes. In wet etching of titanium and molybdenum, which are particularly useful for Schottky electrodes, the etching rate increases exponentially with the etching time, making it extremely difficult to confirm the etching end point and making it impossible to perform wet etching with good reproducibility. In addition, in the dry etching method using radical gas, the high-molecular organic compound that serves as a mask is also etched. There were problems such as difficulty in resist removal.
発明の目的
本発明はかかる問題点を克服し、金属や半導体の加工を
容易ならしめる選択エツチング方法を提供するものであ
る。OBJECTS OF THE INVENTION The present invention provides a selective etching method that overcomes these problems and facilitates the processing of metals and semiconductors.
発明の構成
本発明は被エツチング物とレジスト材料の間にA7!膜
をはさみ、レジスト材料の露光後の現像時にA/の選択
、的除去を行ない、Allのノくターニングを行なった
後、このムlをマスクとして、被エツチング物のエツチ
ングを行なう選択エツチング方法である。Structure of the Invention The present invention provides an A7! This is a selective etching method in which the film is sandwiched, the resist material is developed after exposure, A/ is selected, targeted removal is performed, and after All is turned, the object to be etched is etched using this mura as a mask. be.
実施例の説明 以下実施例をあげて具体的に説明する。Description of examples The present invention will be specifically explained below with reference to examples.
第1図に本発明を用いて加工を行なった半導体装置の加
工工程の断面模式図を示す。n型GaAs基板10上に
EB蒸着法によりTi11を6000人、A/12を6
00人付着せしめ、有機高分子材料よシなるポジ型レジ
スト13を全面に塗布する(第1図(a))。次に、所
定のパターンでマスクし、露光する。ここで、レジスト
13はポジ型レジストなので露光した部分のみが現像液
に溶け、その他は残る。ポジ型レジスト13の現像液は
強力なアルカリよシ成っているため、現像の結果露出し
たA/12は現像時にエツチングされてしまい、特に付
加工程なしでAdのパターンができる(第1図(b))
。尚、ここで、Agの膜厚は500人と薄く、この液に
よるエツチングではサイドエツチングはほとんどなかっ
た。次にアセトンにより残ったレジスト13を除去し、
AL12をマスクとしTi 11をドライエツチングに
より除去する。ドライエツチングは減圧プラズマエツチ
ングを用い、CF4:02=1oO:1の混合ガスを0
.3torrに保ち、100Wのプラズマ中で20分間
エツチングを行なった。FIG. 1 shows a schematic cross-sectional view of the processing steps of a semiconductor device processed using the present invention. 6000 layers of Ti11 and 6000 layers of A/12 were deposited on the n-type GaAs substrate 10 by EB evaporation method.
A positive resist 13 made of an organic polymer material is applied over the entire surface (FIG. 1(a)). Next, it is masked with a predetermined pattern and exposed. Here, since the resist 13 is a positive type resist, only the exposed portion is dissolved in the developer, and the rest remains. Since the developer for the positive resist 13 consists of a strong alkali, the A/12 exposed as a result of development is etched away during development, creating an Ad pattern without any additional process (see Figure 1 (b). ))
. Note that the Ag film thickness here was as thin as 500 mm, and there was almost no side etching when etching with this solution. Next, remove the remaining resist 13 with acetone,
Ti 11 is removed by dry etching using AL 12 as a mask. Dry etching uses low pressure plasma etching, using a mixed gas of CF4:02=1oO:1.
.. Etching was performed for 20 minutes in a 100 W plasma while maintaining the pressure at 3 torr.
次にn型GaAs 10の裏面にAu−Sn合金14(
Sn 比10%)を真空蒸着により付着せしめ、400
’Cで合金化した(第1図(C))。以上のようにし
てショットキーダイオードが得られた。Next, an Au-Sn alloy 14 (
Sn ratio 10%) was deposited by vacuum evaporation, and 400
' Alloyed with C (Fig. 1 (C)). A Schottky diode was obtained in the above manner.
第2図にポジ型しジスト、ig 、 Tiの上記条件下
でのエツチング量とエツチング時間との関係を示す。A
eは全くエツチングされないのに対し、レジストやTi
はそれぞれ770人/ min 。FIG. 2 shows the relationship between the etching amount and etching time for positive type resist, ig, and Ti under the above conditions. A
e is not etched at all, whereas resist and Ti
770 people/min each.
260人/minでエツチングされることがわかる。It can be seen that etching is performed at a rate of 260 people/min.
レジスト13は残しておくと前述したようにプラズマ処
理中に硬化してしまい、容易に除去できなくなるために
エツチング前に除去した。If the resist 13 is left, it will harden during the plasma treatment as described above and cannot be easily removed, so it was removed before etching.
このように本発明に示す如く、ホトリソグラフィによる
パターン形成時にA6パターンを同時に形成することに
より、ドライエツチング時のマスク自体のエツチングが
無視し得る、微細、高密度パターンの形成が可能となっ
た。Thus, as shown in the present invention, by simultaneously forming an A6 pattern during pattern formation by photolithography, it has become possible to form a fine, high-density pattern in which etching of the mask itself during dry etching can be ignored.
以上本発明に関し実施例をあげて詳しく説明したが、被
エツチング物はT1 に限らず、Mo 、 Orなどの
金属およびSi 、 Ge、 GaAs等の半導体でも
可能である。レジスト材料もポジ型に限らず、ネガ型で
も可能である。Although the present invention has been described above in detail with reference to embodiments, the object to be etched is not limited to T1, but may also be metals such as Mo and Or, and semiconductors such as Si, Ge, and GaAs. The resist material is not limited to positive type, but may also be negative type.
発明の効果
以上のように、本発明は、被エツチング物とレジスト材
料との間にAe層を介在させることにより、被エツチン
グ物の微細加工が可能になり、その実用的効果は大なる
ものがある。Effects of the Invention As described above, the present invention enables microfabrication of the object to be etched by interposing the Ae layer between the object to be etched and the resist material, and has great practical effects. be.
第1図(2))〜(C)は本発明の実施例に係る工程断
面図、第2図はポジ型レジスト、Ti、A7?のプラズ
マエ、ノチにおけるエツチングレートの比較図である。
10−・−・・n型GaAs基板、11 ・=−Tj−
、12・・・・・・A6,13・・・・・・ポジ型レジ
スト、14・・・・・・Au −Sn合少。FIGS. 1(2) to (C) are process cross-sectional views according to embodiments of the present invention, and FIG. 2 is a positive resist, Ti, A7? FIG. 2 is a comparison diagram of etching rates in Plasmae and Nochi. 10-... n-type GaAs substrate, 11 .=-Tj-
, 12...A6, 13...Positive resist, 14...Au-Sn combination.
Claims (1)
する工程と、前記レジスト拐料およびAe層を選択的に
除去する工程と、前記除去されることにより形成された
A4パターンをマスクとして被エツチング物をエツチン
グする工程を有することを特徴とする選択エツチング方
法。A step of sequentially forming an Ae layer and a resist material on the object to be etched, a step of selectively removing the resist stripping material and the Ae layer, and a step of etching the object using the A4 pattern formed by the removal as a mask. A selective etching method comprising the step of etching an object.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3058084A JPS60175425A (en) | 1984-02-20 | 1984-02-20 | Selective etching method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3058084A JPS60175425A (en) | 1984-02-20 | 1984-02-20 | Selective etching method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60175425A true JPS60175425A (en) | 1985-09-09 |
Family
ID=12307788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3058084A Pending JPS60175425A (en) | 1984-02-20 | 1984-02-20 | Selective etching method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60175425A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62109319A (en) * | 1985-11-07 | 1987-05-20 | Fuji Electric Co Ltd | Manufacture of semiconductor element |
-
1984
- 1984-02-20 JP JP3058084A patent/JPS60175425A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62109319A (en) * | 1985-11-07 | 1987-05-20 | Fuji Electric Co Ltd | Manufacture of semiconductor element |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6195356A (en) | Photomask material | |
JPS60175425A (en) | Selective etching method | |
JPS62149125A (en) | Manufacture of semiconductor device | |
JPS604221A (en) | Manufacture of semiconductor device | |
JPH04124822A (en) | Manufacture of semiconductor device | |
KR960013140B1 (en) | Fabricating method of semiconductor device | |
JPS62149138A (en) | Manufacture of semiconductor device | |
JPH01214025A (en) | Manufacture of semiconductor device | |
JPS59165425A (en) | Pattern formation | |
JPH07176501A (en) | Manufacture of semiconductor device | |
JPS5856422A (en) | Formation of pattern | |
JPH0230748A (en) | Formation of fine pattern | |
JPS60254733A (en) | Pattern forming method | |
JPH01175247A (en) | Manufacture of semiconductor device | |
JPH02148725A (en) | Manufacture of semiconductor integrated circuit | |
JPS6116527A (en) | Manufacture of metallic electrode | |
JPS5892224A (en) | Pattern formation | |
JPH0350828A (en) | Method of forming gold wiring | |
JPH04329634A (en) | Formation of metal film pattern | |
JPH01145870A (en) | Manufacture of semiconductor device | |
JPH05343301A (en) | Method for fabricating x-ray mask | |
JPH02267967A (en) | Manufacture of semiconductor element | |
JPS63160345A (en) | Manufacture of semiconductor element | |
JPS63257249A (en) | Manufacture of semiconductor device | |
JPS59126636A (en) | Formation of microscopic pattern on semiconductor substrate |