JPS62149138A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62149138A
JPS62149138A JP29111085A JP29111085A JPS62149138A JP S62149138 A JPS62149138 A JP S62149138A JP 29111085 A JP29111085 A JP 29111085A JP 29111085 A JP29111085 A JP 29111085A JP S62149138 A JPS62149138 A JP S62149138A
Authority
JP
Japan
Prior art keywords
metal layer
layer
resistive contact
substrate
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29111085A
Other languages
Japanese (ja)
Inventor
Namiki Ootsuka
大塚 なみき
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29111085A priority Critical patent/JPS62149138A/en
Publication of JPS62149138A publication Critical patent/JPS62149138A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a resistive contact characterized by small resistance and good reproducibility, by completely removing resist before evaporating a metal layer, washing a device, and sufficiently washing the surface of a GaAs substrate, on which the resistive contact is obtained. CONSTITUTION:Photoresist 4 is applied on a gallium arsenide substrate 1 through an SiO2 film, and a pattern is formed. With the resist 4 as a mask, the SiO2 film 2 is removed. The resist 4 is removed, and the surface is masked with phosphoric acid. Then, Au.Ge.Ni are evaporated, and alloy reaction is carried out. An organic material 5 is applied, and heat treatment is performed. Then etching is performed. An unnecessary metal layer 3 and the compound 5 are simultaneously removed, and the thickness of the metal layer 3 is made thin. Finally, the SiO2 film 2 is removed by using fluoric acid. Thus, a resistive contact characterized by small resistance and good reproducibility is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子の製造方法に関し、特にガリウム
砒素半導体素子に抵抗性接触領域全形成する方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a full resistive contact area on a gallium arsenide semiconductor device.

〔従来の技術〕[Conventional technology]

従来、ガリウム砒素(GaAs)の基板に、抵抗性接触
2得る場合、次のような方法があり友。第2図はホトレ
ジスト4を用いてリフトオフを行々い抵抗性接触を得る
第1の従来例を説明する友めの工程を示す断面図、第3
図は二酸化シリコン(Si02)膜2とホトレジスト4
とを用いてリフトオフを行ない抵抗性接触を得る第2の
従来例を説明する定めの工程を示す断面図である。
Conventionally, the following methods have been used to obtain a resistive contact 2 to a gallium arsenide (GaAs) substrate. FIG. 2 is a cross-sectional view showing a companion process for explaining the first conventional example of obtaining resistive contact by performing lift-off using photoresist 4;
The figure shows a silicon dioxide (Si02) film 2 and a photoresist 4.
FIG. 7 is a cross-sectional view showing a predetermined process for explaining a second conventional example in which a resistive contact is obtained by performing lift-off using a conventional method.

例えば第2図アに示すようKGaAs基板l上にホトレ
ジスト4を塗布してパターンを形成したのち金属層3t
−被着する。次に第2図イに示すように有機溶剤中で超
音波処理によりホトレジスト4全付し、リフトオフを行
ない不要な金属層3を除去し友後合金化反応金行々う。
For example, as shown in FIG.
- Deposit. Next, as shown in FIG. 2A, the entire photoresist 4 is applied by ultrasonic treatment in an organic solvent, lift-off is performed to remove unnecessary metal layer 3, and alloying reaction gold is then performed.

あるいは第3図アに示すように5i02膜2を成長させ
7’CGaAs基板l上にホトレジスト4を塗布してパ
ターンを形成する。次に第3図イに示すように抵抗性接
触を得る部分のSin、膜2を除去し几のち全面に金属
層3t−被着する。その後、第3図つに示すよって前記
ホトレジストヲ用い几リフトオフ法により不要が金属層
3を除去し、その後、合金化反応t6なう。以上のよう
な方法があった。
Alternatively, as shown in FIG. 3A, a 5i02 film 2 is grown and a photoresist 4 is applied on a 7'CGaAs substrate 1 to form a pattern. Next, as shown in FIG. 3A, the portions of the Sin film 2 where a resistive contact is to be made are removed, and then a metal layer 3t is deposited on the entire surface. Thereafter, as shown in FIG. 3, the unnecessary metal layer 3 is removed by a lift-off method using the photoresist, and then an alloying reaction t6 is carried out. There was a method like the one above.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のホトレジストを使う交り7トオフ法によ
る抵抗性接触の形成方法でづ、ホトレジストによりパタ
ーンを形成し几のち金属層3vf−所定の厚さ蒸着し、
不要な金属層3をリフトオフ法により除去したのちにG
 a A s基板1と金属層30合金化を行なう。
According to the method of forming a resistive contact by the above-mentioned conventional cross-cutoff method using a photoresist, a pattern is formed using a photoresist, and then a metal layer is deposited to a predetermined thickness of 3Vf.
After removing unnecessary metal layer 3 by lift-off method, G
The a As substrate 1 and the metal layer 30 are alloyed.

このとき、リフトオフでパターニングを行なうため、有
機物であるホトレジスト4全付着したまま金属層3の真
空蒸着全行なう必要がある。そのため、蒸着時にホトレ
ジスト4よりガスが発生し、抵抗性接触を得るGaAs
基板1表面にガスが付着する。また、蒸着前の洗浄によ
りホトレジスト4に水分が吸着される友め蒸着時にガス
が発生しやすくなるため、十分な洗浄が行なえず、清浄
なGaAs基板1表面を得ることが困難なので接触抵抗
率が増大し、再現性が悪いという問題があった。
At this time, since patterning is performed by lift-off, it is necessary to perform the entire vacuum deposition of the metal layer 3 while the photoresist 4, which is an organic substance, is completely attached. Therefore, gas is generated from the photoresist 4 during vapor deposition, resulting in resistive contact between GaAs and GaAs.
Gas adheres to the surface of the substrate 1. In addition, since water is adsorbed to the photoresist 4 by cleaning before vapor deposition, gas is likely to be generated during vapor deposition, making it difficult to perform sufficient cleaning and obtaining a clean surface of the GaAs substrate 1, resulting in a decrease in contact resistivity. There was a problem that the number of particles increased and the reproducibility was poor.

さらにリフトオフを行々うとき強い超音波をかけ洗浄を
行なうため、GaAs基板1の破壊をまねくという問題
があった。
Furthermore, since strong ultrasonic waves are applied during lift-off for cleaning, there is a problem in that the GaAs substrate 1 may be destroyed.

ま几、第2図に示した方法では、第2図イに示し友よう
罠金属層3のエツジ部に突起6が残る。
However, in the method shown in FIG. 2, protrusions 6 remain at the edges of the trap metal layer 3 shown in FIG. 2A.

この突起6は合金化反応を行なうと形状がくずれるため
、金属層3の近傍に他の金属層が存在する場合にシ曽−
トするという問題が生じる。
This protrusion 6 loses its shape when an alloying reaction occurs, so if another metal layer exists near the metal layer 3,
The problem arises that the

また、GaAs基板1表面に金属層3による段差が残り
、平坦な面が得られ々いため、配線音節した場合段差の
部分で断線するおそれがある。
In addition, a level difference due to the metal layer 3 remains on the surface of the GaAs substrate 1, making it difficult to obtain a flat surface, so that if the wiring is connected, there is a risk of disconnection at the level difference.

〔問題点を解決する几めの手段〕[Elaborate means to solve problems]

本発明の目的は、上記の欠点を除去し、第2図イに示し
九よう々金属層エツジ部突起6が無く、段差の少かい、
低抵抗率で再現性の良い抵抗性接触の形成方法を提供す
ることにある。
The object of the present invention is to eliminate the above-mentioned drawbacks, and to eliminate the metal layer edge protrusion 6 as shown in FIG.
The object of the present invention is to provide a method for forming a resistive contact with low resistivity and good reproducibility.

本発明によれば、 (11GaAs基板上に絶縁物よりなる第一の層全形成
し几のち抵抗性接触を形成する領域に前記第一の層を開
口して前記GaAs基板を露出する工程、前記第一の層
の開口部を含む前記第一の層表面全体に第二金属層を被
着する工程、前記第一の層の開口部に露出し友前記半導
体基板の表面に抵抗性接触を得るために前記第二の金属
層と前記半導体基板とを合金化反応させる工程抵抗性接
触を得九前記第一の層の開口部を含む前記第二の金属層
表面に前記第一の層の開口部における段差によって生じ
る前記第二の金属層上の段差を緩和するように有機物よ
りなる第三の層を形成する工程、前記第三の層の表面と
前記第二の金属層と全同時に選択除去して、前記第一の
層の開口部のみに前記第二の金属層を残しかつ前記半導
体基板上の前記第二の金属層の厚さを薄くする工程、前
記第一の層を除去する工程とを含むことを特徴とする半
導体製電の製造方法が得られる。
According to the present invention, (11) forming a first layer made of an insulator entirely on a GaAs substrate, and then opening the first layer in a region where a resistive contact is to be formed to expose the GaAs substrate; depositing a second metal layer over the entire surface of the first layer including the openings in the first layer, the metal layer exposed in the openings in the first layer making resistive contact with the surface of the semiconductor substrate; In order to obtain a resistive contact, the second metal layer and the semiconductor substrate are subjected to an alloying reaction. a step of forming a third layer made of an organic material so as to alleviate a step difference on the second metal layer caused by a step difference in the second metal layer; selectively removing the surface of the third layer and the second metal layer at the same time; a step of leaving the second metal layer only in the opening of the first layer and reducing the thickness of the second metal layer on the semiconductor substrate; and a step of removing the first layer. There is obtained a method for manufacturing semiconductor electrical equipment, which is characterized by comprising the steps of:

〔作用〕[Effect]

本発明によればGaAs基板1表面に抵抗性接触を得る
とき金属層3を蒸着する前にホトレジスト4を除去し洗
浄を行なうため、清浄なGaAs基板1表面を得ること
ができるので接触抵抗率の再現性が極めて良い。また、
リフトオフ処理を行なわないので超音波洗浄工程におけ
る基板破壊を防ぐことができる。その上、8i0□膜2
の開口部でのみGaAs基板1と金属3とが合金化反応
するため、金属層3と他の金属層とがシ欝−卜すること
はない。さらに、GaAs基板1と金属層3との合金化
を行なったのちに有機化合物5 f GaAs基板1表
面に塗布し、平坦な表面全形成したのち、金属層3の厚
さかもとの厚さよりもうすくなるように5iOz膜2上
の不要な金属層3と有機化合物5を同時に除去すること
により第2図6のよう々突起がなくなる。
According to the present invention, when obtaining a resistive contact on the surface of the GaAs substrate 1, the photoresist 4 is removed and cleaned before the metal layer 3 is deposited, so that a clean surface of the GaAs substrate 1 can be obtained, thereby reducing the contact resistivity. Very good reproducibility. Also,
Since lift-off processing is not performed, substrate destruction during the ultrasonic cleaning process can be prevented. Moreover, 8i0□ membrane 2
Since the GaAs substrate 1 and the metal 3 undergo an alloying reaction only at the opening, the metal layer 3 and other metal layers are not damaged. Furthermore, after alloying the GaAs substrate 1 and the metal layer 3, an organic compound 5f is applied to the surface of the GaAs substrate 1 to form a flat surface, and the thickness of the metal layer 3 becomes smaller than the original thickness. By removing the unnecessary metal layer 3 and organic compound 5 on the 5iOz film 2 at the same time, the protrusions are eliminated as shown in FIG. 2.

また、GaAs基板1上の金属層3による段差を少なく
することができるため段差部での配線の断線は力い。
In addition, since the difference in level caused by the metal layer 3 on the GaAs substrate 1 can be reduced, disconnection of the wiring at the difference in level is prevented.

詳細を本発明の一実施例である第1図を用いて説明する
。第1図アに示すように8i02よりがる第一〇H1r
 2 ?形成したのち、ホトレジスト4t−塗布してパ
ターンを形成し、5i02膜2をエツチング除去して開
口部をつくる。次に第1図イに示すようにホトレジスト
4を除去したのち洗浄を打力い第二の金属層3を蒸着し
、合金化反応を行なう。このときホトレジスト4を除去
して蒸着を行なうので蒸着中にガスが発生しない。した
がって、抵抗性接触を得るGaA@基板1表面にガスが
付着して接触抵抗の増大をまねくという問題はおこらな
い。
Details will be explained using FIG. 1, which is an embodiment of the present invention. As shown in Figure 1A, the first 〇H1r is twisted by 8i02.
2? After the formation, a photoresist 4t is applied to form a pattern, and the 5i02 film 2 is etched away to form an opening. Next, as shown in FIG. 1A, after the photoresist 4 is removed, cleaning is performed, a second metal layer 3 is deposited, and an alloying reaction is performed. At this time, since the photoresist 4 is removed before vapor deposition, no gas is generated during vapor deposition. Therefore, the problem of gas adhering to the surface of the GaA@substrate 1 that provides resistive contact and causing an increase in contact resistance does not occur.

次に第1図つに示すように有機化合物よりなる第三の層
5t−塗布して熱処理し、表面を平坦圧する。第1図工
に示すように有機化合物5と有機化合物5と金属層3の
除去速度が同じまたは有機化合物5の方が遅(,8i0
2膜2が除去されないあるいは除去速度が有機化合物5
よりはるかにおそいようかエツチング条件を用いて開口
部以外の第一の層上の不要々金属層3と有機化合物5と
を同時に除去して、GaAs基板1上の金属層3の厚さ
をもとの厚さよりも薄くする(第1図才)。したがって
、突起6は力く力る。tた、龜As基板1上に段差のほ
とんどない平坦力表面を得ることができるので、段差部
での配線の断gAはないつまたSiへ膜2の開口部での
みGaAs基板1と金属層3との合金化反応がおこる几
め、金属層間のシーートは絶対におきかい。まt1合金
化反応を行なった後であるので金属層30表表面GaA
s基板1表面近くまで除去しても接触抵抗率には影響が
ない。金属層3以外のGaAs基板1表面tisich
膜2でおおわれているtめ、GaAl1基板1は有機化
合物5と金属層3とを除去する過程でエツチングによる
損傷を全く受は力い。以上の工程で前記のようが欠点は
なくかつ几。
Next, as shown in FIG. 1, a third layer 5t made of an organic compound is applied and heat treated, and the surface is flattened. As shown in Figure 1, the removal rates of organic compound 5, organic compound 5, and metal layer 3 are the same, or organic compound 5 is slower (,8i0
2 Film 2 is not removed or the removal rate is lower than organic compound 5.
The unnecessary metal layer 3 and organic compound 5 on the first layer other than the opening are simultaneously removed using etching conditions that are much slower, and the thickness of the metal layer 3 on the GaAs substrate 1 is also reduced. (Fig. 1). Therefore, the protrusion 6 exerts a strong force. In addition, since a flat surface with almost no steps can be obtained on the As substrate 1, there is no disconnection of the wiring at the step, and the gap between the GaAs substrate 1 and the metal layer is only at the opening of the Si film 2. In order for the alloying reaction with 3 to occur, the sheet between the metal layers must be large. Since this is after the t1 alloying reaction, the surface GaA of the metal layer 30 is
Even if it is removed close to the surface of the s-substrate 1, the contact resistivity is not affected. GaAs substrate 1 surface tisich other than metal layer 3
Since the GaAl1 substrate 1 is covered with the film 2, it is not damaged at all by etching during the process of removing the organic compound 5 and the metal layer 3. The above process has no drawbacks as described above.

〔実施例〕〔Example〕

次に本発明の一実施例を図面を参照して説明゛する。第
1図は、本発明の一実施例を示し九〇aAs基板に抵抗
性接触を得る工程を示す断面図である。
Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating an embodiment of the present invention and illustrating the process of obtaining resistive contact to a 90aAs substrate.

まず、8i0z膜3000AQ成長する。ガリウム−砒
素基板1にホトレジスト4を塗布して、パターンを形成
し、このホトレジスト4をマスクトシて8 i02膜2
を除去する(第1図ア)。
First, an 8i0z film of 3000AQ is grown. A photoresist 4 is applied to a gallium-arsenide substrate 1 to form a pattern, and this photoresist 4 is applied as a mask to form an i02 film 2.
(Figure 1 A).

次に、ホトレジスト4を除去してリン酸により洗浄を行
カー5次のち、AuGe*Ni 2000 A t”蒸
着し、合金化反応全行なう(第1図イ)。有機化合物s
 1ooooX、塗布し、熱処理することでほとんど平
坦4面が得られる(第1図つ)。CC4Ftガス中でエ
ツチングを行ない、不要な金属層3と有機化合物5とを
同時に除去し金属層3の厚さを薄くする(第1図工)。
Next, the photoresist 4 is removed and washed with phosphoric acid. After that, AuGe*Ni 2000A t" is deposited and the alloying reaction is carried out (Fig. 1A).Organic compound s
By applying 1ooooX and heat-treating, four almost flat surfaces can be obtained (Figure 1). Etching is performed in CC4Ft gas to remove unnecessary metal layer 3 and organic compound 5 at the same time to reduce the thickness of metal layer 3 (first drawing).

このときすでに合金化反応を行なっているので開口部内
の金属層3の表面をエツチングしても抵抗性接触に影響
はかい。
Since the alloying reaction has already taken place at this time, etching the surface of the metal layer 3 within the opening will not affect the resistive contact.

最後に弗酸を用いて5i02膜2を除去する(第1図才
)っ以上説明した実施例によれば、金属層3を蒸着する
前にホトレジスト4を完全に除去し之のち洗浄を行ない
蒸着を行なうため、抵抗性接触を得るGaAs基板1表
面の洗浄が十分に行なえる。
Finally, the 5i02 film 2 is removed using hydrofluoric acid (see Figure 1). According to the embodiment described above, the photoresist 4 is completely removed before the metal layer 3 is vapor deposited, and then cleaning is performed and the vapor deposition is performed. Therefore, the surface of the GaAs substrate 1 on which resistive contact is to be made can be sufficiently cleaned.

また、蒸着時にレジストよりガスが発生して抵抗性接触
を得るGaAs基板1表面て付着するということが彦く
なる几込抵抗の小さい再現性のよい抵抗性接触を得るこ
とができる。また、ホトレジスト4を用い友り7トオフ
が力いため、超音波洗浄工程での基板破壊がない。また
GaAs基板l基板屑層3との合金化反応はS io、
膜2の開口部でのみおこるので金属層3と他の金属層と
のシ霧−トハない。まt1金属層3の厚さかもとの厚さ
よりも薄くなるようにエツチングするので突起6はない
In addition, it is possible to obtain a resistive contact with a small indentation resistance and good reproducibility, since gas is generated from the resist during vapor deposition and is unlikely to adhere to the surface of the GaAs substrate 1 to obtain a resistive contact. Further, since the photoresist 4 is used and the photoresist 7 is strongly removed, the substrate is not destroyed in the ultrasonic cleaning process. In addition, the alloying reaction between the GaAs substrate and the substrate waste layer 3 is Sio,
Since this occurs only at the opening of the membrane 2, there is no atomization between the metal layer 3 and other metal layers. There are no protrusions 6 because the etching is performed so that the thickness of the metal layer 3 is thinner than the original thickness.

さらに、GaAs基板1上に金属層3による段差がすく
表るので平坦4面を得ることができる几め段差部での配
線断線はない。
Furthermore, since the step formed by the metal layer 3 is clearly visible on the GaAs substrate 1, there is no disconnection of wiring at the narrow step portion where four flat surfaces can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明し友ように、本発明は金属層3を蒸着する前に
レジストを完全に除去したのち洗浄を行ない蒸着を行か
うため、抵抗性接触を得るGaAs基板1表面の洗浄が
十分九行なえる。まt1蒸着時にホトレジスト4よりガ
スが発生して抵抗性接触を得るGaAs基板1表面に付
着するということがなくなる友め抵抗の小さい再現性の
よい抵抗性接触を得ることができる。また、ホトレジス
ト4を用いたりフトオフがかいため超音波洗浄工程での
基板破壊がなくなるので素意性が大幅に向上し友。また
、GaAs基板l基板屑層3の合金化反応はSin、膜
2の開口部でのみおこるので金属層3と他の金属層との
シ曽−トは全くおきない。さらに、合金化反応を行なっ
几のち、不要な金属層3のエツチングを行なっているの
で、接触抵抗率には影響を与えずに容易に突起6をなく
 L GaAs基板l上の金属層3による段差を緩和す
ることができる。
As explained above, in the present invention, before depositing the metal layer 3, the resist is completely removed and then the resist is cleaned and then the deposition is performed. Therefore, the surface of the GaAs substrate 1 to obtain resistive contact can be cleaned nine times. . Furthermore, gas is not generated from the photoresist 4 during the evaporation step 1 and adheres to the surface of the GaAs substrate 1 from which a resistive contact is obtained, so that a resistive contact with low resistance and good reproducibility can be obtained. In addition, since photoresist 4 is used and the foot-off is strong, there is no substrate destruction during the ultrasonic cleaning process, which greatly improves the cleanliness. Further, since the alloying reaction of the GaAs substrate 1 substrate waste layer 3 occurs only at the opening of the Sin film 2, no sheeting occurs between the metal layer 3 and other metal layers. Furthermore, since the unnecessary metal layer 3 is etched after performing the alloying reaction, the protrusion 6 can be easily removed without affecting the contact resistivity. can be alleviated.

々お、実施例では第1の層としてEHOt膜を適用し友
が、窒化シリコン膜におきかえても全く同様の効果が得
られる。!!た、金属層3FiAuGe−Niのみに固
定されるものでは々く、AuGe−Pt 、 AuGe
−AuAuGe−Ni −Au AuZnといった金属
でもよい。
Although the EHOt film is used as the first layer in the embodiment, the same effect can be obtained by replacing it with a silicon nitride film. ! ! In addition, the metal layer 3Fi is often fixed only to AuGe-Ni, and AuGe-Pt, AuGe
-AuAuGe-Ni -Au A metal such as AuZn may be used.

励 ν′ 4、図の簡単な説明 第1図ア〜オは本発明による一実施例を示し几GaAs
基板に抵抗性接触全得ろ工程を示す断面図。
Excitation ν' 4, Brief Description of the Figures Figures 1A to 1O show an embodiment according to the present invention.
FIG. 3 is a cross-sectional view showing the entire process of forming resistive contact on the substrate.

第2図ア、イ、第3図アルつは従来技術の工程全示した
GaAs基板の断面図。
Figures 2A and 3A are cross-sectional views of a GaAs substrate showing all the steps of the prior art.

l・・・ガリウム−砒素基板 2・・・第一の層 3・−・第二の金属層 4・・・ホトレジスト 5・・・第三の層 6・・・第二の金属層エツジ部の突起 7・・・ガリウム−砒素基板と、第二の金属層との合金
l...Gallium-arsenic substrate 2...First layer 3...Second metal layer 4...Photoresist 5...Third layer 6...Second metal layer edge portion Protrusion 7...Alloy layer of gallium-arsenic substrate and second metal layer

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に絶縁物よりなる第一の層を形成したのち
抵抗性接触を形成する領域に前記第一の層を開口して前
記半導体基板を露出する工程、前記第一の層の開口部を
含む前記第一の層表面全体に第二の金属層を被着する工
程、前記第一の層の開口部に露出した前記半導体基板の
表面に抵抗性接触を得るために前記第二の金属層と前記
半導体基板とを合金化反応させる工程抵抗性接触を得た
前記第一の層の開口部を含む前記第二の金属層表面に前
記第一の層の開口部における段差によつて生じる前記第
二の金属層上の段差を緩和するように有機物よりなる第
三の層を形成する工程、前記第三の層の表面と前記第二
の金属層とを同時に選択除去して、前記第一の層の開口
部のみに前記第二の金属層を残しかつ前記半導体基板上
の前記第二の金属層の厚さを薄くする工程、前記第一の
層を除去する工程とを含むことを特徴とする半導体装置
の製造方法。
forming a first layer made of an insulator on a semiconductor substrate, and then opening the first layer in a region where a resistive contact is to be formed to expose the semiconductor substrate; depositing a second metal layer over the entire surface of the first layer, the second metal layer to provide resistive contact to the surface of the semiconductor substrate exposed in the opening of the first layer; The step of alloying and reacting the semiconductor substrate with the second metal layer surface including the openings of the first layer that has obtained resistant contact due to the step difference in the openings of the first layer. a step of forming a third layer made of an organic substance so as to reduce the step difference on the second metal layer; selectively removing the surface of the third layer and the second metal layer at the same time; The method includes the steps of: leaving the second metal layer only in the opening of the layer and reducing the thickness of the second metal layer on the semiconductor substrate; and removing the first layer. A method for manufacturing a semiconductor device.
JP29111085A 1985-12-23 1985-12-23 Manufacture of semiconductor device Pending JPS62149138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29111085A JPS62149138A (en) 1985-12-23 1985-12-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29111085A JPS62149138A (en) 1985-12-23 1985-12-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62149138A true JPS62149138A (en) 1987-07-03

Family

ID=17764582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29111085A Pending JPS62149138A (en) 1985-12-23 1985-12-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62149138A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387548A (en) * 1992-06-22 1995-02-07 Motorola, Inc. Method of forming an etched ohmic contact
US5444016A (en) * 1993-06-25 1995-08-22 Abrokwah; Jonathan K. Method of making ohmic contacts to a complementary III-V semiconductor device
US5480829A (en) * 1993-06-25 1996-01-02 Motorola, Inc. Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts
US5606184A (en) * 1995-05-04 1997-02-25 Motorola, Inc. Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387548A (en) * 1992-06-22 1995-02-07 Motorola, Inc. Method of forming an etched ohmic contact
US5444016A (en) * 1993-06-25 1995-08-22 Abrokwah; Jonathan K. Method of making ohmic contacts to a complementary III-V semiconductor device
US5480829A (en) * 1993-06-25 1996-01-02 Motorola, Inc. Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts
US5606184A (en) * 1995-05-04 1997-02-25 Motorola, Inc. Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making

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