JPS62142334A - Formation of metallic pattern - Google Patents

Formation of metallic pattern

Info

Publication number
JPS62142334A
JPS62142334A JP60283995A JP28399585A JPS62142334A JP S62142334 A JPS62142334 A JP S62142334A JP 60283995 A JP60283995 A JP 60283995A JP 28399585 A JP28399585 A JP 28399585A JP S62142334 A JPS62142334 A JP S62142334A
Authority
JP
Japan
Prior art keywords
film
etching
metal
opening
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60283995A
Other languages
Japanese (ja)
Inventor
Bunji Hisamori
久森 文詞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP60283995A priority Critical patent/JPS62142334A/en
Publication of JPS62142334A publication Critical patent/JPS62142334A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make the inclination of an etching plane of an SiO2 film gentle by effecting a first etching to such degree that the etching reaches the middle of a layer and subjecting a photoresist film to a heat treatment to expand an opening of the photoresist, followed by the second etching. CONSTITUTION:On an SiO2 film 2 formed on a GaAs epitaxial wafer 1, a resist film 4 having an opening 3 is formed. Next, the etching of such degree that it reaches the middle of a layer is performed. After that, the wafer is subjected to a heat treatment of 130 deg.C for 30min to shrink the resist film 4 and to expand the opening 3. Then the etching of the SiO2 film is carried out again, so that an etching plane of the SiO2 film becomes to show an extremely gentle inclination. Subsequently, by depositing an Mo metal 5 over the whole surface of the wafer by vacuum vapor deposition, there is no gap produced between the SiO2 film 2 and the Mo metallic film 5 formed on the GaAs epitaxial wafer 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の電極配線などの金属パターンを
形成する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming metal patterns such as electrode wiring of semiconductor devices.

〔従来の技術〕[Conventional technology]

従来、ダイオード、トランジスタ、集積回路などの電極
配線の金属パターンを形成するさいには絶縁膜および金
属膜をホトエツチングして形成するホトエツチング法か
、または、レジストの溶解を利用するりフトオフ法が用
いられているが、リフトオフ法が、工程の削減、パター
ン形状の精度の点で優れており、広範囲に用いられてい
る。
Conventionally, when forming metal patterns for electrode wiring in diodes, transistors, integrated circuits, etc., a photo-etching method is used to photo-etch an insulating film and a metal film, or a lift-off method is used, which utilizes resist dissolution. However, the lift-off method is superior in terms of process reduction and pattern shape accuracy, and is widely used.

本発明はりフトオフ法による金属パターンの形成方法の
改良に関するもので、以下、 Mo金属を7ヨツトキー
金属に、 Al金属をボンディング金属とするGaAs
マイクロ波用シEl’/トキーノ(リアダイオードを例
に説明を行う。
The present invention relates to an improvement in the method of forming metal patterns by the beam lift-off method, and hereinafter, GaAs with Mo metal as the 7-Yotkey metal and Al metal as the bonding metal.
Explanation will be given using a rear diode as an example.

第2図は従来の金属パターン形成方法の一例を示す説明
図である。
FIG. 2 is an explanatory diagram showing an example of a conventional metal pattern forming method.

GaAsエビタキシャルウエノ・1上に、真空スパッタ
法により約6千オングストローム(X)の厚さの5i0
2膜2を形成し、5i02膜2上にホトリソグラフィー
法により直径約5マイクロメータ(μm)の開口部3を
持つレジスト膜4を形成する(第2図(a))。次に、
レジスト膜4をマス1; りAS I 02 m 2のホトエツチングを行い、 
GaAsエピタキシャルウェハ1の一部を露出する(第
2図(b))。次いで、真空蒸着法によりウェハ全面に
Mo金属膜5を付着させ(第2図(c) ) 、アセト
ン溶液でレジスト膜4を溶解し、レジスト膜4とともに
レジスト膜4上に付着したMo金属膜5を除去する。(
第2図(d)) 所定の領域にショア1−キー金属のMo金属膜5が形成
されたGaAsエピタキシャルウェハ1全面に真空蒸着
法によりAl金属を付着し、ホトエツチング法により付
着したAl金属の所定のパターン6以外の部分を除去す
ると(第2図tel ) 。
5i0 with a thickness of about 6,000 angstroms (X) was deposited on GaAs epitaxial Ueno-1 by vacuum sputtering.
A resist film 4 having an opening 3 having a diameter of about 5 micrometers (μm) is formed on the 5i02 film 2 by photolithography (FIG. 2(a)). next,
The resist film 4 is photo-etched with ASI 02 m 2 in a mass 1;
A part of the GaAs epitaxial wafer 1 is exposed (FIG. 2(b)). Next, a Mo metal film 5 is deposited on the entire surface of the wafer by vacuum evaporation (FIG. 2(c)), and the resist film 4 is dissolved in an acetone solution to remove the Mo metal film 5 deposited on the resist film 4 together with the resist film 4. remove. (
(Fig. 2(d)) Al metal is deposited on the entire surface of the GaAs epitaxial wafer 1 on which the Mo metal film 5 of the Shore 1 key metal is formed in a predetermined region by vacuum evaporation method, and the deposited Al metal is removed in a predetermined area by photoetching method. When parts other than pattern 6 are removed (Figure 2, tel).

ショットキーバリアダイオードの基本部分の形成が完了
する。
The formation of the basic part of the Schottky barrier diode is completed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の方法では、リフトオフに必要なレジ
ストの庇部分が確保されるまでS ioz膜2のエツチ
ングを進めていくとエツチングが初期には等方的に進む
が、レジスト下では、エツチングが進むほどエツチング
速度が遅くなるために、第2図(blに示すように、 
 5i02膜2のエツチング面のウェハ面に対する傾き
が急峻になり、 GaAsエピタキシアルウェハ1上に
形成したMo金属膜5とS ioz膜2の間に、第2図
(dlに示すような隙間7が生じ易いという問題があっ
た。
In the conventional method as described above, when etching of the Sioz film 2 is continued until the eaves of the resist necessary for lift-off is secured, the etching progresses isotropically at the beginning, but under the resist, the etching progresses in an isotropic manner. As the etching progresses, the etching speed becomes slower, so as shown in Figure 2 (bl),
The etched surface of the 5i02 film 2 has a steep slope with respect to the wafer surface, and a gap 7 is formed between the Mo metal film 5 formed on the GaAs epitaxial wafer 1 and the Sioz film 2 as shown in FIG. There was a problem that it was easy to occur.

この隙間は、 GaAsの露出部分の酸化による特性の
劣化をもたらすとともに1本来Mo金属膜5を形成すべ
きGaAs表面にボンディング金属のAl金属膜6が接
触することになり、ショットキー特性の劣化をもたらす
This gap causes deterioration of the characteristics due to oxidation of the exposed portion of GaAs, and also causes the Al metal film 6 of the bonding metal to come into contact with the GaAs surface on which the Mo metal film 5 should originally be formed, resulting in deterioration of the Schottky characteristics. bring.

同時に、 Al金属膜6に段差の大きい部分を発生させ
9表面の配線に段間ぎれが生ずる要因でもある。
At the same time, it is also a factor that causes large step differences to occur in the Al metal film 6, and gaps between steps in the wiring on the surface of the Al metal film 9.

首己 本発明は上→の問題を解消するためになされたもので、
 Mo金属膜5と5i02膜2の間に隙間の生じない方
法を提供することを目的とする。
The present invention was made to solve the above problems.
It is an object of the present invention to provide a method that does not create a gap between the Mo metal film 5 and the 5i02 film 2.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の方法は、最初のエツチングを1層の中間に達す
る程度に行い、ホトレジスト膜を熱処理してホトレジス
ト開口部を拡大し、再びエツチングを行うことによって
、  5i02 膜のエツチング面の傾きを緩やかにす
る方法である。
In the method of the present invention, the first etching is performed to reach the middle of one layer, the photoresist film is heat-treated to enlarge the photoresist opening, and the etching is performed again, thereby making the slope of the etched surface of the 5i02 film gentle. This is the way to do it.

〔実施例〕〔Example〕

第1図は本発明の金属パターン形成方法を示す説明図で
ある。
FIG. 1 is an explanatory diagram showing the metal pattern forming method of the present invention.

GaAsエピタキシャルウェハ1上に形成したS i0
2膜2上に開口部3を持つレジスト膜4を形成する(第
1図(a))。次に、開口部3のS i02膜2に対し
蝕刻が層の中間に達するエツチングを行う(第1図(b
))。
S i0 formed on GaAs epitaxial wafer 1
2. A resist film 4 having an opening 3 is formed on the film 2 (FIG. 1(a)). Next, the SiO2 film 2 in the opening 3 is etched to reach the middle of the layer (Fig. 1(b)).
)).

その後、ウェハをオープン中で130°C930分の熱
処理を行い、レジスト膜4を収縮させて開口部3を拡大
する(第1図(C))。開口部3を /拡大した後、再
度、 5i02膜2のエツチングを行うと、  5i0
2膜2のエツチング面は非常に緩やかな傾斜になる(第
1図(d))。
Thereafter, heat treatment is performed for 930 minutes at 130° C. while the wafer is open, thereby shrinking the resist film 4 and enlarging the opening 3 (FIG. 1(C)). After enlarging the opening 3, etching the 5i02 film 2 again results in 5i0
2 The etched surface of the film 2 has a very gentle slope (FIG. 1(d)).

次いで、真空蒸着法によりウェハ全面にMo金属5を付
着させると、 GaAsエピタキシアルウェハ1上に形
成されたMo金属膜5と5i02膜2の間に隙間ができ
ることがない(第1図(e))。
Next, when the Mo metal film 5 is deposited on the entire surface of the wafer by vacuum evaporation, there is no gap between the Mo metal film 5 formed on the GaAs epitaxial wafer 1 and the 5i02 film 2 (Fig. 1(e)). ).

この後は、従来の場合と同様に、アセトン溶液テレシス
ト膜4を溶解し、レジスト膜4とその上に付着したMo
金属膜5を除去しく第1図(f) ) 。
After this, as in the conventional case, the acetone solution telesist film 4 is dissolved, and the resist film 4 and the Mo attached thereon are dissolved.
The metal film 5 is removed (see FIG. 1(f)).

ホトエツチングによって残ったMo金属膜5を覆うAl
金属のパターン6を形成する(第1図(g))。
Al covering the Mo metal film 5 left by photoetching
A metal pattern 6 is formed (FIG. 1(g)).

〔発明の効果〕〔Effect of the invention〕

以上説明したとおり1本発明によれば9例えば、ショッ
トキーバリアダイオードの電極形成において、ショット
キー金属と5i02膜の間に隙間ができて特性の劣化を
もたらすという問題が解消され9歩留りが向上するとと
もに信頼性が向上するという効果がある。
As explained above, 1 According to the present invention, 9 For example, in the electrode formation of a Schottky barrier diode, the problem of a gap being formed between the Schottky metal and the 5i02 film, which causes deterioration of characteristics, is solved, and the yield is improved. This also has the effect of improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の金属パターン形成方法を示す説明図、
第2図は従来の金属パターン形成方法の一例を示す説明
図である。 1・・・GaAsエピタキシャルウニノー、2・・・5
i02膜、3・・・開口部、4・・・レジスト膜、5・
・・MO金属膜、6・・・Al金属膜。 特許出願人 新日本無線株式会社 第1[豪
FIG. 1 is an explanatory diagram showing the metal pattern forming method of the present invention,
FIG. 2 is an explanatory diagram showing an example of a conventional metal pattern forming method. 1...GaAs epitaxial Unino, 2...5
i02 film, 3... opening, 4... resist film, 5...
...MO metal film, 6...Al metal film. Patent applicant: New Japan Radio Co., Ltd. No. 1 [Australia]

Claims (1)

【特許請求の範囲】[Claims] 基板上に絶縁性の保護膜を形成する工程と、上記保護膜
上に形成するパターンに対応したホトレジスト膜を形成
する工程と、ホトレジスト開口部の保護膜の層の中間に
達するエッチングを行う工程と、前記ホトレジスト膜を
熱処理して上記ホトレジスト開口部を拡大する工程と、
拡大した前記ホトレジスト開口部の保護膜の層の底部に
達するエッチングを行う工程と、拡大した前記ホトレジ
スト開口部の保護膜を除去した領域にリフトオフ法によ
って金属パターンを形成する工程を備えたことを特徴と
する金属パターンの形成方法。
A step of forming an insulating protective film on the substrate, a step of forming a photoresist film corresponding to a pattern to be formed on the protective film, and a step of performing etching to reach the middle of the layer of the protective film at the photoresist opening. , enlarging the photoresist opening by heat-treating the photoresist film;
The present invention is characterized by comprising the steps of performing etching to reach the bottom of the protective film layer in the enlarged photoresist opening, and forming a metal pattern by a lift-off method in the region from which the protective film of the enlarged photoresist opening has been removed. A method for forming a metal pattern.
JP60283995A 1985-12-17 1985-12-17 Formation of metallic pattern Pending JPS62142334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60283995A JPS62142334A (en) 1985-12-17 1985-12-17 Formation of metallic pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60283995A JPS62142334A (en) 1985-12-17 1985-12-17 Formation of metallic pattern

Publications (1)

Publication Number Publication Date
JPS62142334A true JPS62142334A (en) 1987-06-25

Family

ID=17672924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60283995A Pending JPS62142334A (en) 1985-12-17 1985-12-17 Formation of metallic pattern

Country Status (1)

Country Link
JP (1) JPS62142334A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448159B1 (en) * 1998-06-03 2002-09-10 United Microelectronics Corporation Chemical mechanical polishing for forming a shallow trench isolation structure
US7037802B2 (en) 1998-06-03 2006-05-02 United Microelectronics Corporation Chemical mechanical polishing in forming semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448159B1 (en) * 1998-06-03 2002-09-10 United Microelectronics Corporation Chemical mechanical polishing for forming a shallow trench isolation structure
US7018906B2 (en) 1998-06-03 2006-03-28 United Microelectronics Corporation Chemical mechanical polishing for forming a shallow trench isolation structure
US7037802B2 (en) 1998-06-03 2006-05-02 United Microelectronics Corporation Chemical mechanical polishing in forming semiconductor device

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