JPH03227518A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the element characteristic without widening a pattern on an n-type active layer region by forming an insulator film between an electrode at the crossings of the electrode and mesa isolation steps and a semiconductor substrate. CONSTITUTION:An insulator film 1 and an n-type active layer region 2 are formed into one plane so that an electrode 3 may not break between the insulator film 1 and the n-type active layer region 2. All the steps are made of the insulator film 1. Therefore, the pattern of the Schottky electrode 3 does not need widening on the n-type active layer region 2. Thereby the element performance, especially the low-noise performance, is improved. Even if the electrode 3 slips vertically from its correct position, the wider pattern sections overlap less the n-type active layer region 2, therefore, the range of the tolerance of the overlap error of the Schottky electrode 3 is increased depending on the width W of the insulator film 1 and the pattern yield and performance yield are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices with mesa isolation.

Conventional technology As an example of conventional technology, GaAsMES
The structure that has been used in FET is shown in FIG. FIG. 3(a) is a plan view of the element. FIG. 3(b) shows a cross section cut along the center line C of FIG. 3(a). In FIG. 3, 2 is an n-type active layer region. 3 is a Schottky electrode, which functions as a gate electrode. 4 is an ohmic electrode, which functions as a source and drain electrode.

L is the pattern width of the electrode 3 and is the gate length of the FET.

A indicates a portion where the electrode 3 intersects with the mesa step. The pattern width (gate length>L) of the portion of the Schottky electrode 3 located above the n-type active layer region 2 is usually 1 μm or less. Therefore, the portion A where the Schottky electrode 3 crosses the mesa step.
The Schottky electrode is prone to breakage. To prevent this, the pattern width near A is widened as shown in FIG. 3(a).

Problems to be Solved by the Invention In GaAs MESFET, improving the device function,
In order to reduce device noise, it is necessary to shorten the gate length. In terms of improving device performance, it is not desirable to widen the gate pattern width of the mesa step portion A. This is because the noise generated near A in FIG. 3(a) significantly increases the noise figure.

Furthermore, in reality, due to an overlay error when overlapping the patterns of the Schottky electrode 3, the wide part of the pattern overlaps the n-type active layer region 2, further deteriorating the device performance.

If the pattern width of the Schottky electrode 3 near A is not widened, the yield will decrease due to disconnection. Especially high performance G
In aAsM ESFET, the gate length is approximately 0.25 to 0.35 μm, and it is difficult to prevent wire breakage without expanding the pattern width.

The conventional technology has the problems described above.

Means for Solving the Problems In order to solve the problems described above, in the present invention, an insulating film is provided between the electrode and the semiconductor substrate at the location where the mesa separation step and the electrode intersect. In order to prevent disconnection, the electrode has a structure in which the pattern width is widened on this insulating film.

By doing this, it is possible to form a portion on the insulating film in which the pattern width is expanded to prevent disconnection. This eliminates the need to widen the pattern width above the n-type active layer region, and improves device characteristics.

Embodiment FIG. 1 shows an embodiment of the present invention. Figure 1 is G a A
This is an example in which the present invention is applied to SMESFET. Figure 1(a) is a plan view of the element, Figure 1(b)
is a cross section cut along the center line C in FIG. 1(a).

In FIG. 1, ▪ is an insulating film, which is a silicon oxide film deposited by chemical vapor deposition. 2 is an n-type active layer region.

3 is a Schottky electrode which functions as a gate electrode of the MESFET. 4 is an ohmic electrode, one of which functions as a source electrode and the other as a drain electrode. 5 is a semi-insulating portion of the GaAs substrate exposed by etching. A indicates a portion where the step of the mesa pattern consisting of the n-type active layer region 2 and the electrode 3 intersect. L is the gate length.

W is the insulator pattern width. An insulator film 1 is formed at the step portion where the electrode 3 crosses. Therefore, the pattern of the electrode 3 is expanded on the insulating film 1 as shown in FIG. 1(a). In order to prevent disconnection of the electrode 3 between the n-type active layer region 2 and the insulator film 1, the insulator film 1 is placed on the same plane as the n-type active layer region 2, as shown in FIG. 1(b). Form it so that it becomes.

FIG. 2 shows a method for forming an insulator film. Figure 2(a).

(b>, (c) is a plan view, Fig. 2Cb), (d
) and (f) are cross-sectional views. Figure 2 (a), (
In b), a mesa isolation pattern is formed on the GaAs substrate. In FIGS. 2C and 2D, a silicon oxide film is deposited over the entire surface by chemical vapor deposition. At this time, by changing the deposition conditions and changing the cross-sectional shape of the silicon oxide film, the width W of the insulator pattern after subsequent etching can be changed.

In FIGS. 2(e) and 2(f), the silicon oxide film is etched until it becomes flush with the n-type active layer region 2 by reactive ion etching. Thereafter, electrodes are formed to obtain the structure shown in FIG.

Note that spin-on glass may be used as the insulator film. In this case, the shape of the insulator film can be changed by changing the rotation speed during coating.

In this way, the insulator film 1 is formed on the same plane as the n-type active layer region 2. Further, since all the step portions are formed of an insulating film, the pattern width of the Schottky electrode 3 does not need to be widened above the n-type active layer region 2. This improves device performance, especially low noise performance.

In addition, in FIG. 1(a), even if the electrode 3 is misaligned in the vertical direction, n
Since the overlap on the type active layer region 2 is reduced, the permissible Schottky electrode 3 is
The permissible range of overlay errors is widened. Furthermore, since the pattern width on the insulator film 1 does not affect the device performance,
The expansion width of part A can be made thicker than before.
Can prevent wire breakage. These improve pattern yield and performance yield.

Effects of the Invention According to the present invention, as described above, there is no need to widen the pattern width above the n-type active layer region, so that the device characteristics can be improved.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of an embodiment in which the present invention is applied to a GaAs MESFET, FIG. 1(b) is a sectional view taken along the center line C of FIG. 1(a), and FIG. 2(a) , (c)
, (e) is a plan view showing the insulator pattern forming method in the above embodiment, and FIGS. 2(b), (d), (T
) is its cross-sectional view, and Fig. 3(a) is the conventional GaAs
FIG. 3(b) is a plan view of an example of a structure that has been used in MESFET, and is a sectional view taken along the center line C in FIG. 3(a). DESCRIPTION OF SYMBOLS 1... Insulator film, 2... N-type active layer region, 3... Schottky electrode (gate), 4...
...Ohmic electrode (source, drain), 5.
... Semi-insulating substrate, A ... Pattern width expansion part (intersection with mesa step), C ... Center line, L ... Gate length, W...Insulator pattern width.

Claims (1)

[Claims] A semiconductor device characterized in that an insulating film is provided between the electrode and the semiconductor substrate at a location where the electrode intersects with a mesa separation step.