JPH10189606A - Bump of semiconductor device and manufacture thereof - Google Patents
Bump of semiconductor device and manufacture thereofInfo
- Publication number
- JPH10189606A JPH10189606A JP8343007A JP34300796A JPH10189606A JP H10189606 A JPH10189606 A JP H10189606A JP 8343007 A JP8343007 A JP 8343007A JP 34300796 A JP34300796 A JP 34300796A JP H10189606 A JPH10189606 A JP H10189606A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- film
- semiconductor device
- etching
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置のバン
プ構造及びその製造方法に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a bump structure of a semiconductor device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図２はかかる
従来の半導体装置のＡｕバンプ形成の工程断面図であ
る。 （１）まず、図２（ａ）に示すように、半導体基板１１
上にメタルパッド１２を形成し、半導体基板の全面に絶
縁膜１３（パッシベーション膜）形成後、１回のホトリ
ソ／エッチングによって、メタルパッド１２とＡｕバン
プとの接続孔を形成する。その後、半導体基板全面にス
パッタリング法により、Ａｕバンプ用バリアメタル等と
なる金属膜１４を形成する。2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there are the following. FIG. 2 is a sectional view showing a process of forming an Au bump of the conventional semiconductor device. (1) First, as shown in FIG.
After a metal pad 12 is formed thereon and an insulating film 13 (passivation film) is formed on the entire surface of the semiconductor substrate, a connection hole between the metal pad 12 and the Au bump is formed by one photolithography / etching. Thereafter, a metal film 14 serving as a barrier metal for an Au bump or the like is formed on the entire surface of the semiconductor substrate by a sputtering method.
【０００３】（２）次に、図２（ｂ）に示すように、メ
タルパッド１２上部に所望のバンプ径に相当する大きさ
にレジスト１５をパターニングし開孔する。次に、金属
膜１４を電解メッキの一方の電極として、その開孔部の
みに選択的にＡｕを析出させる。 （３）その後、図２（ｃ）に示すように、レジスト１５
を除去し、柱状Ａｕバンプ１６をマスクとして、パッド
上部以外の金属膜１４をエッチングすることにより、柱
状Ａｕバンプ１６を得る。(2) Next, as shown in FIG. 2B, a resist 15 is patterned on the metal pad 12 to a size corresponding to a desired bump diameter, and a hole is formed. Next, using the metal film 14 as one electrode of the electrolytic plating, Au is selectively deposited only in the opening. (3) Thereafter, as shown in FIG.
Is removed, and the metal film 14 other than the upper part of the pad is etched using the columnar Au bump 16 as a mask to obtain the columnar Au bump 16.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、以上し
た従来の半導体装置におけるＡｕバンプ形成方法では、
メタルパッド１２とＡｕバンプ１６との接続孔部の段差
が、パッシベーション膜１３の膜厚（８０００〜１００
００Å）程あるため、この段部でＡｕバンプ用バリアメ
タル１４が断切れを起こしバンプできなかったり、ま
た、Ａｕバンプ用バリアメタル１４のストレスによって
パッシベーション膜の破壊に至り、信頼性を低下させる
という問題があった。However, in the above-described conventional method for forming an Au bump in a semiconductor device,
The step in the connection hole between the metal pad 12 and the Au bump 16 depends on the thickness of the passivation film 13 (8000 to 100).
00Å), the Au bump barrier metal 14 is cut off at this step, making it impossible to bump, or the stress of the Au bump barrier metal 14 leads to the destruction of the passivation film, lowering the reliability. There was a problem.
【０００５】本発明は、上記問題点を除去し、被覆性の
悪さによって起こるバリアメタルの断線を防止するとと
もに、バリアメタル生成時、開孔部にストレスが集中す
るのを防止し、パッシベーション膜の破壊を防止するこ
とができる半導体装置のバンプ及びその製造方法を提供
することを目的とする。The present invention eliminates the above-mentioned problems, prevents breakage of the barrier metal caused by poor coverage, prevents stress from being concentrated on the opening when the barrier metal is formed, and improves the passivation film. An object of the present invention is to provide a bump of a semiconductor device and a method of manufacturing the bump, which can prevent destruction.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 〔１〕半導体装置のバンプにおいて、半導体基板上のメ
タルパッド上に階段状の接続孔を有する絶縁膜を設ける
ようにしたものである。 〔２〕半導体装置のバンプの製造方法において、半導体
基板上のメタルパッド上に形成される絶縁膜を、接続孔
の径の大きさの異なるマスクを複数枚用いて、複数回の
ホトリソエッチングにより、階段状に開孔するようにし
たものである。According to the present invention, in order to achieve the above object, [1] In a bump of a semiconductor device, an insulating film having a step-like connection hole is provided on a metal pad on a semiconductor substrate. It was made. [2] In a method of manufacturing a bump of a semiconductor device, an insulating film formed on a metal pad on a semiconductor substrate is subjected to photolithographic etching a plurality of times using a plurality of masks having different diameters of connection holes. The holes are formed in a stepwise manner.
【０００７】〔３〕上記〔２〕記載の半導体装置のバン
プの製造方法において、前記接続孔の径の大きさの異な
るマスクを２枚用意し、径の大きいマスクを用いた第１
回目のホトリソエッチングにより、前記絶縁膜の所定の
深さだけ除去し、次に、径の小さいマスクを用いた第２
回目のホトリソエッチングにより、前記絶縁膜の残りを
除去して前記絶縁膜を階段状に開孔するようにしたもの
である。[3] In the method for manufacturing a bump of a semiconductor device according to the above [2], two masks having different diameters of the connection holes are prepared, and the first mask using the larger diameter mask is used.
By a second photolithographic etching, a predetermined depth of the insulating film is removed, and then a second photolithography using a small-diameter mask is performed.
The remaining portion of the insulating film is removed by a second photolithographic etching to open the insulating film in a stepwise manner.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら詳細に説明する。図１は本発明の
第１実施例を示す半導体装置のＡｕバンプ形成の工程断
面図である。 （１）まず、図１（ａ）に示すように、半導体基板２１
上にメタルパッド２２を形成し、半導体基板の全面に保
護絶縁膜（パッシベーション膜）（８０００Å〜１００
００Å）２３を生成した後、メタルパッド２２とＡｕバ
ンプの接続のための接続孔の形成を行うが、この時、１
回目のホトリソ／エッチングで開孔部のパッシベーショ
ン膜を４０００Å〜５０００Å程エッチングする。すな
わち、完全にエッチングせず、１／２程度エッチング
し、パッシベーション膜２３を残す。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a process of forming an Au bump of a semiconductor device according to a first embodiment of the present invention. (1) First, as shown in FIG.
A metal pad 22 is formed thereon, and a protective insulating film (passivation film) (8000Å-100
00)), a connection hole for connecting the metal pad 22 and the Au bump is formed.
In the second photolithography / etching, the passivation film in the opening is etched to about 4000 to 5000 degrees. That is, the etching is not completely performed, but is performed by about １ ／ to leave the passivation film 23.
【０００９】（２）その後、図１（ｂ）に示すように、
１回目の開孔径よりも内側にホトリソ／エッチングを施
し、階段状に開孔する。 （３）次に、図１（ｃ）に示すように、半導体基板全面
にスパッタリング法により、Ａｕバンプ用バリアメタル
等となる金属膜２４を形成する。 （４）次に、メタルパッド２２上部に所望のバンプ径に
相当する大きさにレジスト（図示なし）をパターニング
し開孔した後、金属膜２４を電解メッキの一方の電極と
してその開孔部のみに選択的にＡｕを析出させる。その
後、図１（ｄ）に示すように、レジスト（図示なし）を
除去して、Ａｕバンプ２５を得る。(2) Thereafter, as shown in FIG.
Photolithography / etching is performed on the inner side of the first opening diameter, and the holes are opened stepwise. (3) Next, as shown in FIG. 1C, a metal film 24 serving as a barrier metal for an Au bump is formed on the entire surface of the semiconductor substrate by a sputtering method. (4) Next, a resist (not shown) is patterned and opened to a size corresponding to a desired bump diameter on the metal pad 22. Then, the metal film 24 is used as one electrode of electrolytic plating and only the opening is formed. To selectively deposit Au. Thereafter, as shown in FIG. 1D, the resist (not shown) is removed to obtain an Au bump 25.
【００１０】このように、第１実施例では、メタルパッ
ド上部開孔のためのホトリソ／エッチングをそれぞれ２
回しか行っていないが、３回以上行ってもよい。図３は
本発明の第２実施例を示す半導体装置のＡｕバンプ形成
の要部工程断面図である。 （１）まず、図３（ａ）に示すように、半導体基板３１
上にメタルパッド３２を形成し、半導体基板の全面に保
護絶縁膜（パッシベーション膜）（９０００Å〜１２０
００Å）３３を生成した後、メタルパッド３２とＡｕバ
ンプの接続のための接続孔の形成を行うが、この時、１
回目のホトリソ／エッチングで開孔部のパッシベーショ
ン膜を３０００Å〜４０００Å程エッチングする。すな
わち、１／３程度エッチングし、パッシベーション膜３
３を残す。As described above, in the first embodiment, the photolithography and the etching for opening the upper portion of the metal pad are each performed by two times.
It is performed only once, but may be performed three or more times. FIG. 3 is a cross-sectional view of a main step of forming an Au bump of a semiconductor device according to a second embodiment of the present invention. (1) First, as shown in FIG.
A metal pad 32 is formed thereon, and a protective insulating film (passivation film) (9000 ° to 120 °) is formed on the entire surface of the semiconductor substrate.
00Å) After the formation of 33, a connection hole for connecting the metal pad 32 and the Au bump is formed.
In the second photolithography / etching, the passivation film at the opening is etched to about 3000 to 4000 degrees. That is, the passivation film 3 is etched about 1/3.
Leave 3.
【００１１】（２）次に、図３（ｂ）に示すように、残
されたパッシベーション膜３３の接続孔に更に段を設け
るために、１回目のホトリソ／エッチングで開孔部の内
側のパッシベーション膜を、第２回目のホトリソ／エッ
チングで、更に１／３程度エッチングし、段階状の開孔
部を形成する。 （３）次に、図３（ｃ）に示すように、２回目のホトリ
ソ／エッチングによる開孔径よりも内側に、第３回目の
ホトリソ／エッチングを施し、完全に開孔部を形成する
とともに、３階段状に開孔する。(2) Next, as shown in FIG. 3 (b), in order to further provide a step in the connection hole of the remaining passivation film 33, passivation inside the opening is performed by the first photolithography / etching. The film is further etched about 1/3 by the second photolithography / etching to form a stepped opening. (3) Next, as shown in FIG. 3 (c), a third photolithography / etching process is performed on the inner side of the hole diameter by the second photolithography / etching process to completely form an opening portion. Open in three steps.
【００１２】（４）次に、図３（ｄ）に示すように、半
導体基板全面にスパッタリング法により、Ａｕバンプ用
バリアメタル等となる金属膜３４を形成する。以降は第
１実施例で示した技術によってＡｕバンプを形成する。
図４は本発明の第３実施例を示す半導体装置のＡｕバン
プ形成の要部工程断面図である。(4) Next, as shown in FIG. 3D, a metal film 34 serving as a barrier metal for Au bumps is formed on the entire surface of the semiconductor substrate by sputtering. Thereafter, Au bumps are formed by the technique described in the first embodiment.
FIG. 4 is a cross-sectional view of a main step of forming an Au bump of a semiconductor device according to a third embodiment of the present invention.
【００１３】（１）まず、図４（ａ）に示すように、半
導体基板４１上にメタルパッド４２を形成し、半導体基
板の全面に保護絶縁膜（パッシベーション膜）（８００
０Å〜１００００Å）４３を生成した後、メタルパッド
４２とＡｕバンプの接続のための接続孔の形成を行う。
つまり、１回目のホトリソ／エッチングで完全に開孔部
を形成する。(1) First, as shown in FIG. 4A, a metal pad 42 is formed on a semiconductor substrate 41, and a protective insulating film (passivation film) (800) is formed on the entire surface of the semiconductor substrate.
(0 ° to 10000 °) 43 is formed, and a connection hole for connecting the metal pad 42 and the Au bump is formed.
That is, the opening is completely formed by the first photolithography / etching.
【００１４】（２）次に、図４（ｂ）に示すように、そ
の後、１回目のホトリソ／エッチングによる開孔部より
外側に、２回目のホトリソ／エッチングで４０００Å〜
５０００Å程パッシベーション膜４３をエッチングし、
階段状に開孔する。 （３）次に、図４（ｃ）に示すように、半導体基板全面
にスパッタリング法により、Ａｕバンプ用バリアメタル
等となる金属膜４４を形成する。(2) Next, as shown in FIG. 4 (b), after the first photolithography / etching, the outer side of the opening is formed at a temperature of 4,000 ° C. by the second photolithography / etching.
Etch the passivation film 43 by about 5000 °
Open in steps. (3) Next, as shown in FIG. 4C, a metal film 44 to be a barrier metal for Au bumps or the like is formed on the entire surface of the semiconductor substrate by a sputtering method.
【００１５】以降は第１実施例で示した技術によってＡ
ｕバンプを形成する。また、上記したように、開孔の順
番も外側、内側のどちらからでもよい。エッチングの条
件は、内側から先に穴を開ける場合の第２回目のエッチ
ングは、第１回目のエッチングでの穴の形状の変化を防
ぐ意味から異方性エッチングを行うことが望ましいが、
その他のエッチングにおいては、異方性エッチング、等
方性エッチングのいずれを採用してもよい。Thereafter, A is determined by the technique shown in the first embodiment.
A u bump is formed. Further, as described above, the opening order may be either from the outside or the inside. As for the etching conditions, it is desirable to perform anisotropic etching for the second etching in the case where a hole is formed first from the inside in order to prevent a change in the shape of the hole in the first etching.
In other etchings, either anisotropic etching or isotropic etching may be employed.
【００１６】さらに、Ａｕバンプの形成について述べた
が、電気めっきが可能な材料であれば、これに限定され
るものではない。このように、本発明によれば、パッド
上の絶縁膜の開孔部を階段状に形成するようにしたの
で、メタルパッドとバンプの接続部の段差が、従来構造
よりも低減されたことにより、被覆性の悪さによって
起こるバリアメタルの断線を防止することができる。
バリアメタル生成時の開孔部にストレスが集中するのを
防止し、パッシベーション膜の破壊を防止することがで
きる。Furthermore, although the formation of the Au bump has been described, the material is not limited to this as long as it can be electroplated. As described above, according to the present invention, since the opening of the insulating film on the pad is formed in a step shape, the step between the connection portion between the metal pad and the bump is reduced as compared with the conventional structure. In addition, disconnection of the barrier metal caused by poor coverage can be prevented.
It is possible to prevent stress from being concentrated on the opening at the time of forming the barrier metal, and to prevent the destruction of the passivation film.
【００１７】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【００１８】[0018]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）半導体装置のバンプの形成の際、被覆性の悪さに
よって起こるバリアメタルの断線を防止することができ
る。As described above, according to the present invention, the following effects can be obtained. (1) In forming a bump of a semiconductor device, disconnection of a barrier metal caused by poor coverage can be prevented.
【００１９】（２）バリアメタル生成時の開孔部にスト
レスが集中するのを防止し、パッシベーション膜の破壊
を防止することができる。(2) It is possible to prevent stress from being concentrated on the opening at the time of generation of the barrier metal, and to prevent destruction of the passivation film.
【図１】本発明の第１実施例を示す半導体装置のＡｕバ
ンプ形成の工程断面図である。FIG. 1 is a sectional view showing a process of forming an Au bump of a semiconductor device according to a first embodiment of the present invention.
【図２】従来の半導体装置のＡｕバンプ形成の工程断面
図である。FIG. 2 is a cross-sectional view illustrating a process of forming an Au bump of a conventional semiconductor device.
【図３】本発明の第２実施例を示す半導体装置のＡｕバ
ンプ形成の要部工程断面図である。FIG. 3 is a cross-sectional view of a main part step of forming an Au bump of a semiconductor device according to a second embodiment of the present invention.
【図４】本発明の第３実施例を示す半導体装置のＡｕバ
ンプ形成の要部工程断面図である。FIG. 4 is a cross-sectional view of a main part step of forming an Au bump of a semiconductor device according to a third embodiment of the present invention.
２１，３１，４１ 半導体基板 ２２，３２，４２ メタルパッド ２３，３３，４３ 保護絶縁膜（パッシベーション
膜） ２４，３４，４４ 金属膜（バリアメタル） ２５ Ａｕバンプ21, 31, 41 Semiconductor substrate 22, 32, 42 Metal pad 23, 33, 43 Protective insulating film (passivation film) 24, 34, 44 Metal film (barrier metal) 25 Au bump
Claims (3)
る絶縁膜を具備することを特徴とする半導体装置のバン
プ。1. A bump for a semiconductor device, comprising: an insulating film having a step-like connection hole on a metal pad on a semiconductor substrate.
て、 半導体基板上のメタルパッド上に形成される絶縁膜を、
接続孔の径の大きさの異なるマスクを複数枚用いて、複
数回のホトリソエッチングにより、階段状に開孔するこ
とを特徴とする半導体装置のバンプの製造方法。2. A method of manufacturing a bump of a semiconductor device, comprising: forming an insulating film on a metal pad on a semiconductor substrate;
A method of manufacturing a bump for a semiconductor device, wherein a plurality of masks having different diameters of connection holes are used, and a plurality of photolithographic etchings are performed to form holes in a stepwise manner.
造方法において、前記接続孔の径の大きさの異なるマス
クを２枚用意し、径の大きいマスクを用いた第１回目の
ホトリソエッチングにより、前記絶縁膜を所定の深さだ
け除去し、次に、径の小さいマスクを用いた第２回目の
ホトリソエッチングにより、前記絶縁膜の残りを除去し
て前記絶縁膜を階段状に開孔することを特徴とする半導
体装置のバンプの製造方法。3. The method for manufacturing a bump of a semiconductor device according to claim 2, wherein two masks having different diameters of said connection holes are prepared, and a first photolithographic etching using the mask having a larger diameter is performed. Then, the insulating film is removed by a predetermined depth, and then the remaining insulating film is removed by a second photolithographic etching using a small-diameter mask to open the insulating film stepwise. A method for manufacturing a bump of a semiconductor device, characterized by forming holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8343007A JPH10189606A (en) | 1996-12-24 | 1996-12-24 | Bump of semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8343007A JPH10189606A (en) | 1996-12-24 | 1996-12-24 | Bump of semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10189606A true JPH10189606A (en) | 1998-07-21 |
Family
ID=18358223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8343007A Withdrawn JPH10189606A (en) | 1996-12-24 | 1996-12-24 | Bump of semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10189606A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6599822B1 (en) * | 1998-09-30 | 2003-07-29 | Micron Technology, Inc. | Methods of fabricating semiconductor substrate-based BGA interconnection |
| US6818539B1 (en) | 1999-06-30 | 2004-11-16 | Seiko Epson Corporation | Semiconductor devices and methods of fabricating the same |
| JP2007035875A (en) * | 2005-07-26 | 2007-02-08 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
| US7728431B2 (en) | 2006-06-15 | 2010-06-01 | Sony Corporation | Electronic component, semiconductor device employing same, and method for manufacturing electronic component |
-
1996
- 1996-12-24 JP JP8343007A patent/JPH10189606A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6599822B1 (en) * | 1998-09-30 | 2003-07-29 | Micron Technology, Inc. | Methods of fabricating semiconductor substrate-based BGA interconnection |
| US6646286B1 (en) | 1998-09-30 | 2003-11-11 | Micron Technology, Inc. | Semiconductor substrate-based BGA interconnection |
| US6740578B2 (en) | 1998-09-30 | 2004-05-25 | Micron Technology, Inc. | Methods of fabricating semiconductor substrate-based BGA interconnections |
| US7061109B2 (en) | 1998-09-30 | 2006-06-13 | Micron Technology, Inc. | Semiconductor substrate-based BGA interconnection for testing semiconductor devices |
| US7126224B2 (en) | 1998-09-30 | 2006-10-24 | Micron Technology, Inc. | Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements |
| US6818539B1 (en) | 1999-06-30 | 2004-11-16 | Seiko Epson Corporation | Semiconductor devices and methods of fabricating the same |
| US7285863B2 (en) | 1999-06-30 | 2007-10-23 | Seiko Epson Corporation | Pad structures including insulating layers having a tapered surface |
| JP2007035875A (en) * | 2005-07-26 | 2007-02-08 | Seiko Epson Corp | Semiconductor device and its manufacturing method |
| US7728431B2 (en) | 2006-06-15 | 2010-06-01 | Sony Corporation | Electronic component, semiconductor device employing same, and method for manufacturing electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5403777A (en) | Semiconductor bond pad structure and method | |
| JPH0982804A (en) | Semiconductor device and manufacture thereof | |
| JPH04229618A (en) | Integrated circuit device contact and formation method thereof | |
| JPH10189606A (en) | Bump of semiconductor device and manufacture thereof | |
| JPS6379347A (en) | Manufacture of semiconductor device | |
| JPH10177969A (en) | Semiconductor device and its manufacturing method | |
| JP2950045B2 (en) | Method for manufacturing semiconductor device | |
| JP2808674B2 (en) | Method for manufacturing semiconductor device | |
| KR930008868B1 (en) | Semicondcutor device having multilayer interconnection structure and method of manufacturing the same | |
| US20020048942A1 (en) | Method of manufacturing semiconductor device with two step formation of contact hole | |
| JP2644079B2 (en) | Semiconductor integrated circuit | |
| JPH04217324A (en) | Manufacture of semiconductor device | |
| JPS62136857A (en) | Manufacture of semiconductor device | |
| JP2734881B2 (en) | Method for manufacturing semiconductor device | |
| JPH05218212A (en) | Manufacture of semiconductor device | |
| JPH1197536A (en) | Semiconductor device and its manufacture | |
| JPS6362104B2 (en) | ||
| JPS6123322A (en) | Manufacture of semiconductor device | |
| JPS63287034A (en) | Semiconductor device | |
| JPH04350940A (en) | Manufacture of semiconductor device | |
| JPS6085542A (en) | Manufacture of semiconductor device | |
| JPH0645453A (en) | Manufacture of semiconductor device | |
| JPH04296030A (en) | Manufacture of semiconductor device | |
| JPH04337631A (en) | Manufacture of semiconductor device | |
| JPH06112209A (en) | Production of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040302 |