JP2950045B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a metal wiring.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described below with reference to FIG. FIG. 3 is a sectional view in the order of steps showing a conventional technique corresponding to the present invention. An electrical insulating film 2 is formed on a semiconductor substrate 1 and a reactive ion etching method (hereinafter referred to as RI
After that, the first and second metal films 3 and 4 are sequentially deposited by sputtering. The first metal film 3 is made of Ti, T
One of iW and Cr, and the second metal film 4 are deposited with a thickness of 30 to 100 nm using Ni, Cu, Pt or Au in consideration of barrier properties and plating properties. The first and second metal films 3 and 4 serve as power supply layers for electrolytic plating described later. Next, a predetermined region is opened using the photoresist 5. As described above, FIG.
The structure shown in FIG.

Thereafter, a metal wiring 6 made of gold is formed to a thickness of 0.5 to 2.0 μm by electrolytic plating, and FIG.
The structure shown in (b) is obtained.

Next, after the photoresist 5 is removed, the first and second metal films 3 and 4 are sequentially removed by RIE using the metal wiring 6 as a mask to obtain a structure shown in FIG.

[0005]

SUMMARY OF THE INVENTION In the conventional manufacturing method,
The controllability of the film thickness of the metal wiring 6 is poor, and in particular, when there is a difference in the cross-sectional area of the region where the metal wiring is to be formed as in the two openings shown in FIG. As a result, as shown in FIG. 3 (c), it appears as a film thickness difference, and the cross-sectional shape becomes an umbrella shape, making it difficult to planarize in a later process. There was a drawback that it easily occurred.

Although there is a method of increasing the thickness of the photoresist 5 to about 2.0 μm in order to prevent the sectional shape from becoming umbrella-shaped, it is impossible to reduce the difference in film thickness due to the difference in sectional area. Since a thick resist is used, there is a problem that formation of a fine pattern becomes difficult.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a metal wiring is formed by using an electrolytic plating method. It is an object of the present invention to provide a manufacturing method for reducing the amount of light.

[0008]

According to a method of manufacturing a semiconductor device of the present invention, a first and a second metal layer are formed on a semiconductor substrate including an insulating film covering the semiconductor substrate and an opening provided in the insulating film. Forming a second insulating film, a third metal film, and a fourth metal film on the first metal film and the third metal film in this order.
Forming a hole in a predetermined region through the metal film and the second insulating film, forming a metal wiring in a region where the second metal film is exposed, and using the metal wiring as a mask, the third and fourth metal films And a step of removing the second insulating film.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device shown in the order of steps for explaining a first embodiment of the present invention.

A first insulating film 7 such as an oxide film is formed on a semiconductor substrate 1 and a hole is formed by RIE using a patterned photoresist as a mask. Then, the photoresist is removed and the surface is opened. A first and a second metal film 3,
4 are sequentially deposited by a sputtering method. First metal film 3
Is 50 to 50 of Ti, TiW, Cr, etc., which have good adhesion to the insulating film.
The second metal film 4 is made of a metal having good plating properties and good barrier properties, such as Cu, Pt, Ni, Au, etc., in a thickness of 30 to 100 nm.
It is used with a thickness of nm. Here, the first and second metal films 3 and 4
May be a single layer as long as adhesion, plating and barrier properties are satisfied. The first and second metal films 3 and 4 are used as power supply layers for electrolytic plating. Next, as the second insulating film 8, silicon dioxide is formed to a thickness of 1.0 to 2.0 μm by a chemical vapor deposition method.
After the formation, the second metal films 11 and 12 are deposited by a sputtering method, and then holes are formed in the third and fourth metal films 9 and 10 and the second insulating film 8 using the patterned photoresist as a mask. Then, the photoresist is removed to obtain the structure shown in FIG. The third and fourth metal films 9 and 10 are film types,
The film thickness is the same as the first and second metal films 3 and 4.

Next, using the first and second metal films 3 and 4 as a power supply layer, a metal wiring 6 made of Au is formed by an electrolytic plating method to obtain a structure shown in FIG. 1B.

Thereafter, the metal wiring 6 on the fourth metal film 10 is formed.
And the third and fourth metal films 9 and 10 are sequentially removed by RIE. Ar as an etching gas,
A combination of O ₂ , Ne, SF ₆ , C ₂ Cl ₂ F _{4 and the} like is selected according to the type of metal. Next, the second insulating film 8 is removed with a hydrofluoric acid buffer, and the first and second metal films 3 and 4 are removed by RIE in the same manner as the third and fourth metal films 9 and 10. The structure shown in (c) is obtained.

The effect of the first embodiment is shown in FIG.
An advantage of the present invention is that the difference in Au plating film thickness caused by the depth of the openings, such as the openings A, B11, and 12 shown in FIG. Since the opening A11 is deeper than the opening B12, in the conventional technique, the opening B12 reaches a desired plating film thickness earlier. However, according to the present invention, when the plating film comes into contact with the third metal film 9, the area of the metal serving as the plating electrode is increased by the third and fourth metal films 9 located on the side of the opening B 12. 10, the surface area is increased to increase the plating rate. Therefore, even if the plating film of the opening B reaches the second metal film 10 first, the plating rate of the opening A does not decrease because the plating film does not reach the third metal film 9, and the plating rate does not decrease. Opening A11 and opening B12
Can be reduced.

FIG. 2 is a sectional view of a semiconductor device shown in the order of steps for explaining a second embodiment of the present invention. Since the second embodiment has many common parts with the first embodiment, only characteristic manufacturing methods and effects will be described.

After completing the steps of sputtering and depositing the third and fourth metal films 9 and 10 in the same manner as in the first embodiment (FIG. 2A), the third metal film 9 and 10 are patterned using the patterned photoresist as a mask. , A predetermined region of the fourth metal film 9, 10
Removed by IE method. In the above-described removal, the surface of the second insulating film 8 is more exposed at the ends of the third and fourth metal films 9 and 10 facing the opening A11. Subsequently, the photoresist 5 is removed, and the photoresist 5 is opened (FIG. 2B).

Next, using the photoresist 5 as a mask, RI
When a predetermined region of the second insulating film 8 is removed by the E method, the third and fourth metal films 9 and 10, the second insulating film, and the first and second metal films 9 and 10 are removed.
The metal films 3 and 4 are arranged stepwise facing the opening A11 (FIG. 2C). In the subsequent electrolytic plating, the opening A11 is plated to be 10 to 50 nm thicker than the second insulating film 8 and the opening B12 is thicker than the fourth metal film 10 by about 10 to 50 nm (FIG. 2D).

After that, the metal film on the outside of the opening is removed by RIE to remove the second insulating film 8 with a hydrofluoric acid buffer solution to obtain the structure shown in FIG.

As described above, the unique effect of the second embodiment is that the ends of the third and fourth metal films 9 and 10 facing the opening A11 having the deep groove are patterned so as to be farther from the opening A11. By doing so, the time until the plating film of the opening A11 comes into contact with the third metal film 9 and the plating rate starts to decrease becomes longer, so that the deeper opening than in the first embodiment is performed. The difference in plating film thickness between the hole and the shallow hole can be reduced.

[0019]

As described above, according to the present invention, by providing a metal film on the uppermost portion of the insulating film separating the wiring region, a plating electrode is formed when the plating film reaches the contact with this metal film. The area of the metal increases and the plating rate decreases. Therefore, the controllability of the film thickness can be improved without lowering the average plating rate.

Further, the deeper the hole, the longer the time until the plating rate decreases, so that the difference in plating film thickness caused by the difference in the depth of the hole can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device shown in a process order for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor element shown in order of steps for describing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 insulating film 3 first metal film 4 second metal film 5 photoresist 6 metal wiring 7 first insulating film 8 second insulating film 9 third metal film 10 fourth metal film 11 open Hole A 12 Opening B

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/3205 H01L 21/3213 H01L 21/44-21/445 H01L 21 / 768 H01L 29/40-29/51

Claims (3)

(57) [Claims] A step of forming a first insulating film on the semiconductor substrate; a step of selectively forming a first opening in the first insulating film; Forming a first and a second metal film in the opening in an overlapping manner, forming a second insulating film on the second metal film, and forming a third and a fourth film on the second insulating film; Forming a metal film in an overlapping manner;
Selectively providing a second opening in the fourth metal film and the second insulating film; and selectively forming a metal wiring on the second metal film exposed by the second opening. Selectively removing portions of the first and second metal films other than the third and fourth metal films, the second insulating film, and the metal wiring region in alignment with the metal wiring. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the metal wiring is formed by an electrolytic plating method. 3. The method according to claim 1, wherein the metal wiring is an Au wiring.
The third metal film is one or more metal layers or alloy layers selected from TiW, Ti, and Cr,
2. The method according to claim 1, wherein the metal film is at least one metal layer or an alloy layer selected from Pt, Pd, Au, Ni, and Cu.