JPS59126636A - Formation of microscopic pattern on semiconductor substrate - Google Patents
Formation of microscopic pattern on semiconductor substrateInfo
- Publication number
- JPS59126636A JPS59126636A JP314283A JP314283A JPS59126636A JP S59126636 A JPS59126636 A JP S59126636A JP 314283 A JP314283 A JP 314283A JP 314283 A JP314283 A JP 314283A JP S59126636 A JPS59126636 A JP S59126636A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- pattern
- semiconductor substrate
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 56
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 11
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000460 chlorine Substances 0.000 claims abstract description 9
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 9
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 239000011261 inert gas Substances 0.000 claims abstract description 9
- 238000001020 plasma etching Methods 0.000 claims abstract description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 15
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 150000001485 argon Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- FZUJWWOKDIGOKH-UHFFFAOYSA-N sulfuric acid hydrochloride Chemical compound Cl.OS(O)(=O)=O FZUJWWOKDIGOKH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体集積回路装置（ＩＣ）などの製造工程
において半導体基板の主面部に微細パターンを形成する
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a fine pattern on the main surface of a semiconductor substrate in the manufacturing process of a semiconductor integrated circuit device (IC) or the like.
ＩＣの製造工程において半導体基板の主面部に所望のパ
ターンを形成する場合には、半導体基板の主面上に、こ
の主面部に形成すべき所望のパターンに対応するパター
ンを有するエツチングマスク用のレジスト膜を形成し、
このレジスト膜をマスクにしたエツチングによって、上
記半導体基板の主面部に上記レジスト膜のパターンに対
応するパターンを形成する方法が従来から広く用いられ
ている。When forming a desired pattern on the main surface of a semiconductor substrate in the IC manufacturing process, a resist for an etching mask having a pattern corresponding to the desired pattern to be formed on the main surface of the semiconductor substrate is used. form a film,
Conventionally, a method has been widely used in which a pattern corresponding to the pattern of the resist film is formed on the main surface of the semiconductor substrate by etching using the resist film as a mask.
近年、工Ｃの集・積度の増大にともなって、半導体基板
の主面部に形成されるパターンの微細化およびパターン
精度の向上がより一層要求されるようになってきた。と
ころで、上述の従来の方法では、半導体基板の主面部に
形成されるパターンの微細化を図るためには、エツチン
グマスク用のレジスト膜の膜厚を薄くして、レジスト膜
のパターンを微細化する必要がある。しかし、レジスト
膜の膜厚を薄くした場合には、最近、開発が進んでｂる
サイドエツチングの少ないプラズマエツチング。In recent years, with the increase in the concentration and integration of manufacturing processes, there has been a growing demand for finer patterns and improved pattern precision to be formed on the main surface of semiconductor substrates. By the way, in the conventional method described above, in order to miniaturize the pattern formed on the main surface of the semiconductor substrate, the thickness of the resist film for an etching mask is made thinner, and the pattern of the resist film is miniaturized. There is a need. However, when reducing the thickness of the resist film, plasma etching, which causes less side etching, has recently been developed.
イオンビームエツチングなどのドライエツチングでは、
エツチング時のイオン衝撃によってレジスト膜の膜厚が
１０００Ａ／ｍｉｎの速度で除去されるので、レジスト
膜のパターン精度の維持がむづかしく、半導体基板の主
面部に微細パターンをＭ度よく形成する仁とけ容易でば
ないという問題があった。In dry etching such as ion beam etching,
Because the thickness of the resist film is removed at a rate of 1000 A/min by ion bombardment during etching, it is difficult to maintain the pattern accuracy of the resist film, and it is difficult to maintain the pattern accuracy of the resist film. There was a problem that it was not easy to melt.
この発明は、かかる問題を改善する目的でなされたもの
で、半導体基板の主面上に、この主面部に形成すべき所
望のパターンに対応するパターンを有し塩素を含む化合
物のプラズマによってエツチング時れかつ不活性ガスの
イオンビームによるエツチング速度がレジスト膜のエツ
チング速度より小さｂ金属膜を形成し、この金属膜をマ
スクにしたイオンビームエツチングによって、半導体基
板の主面部に微細パターンを精度よく形成できるように
した方法を提供するものである。The present invention has been made for the purpose of improving this problem, and has a pattern on the main surface of a semiconductor substrate corresponding to a desired pattern to be formed on the main surface, and is etched by plasma of a compound containing chlorine. In addition, the etching speed of the ion beam of an inert gas is smaller than the etching speed of the resist film.B A metal film is formed, and by ion beam etching using this metal film as a mask, a fine pattern is formed on the main surface of the semiconductor substrate with high precision. This provides a method that allows you to do so.
発明者らが種りの金属膜のドライエツチングによるエツ
チング速度を詳細に検討した実験結果によれば、５００
ｅｖのエネルギーと１ｍＡ／ｃｍ２電流密度とを有する
アルゴンイオンビームによるエツチング速度が、モリブ
デン（ＭＯ）膜では２３０八／ｍ ｉｎ 、チタン（ｒ
土）膜でｉ４３２０Ａ／ｍｉｎであり、これらのＭｏ膜
およびＴ１膜のエツチング速度がレジスト膜のエツチン
グ速度（１０００八／ｍ１ｎ）より小さいことが判明し
た。According to the experimental results of the inventors' detailed study of the etching speed of dry etching of seed metal films, it was found that
The etching rate with an argon ion beam having an energy of 1 mA/cm2 and a current density of 1 mA/cm2 is 2308/min for a molybdenum (MO) film, and 2308/min for a molybdenum (MO) film, and 2308/min for a titanium (r
It was found that the etching rate of the Mo film and the T1 film was smaller than the etching rate of the resist film (10008/m1n).
また、ガス圧が０．２Ｔｏｒｒの四塩化炭素（ＣＣ１４
）を周波数が１：’Ｌ５６ＭＨｚの高周波重力によって
プラズマ化したＣＣｌ４のプラズマによるエツチング速
度が、Ｍ。In addition, carbon tetrachloride (CC14) with a gas pressure of 0.2 Torr
) is converted into plasma by high-frequency gravity of 1:'L56MHz, and the etching rate by the plasma of CCl4 is M.
膜でけ６００Ａ／ｍｉｎ、 ＴｉｙｌＩで！ ８００八
／ｍ ｉ ｎであり、これらのＭｏ膜およびＴ３膜のＣ
Ｃ／４のプラズマによるエツチング速度がＭｏ膜および
Ｔ１膜のアルゴンイオンビームによるエツチング速度よ
り犬きく、かつ１／シスト膜のエツチング速度より小さ
いことも判明した。Membrane output 600A/min, TiylI! 8008/min, and the C of these Mo films and T3 films is
It was also found that the etching rate by the C/4 plasma was much higher than the etching rate by the argon ion beam for the Mo film and the T1 film, and was lower than the etching rate for the 1/cyst film.
この発明は、上述の実験結果に基づいてなされたもので
ある。This invention was made based on the above-mentioned experimental results.
第１図、第２図、第３図および第４図はこの発明の一実
ｔ＠例の半導体基板の微細パターンの形成方法の主要段
階の状態を順次示す断面図である。1, 2, 3, and 4 are cross-sectional views sequentially showing the main stages of a method for forming a fine pattern on a semiconductor substrate according to an example of the present invention.
まず、第１図に示すように、半導体基板〔１）の主面上
に１，６００Ａ程度の膜厚を有するＴ１膜（２）を形成
する。次に、第２図に示すように、Ｔ１膜（２）の表面
上に、半導体基板（１）の主面部に形成すべき所望のパ
ターンに対応するパターンを有するエツチングマスク用
のレジスト膜（３）を形成する。次に、第３図に示すよ
うに、レジスト膜（３）ｆマスクにしたＣＣＩ！４のプ
ラズマによるプラズマエツチングによって、Ｔ１膜（２
）のレジスト膜（３）で覆われていない部分を除去して
レジスト膜（３）の下にこのレジスト膜（３）のパター
ンに対応するパターンを有するＴ１膜（２ａ）を残す。First, as shown in FIG. 1, a T1 film (2) having a thickness of about 1,600 Å is formed on the main surface of a semiconductor substrate [1]. Next, as shown in FIG. 2, a resist film (3) for an etching mask having a pattern corresponding to a desired pattern to be formed on the main surface of the semiconductor substrate (1) is formed on the surface of the T1 film (2). ) to form. Next, as shown in FIG. 3, a resist film (3) is used as a mask for CCI! The T1 film (2
) is removed to leave a T1 film (2a) having a pattern corresponding to the pattern of this resist film (3) under the resist film (3).
次に、第４図に示すように、レジスト膜（３）およびＴ
１膜（２ａ）をマスクにして、５００ｅｖのエネルギー
と１ｍＡ／ａｍ２の電流密度とを有するアルゴンイオン
ビームを図示矢印の方向から半導体基板（１）の露出主
面部に投射すると、このアルゴンイオンビームによって
半導体基板（１）の露出主面部の所要厚さがエツチング
除去されて半導体基板（１）の主面部のＴ１膜（２ａ）
の下の部分（ｌａ）にＴ１膜（２ａ）のパターンに対応
するパターンが形成すれる。Next, as shown in FIG. 4, the resist film (3) and T
When an argon ion beam having an energy of 500 ev and a current density of 1 mA/am2 is projected onto the exposed main surface of the semiconductor substrate (1) from the direction of the arrow shown in the figure using the 1 film (2a) as a mask, this argon ion beam causes A required thickness of the exposed main surface of the semiconductor substrate (1) is removed by etching to form a T1 film (2a) on the main surface of the semiconductor substrate (1).
A pattern corresponding to the pattern of the T1 film (2a) is formed in the lower portion (la).
この実施例の方法では、＠３図に示した００１４のプラ
ズマによるプラズマエツチングの段階において、膜厚が
１．６００Ａ ８度のＴｉ膜（２）のエツチング時間が
約２分で終了するので、レジスト膜（３）のエツチング
による膜厚の減少が約２．０ＯＯＡ程度の少ないもので
ある。従って、レジスト膜（３）の膜厚を薄くしてレジ
スト膜（３）のパターンを微細化することができ、これ
にともなってＴ１膜（２ａ）のパターンを微細化するこ
とができる。そして、第４図に示したアルゴンイオンビ
ームによるエツチング段階において、Ｔｉ１ｌＷ（２ａ
）のエツチング速度がレジス）膜（３）のエツチング速
度より小さいので、レジスト膜〔３）のパターン精度の
維持ができなくなっても、Ｔｉ膜（２ａ）のパターンＭ
度を維持することが可能となり、半導体基板（１）の主
面部の部分（１ａ）のパターンの微細化およびパターン
精度の向上を図ることができる。In the method of this example, the etching time for the Ti film (2) with a film thickness of 1.600A and 8 degrees is completed in about 2 minutes at the stage of plasma etching using the 0014 plasma shown in Figure @3, so the resist The reduction in film thickness due to film (3) etching is as small as about 2.0 OOA. Therefore, the pattern of the resist film (3) can be made finer by reducing the thickness of the resist film (3), and accordingly, the pattern of the T1 film (2a) can be made finer. Then, in the etching step using the argon ion beam shown in FIG.
) is lower than that of the resist film (3), so even if the pattern accuracy of the resist film (3) cannot be maintained, the pattern M of the Ti film (2a)
This makes it possible to maintain fineness of the pattern on the main surface portion (1a) of the semiconductor substrate (1) and to improve pattern accuracy.
この実施例では、Ｔｉ膜（２）を用いる場合について述
べたが、Ｍｏ膜を用いる場合でも、この実施例と同様の
効果がある。また、この実施例では、０Ｃ１４のプラズ
マを用いたが、必ずしもこれけＣＣｌ４のプラズマに限
定する必要がなく、その他の塙酸（ＨＣｌ）などの塩素
を含む化合物のプラズマを用いて本よい。更に、この実
施例では、アルゴンイオンビームを用すたが、必ずしも
これはアルゴンイオンビームである必要がなく、その他
の不活性ガスのイオンビームであってもよい。In this embodiment, the case where a Ti film (2) is used has been described, but the same effect as in this embodiment can be obtained even when a Mo film is used. Further, although 0C14 plasma was used in this embodiment, it is not necessarily limited to CCl4 plasma, and plasma of other chlorine-containing compounds such as sulfuric acid (HCl) may also be used. Furthermore, although an argon ion beam is used in this embodiment, it does not necessarily have to be an argon ion beam, and an ion beam of another inert gas may be used.
以上、説明したように、こ゛の発明によれば、半導体基
板の主面上に塩素を含む化合物の、プラズマによってエ
ツチングされかつ不活性ガスのイオンビームによるエツ
チング速度がレジスト膜より小さい所要厚さの金属膜を
形成し、この金属膜の表面上に形成され上記半導体基板
の主面部に形成すべきパターンに対応するパターンを有
するエツチングマスク用レジスト膜をマスクにした上記
塩素を含む化合物のプラズマによるプラズマエツチング
を上記金属膜に施して上記エツチングマスク用レジスト
膜の下にこのレジス）［のパターンに対応するパターン
を有する上記金属膜の部分を残し、上記エツチングマス
ク用レジスト膜とこのレジスト膜の下に残された上記金
４膜の部分とをマスクにした上記不活性ガスのイオンビ
ームによるイオンビームエツチングを上記半導体基板の
主面部に施すので、上記塩素を含む化合物のプラズマに
よるプラズマエツチング時に、上記金譚膜のエツチング
時間が短時間で終了するように、上記金属膜の膜厚を設
定すれば、上記エツチングマスク用レジスト膜のエツチ
ングによる膜厚の減少が少なくなる。従って、上記エツ
チングマスク用レジスト膜の膜厚ｆ １７ ＜ ｌ、て
上記エツチングマスク用レジスト膜のパターンを微細化
することができ、これにともなって上記金属膜の上記エ
ツチングマスク用レジスト膜の下に浅された部分のパタ
ーンを微細化することができる。そして、上記不活性ガ
スのイオンビームによるイオンビームエツチング時に、
上記金；４膜のエツチング速度が上記エツチングマスク
用レジスト膜のエツチング速度より小さいので、上記エ
ツチングマス′り用レジスト膜のパターン精度の維持が
できなくなっても、上記金属膜の上記エツチングマスク
用レジスト膜の下に残された部分のパターン精度を維持
することが可能となり、上記半導体基板の主面部に微細
パターンを精度よく形成することができる。As explained above, according to this invention, a chlorine-containing compound is etched by plasma on the main surface of a semiconductor substrate, and the etching rate by an inert gas ion beam is lower than that of a resist film. Plasma generated by forming a metal film and using the plasma of the above-mentioned chlorine-containing compound using as a mask a resist film for an etching mask, which is formed on the surface of the metal film and has a pattern corresponding to the pattern to be formed on the main surface of the semiconductor substrate. Etching is applied to the metal film to leave a portion of the metal film having a pattern corresponding to the pattern of this resist under the etching mask resist film, and a portion of the metal film having a pattern corresponding to the pattern of this resist is left under the etching mask resist film and this resist film. Since the main surface of the semiconductor substrate is subjected to ion beam etching using the ion beam of the inert gas using the remaining portion of the gold 4 film as a mask, the gold is etched during plasma etching using the plasma of the chlorine-containing compound. If the thickness of the metal film is set so that the etching time for the etching mask is completed in a short time, the decrease in the film thickness of the etching mask resist film due to etching will be reduced. Therefore, the pattern of the etching mask resist film can be made finer when the film thickness f 17 <l of the etching mask resist film, and as a result, the pattern of the etching mask resist film of the metal film is smaller than the etching mask resist film. The pattern in the shallow portion can be made finer. Then, during ion beam etching using the inert gas ion beam,
Since the etching speed of the gold film is lower than the etching speed of the etching mask resist film, even if the pattern accuracy of the etching mask resist film cannot be maintained, the etching mask resist film of the metal film may not be able to maintain the pattern accuracy of the etching mask resist film. It becomes possible to maintain the pattern accuracy of the portion left under the film, and a fine pattern can be formed with high accuracy on the main surface of the semiconductor substrate.
第１図、第２図、第３図および第４Ｍはこの発明の一実
施例の主要段階の状態を順次示す断面図である。
図におＡて、（１）は半導体基板、（２）けＴ１膜（金
属膜） 、（２ａ）Ｉ／′ｉＴｉ膜（２）の一部（金属
膜のエツチングマスク用レジスト膜の下に残された部分
）、（、ｌｔエツチングマスク用レジスト膜である。
なお、図中同一符号はそれぞれ同一または相当部分を示
す。
代理人 葛 野 信 −（外１名）1, 2, 3, and 4M are sectional views sequentially showing the main stages of an embodiment of the present invention. In the figure A, (1) is the semiconductor substrate, (2) is the T1 film (metal film), and (2a) is a part of the I/'iTi film (2) (underneath the resist film for etching mask of the metal film). The remaining parts), (, lt are resist films for etching masks. In addition, the same reference numerals in the figures indicate the same or corresponding parts. Representative: Shin Kuzuno - (1 other person)
Claims (5)
マによってエツチング、されかつ不活性ガスのイオンビ
ームによるエツチング速度がレジスト膜より小さい所要
厚さの金属膜を形成する第１の工程、上記金属膜の表面
上に上記半導体基板の主面部に形成すべきパターンに対
応するパターンを有スルエツｔングマスク用レジスト膜
を形成する第２の工程、上記エツチングマスク用レジス
ト膜をマスクにした上記塩素を含む化合物のプラズマに
よるプラズマエツチングによって上記エツチングマスク
用レジスト膜の下にこのエツチングマスク用レジスト膜
のパターンに対応するパターンを有する上記金属膜の部
分を残す第５の工程、および上記エツチングマスク用レ
ジスト膜とこのエツチングマスク用レジスト膜の下に残
された上記金属膜の部分とをマスクにした上記不活性ガ
スのイオンビームによるイオンビームエツチングを上記
半導体基板の主面部に施す第４の工程を備えた半導体基
板の微細パターンの形成方法。(1) A first step of forming a metal film on the main surface of the semiconductor substrate with a required thickness that is etched with a plasma of a compound containing chlorine and whose etching rate is lower than that of the resist film with an ion beam of an inert gas; A second step of forming a resist film for etching mask with a pattern corresponding to the pattern to be formed on the main surface of the semiconductor substrate on the surface of the metal film, the above-mentioned chlorine is applied using the resist film for etching mask as a mask. a fifth step of leaving a portion of the metal film having a pattern corresponding to the pattern of the etching mask resist film under the etching mask resist film by plasma etching using plasma of a compound containing the etching mask; and a fourth step of subjecting the principal surface of the semiconductor substrate to ion beam etching using an ion beam of the inert gas using the portion of the metal film left under the etching mask resist film as a mask. A method for forming fine patterns on semiconductor substrates.
許請求の範囲第１項記載の半導体基板の微細パターンの
形成方法。(2) The method for forming a fine pattern on a semiconductor substrate according to claim 1, wherein the metal film is a titanium film.
る特許請求の範囲第１項記載の半導体基板の微細パター
ンの形成方法。(3) The method for forming a fine pattern on a semiconductor substrate according to claim 1, wherein the metal film is a molybdenum film.
とする特許請求の範囲第１項ないし第３項のいずれかに
記載の半導体基板の微細パターンの形成方法。(4) The method for forming a fine pattern on a semiconductor substrate according to any one of claims 1 to 3, wherein the chlorine-containing compound is carbon tetrachloride.
る特許請求の範囲第１項ないし第４項のいずれかに記載
、の半導体基板の微細パターンの形成方法。(5) The method for forming a fine pattern on a semiconductor substrate according to any one of claims 1 to 4, characterized in that the inert gas is argon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP314283A JPS59126636A (en) | 1983-01-10 | 1983-01-10 | Formation of microscopic pattern on semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP314283A JPS59126636A (en) | 1983-01-10 | 1983-01-10 | Formation of microscopic pattern on semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59126636A true JPS59126636A (en) | 1984-07-21 |
Family
ID=11549101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP314283A Pending JPS59126636A (en) | 1983-01-10 | 1983-01-10 | Formation of microscopic pattern on semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59126636A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61288427A (en) * | 1985-06-17 | 1986-12-18 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
-
1983
- 1983-01-10 JP JP314283A patent/JPS59126636A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61288427A (en) * | 1985-06-17 | 1986-12-18 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
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