JPH02231722A - Wiring pattern forming method - Google Patents

Abstract

PURPOSE:To form a further minute wiring pattern by forming a photoresist pattern on a semiconductor substrate, then forming a metal layer on the entire surface of the substrate, removing the metal layer until the photoresist pattern is exposed, selectively removing the metal layer remaining on the side surface wall, and forming a wiring. CONSTITUTION:A photoresist layer is formed on a semiconductor substrate 1. The layer is selectively etched away, and a photoresist pattern 2 is formed. A metal layer 3 is formed on the semiconductor substrate 1 including the photoresist pattern 2 by vapor deposition or sputtering. Then, the metal layer 3 around the photoresist pattern 2 and the metal layer 3 on the photoresist pattern are removed by anisotropic dry etching. The photoresist pattern 2 is removed, and only a metal layer 3a is made to remain. Then, a photoresist pattern 2a is formed so as to cover a part of the metal layer 3a. With the photoresist pattern 2a as a mask, the metal layer 3a which is exposed from the mask is removed by etching. Thus, a minute wiring pattern 3c is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring pattern on a semiconductor substrate. [Prior Art] Conventionally, a method for forming wiring patterns for semiconductor devices involves forming a metal layer over the entire surface of a semiconductor substrate by metal vapor deposition or sputtering, forming a photoresist pattern on the metal layer, and using this photoresist pattern as a mask. Anisotropic etching was performed to remove unnecessary metal layers to form a wiring pattern. 1 is a cross-sectional view of the semiconductor chip shown in FIG. First, as shown in FIG. 3(a), a metal layer 3 is formed on a semiconductor substrate 1 by a metal vapor deposition method or a sputtering method. Next, as shown in FIG. 3(b), a photoresist layer is formed on this metal layer 3 and selectively etched away to form a photoresist pattern 2. Next, as shown in FIG. As shown in c), anisotropic dry etching is performed using the photoresist pattern 2 as a mask.
All parts except metal layer 3b are removed. Next, as shown in FIG. 3(d), unnecessary photoresist pattern 2 is removed by etching to obtain a wiring pattern made of metal layer 3b. [Problems to be Solved by the Invention] In the conventional wiring pattern forming method described above, there is a limit to the resolution of the exposure apparatus that creates the photoresist pattern.
The width of the wiring pattern is limited to around 1 μm at most. The drawback is that it is not possible to form wiring patterns with dimensions smaller than this width. Another drawback is that the wiring width of this wiring pattern is determined by one mask pattern loaded into the exposure device. An object of the present invention is to provide a method for forming a wiring pattern that allows a finer wiring pattern to be obtained and the width of the wiring to be varied using one mask pattern. [Means to solve the problem] 1. A first wiring pattern forming method of the present invention includes the steps of: forming a photoresist pattern on a semiconductor substrate; forming a metal layer by sputtering or metal vapor deposition on the semiconductor substrate including the photoresist pattern; A step of removing the metal layer other than the metal layer while leaving the metal layer attached to the side surface of the photoresist layer of the photoresist pattern by performing anisotropic dry etching on the surface of the semiconductor substrate including the photoresist pattern and the metal layer. It consists of: 2. A second wiring pattern forming method of the present invention includes a step of forming a metal layer on a semiconductor substrate by sputtering or metal vapor deposition, a step of forming a photoresist pattern on the metal layer, and a step of forming a photoresist pattern on the metal layer and the photoresist pattern. a step of removing the oxide film other than the oxide film adhering to the side wall of the photoresist layer by anisotropic dry etching the surface of the semiconductor substrate containing the semiconductor substrate; and a step of forming a plated metal layer on the metal layer by a plating method. , after removing the photoresist pattern, removing the metal layer other than the metal layer that is the base metal layer of the plating metal layer. [Example] Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(f) are a sectional view and a partial plan view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention. First, as shown in FIG. 1(a), a photoresist layer is formed on a semiconductor substrate 1 and selectively etched away to form a photoresist pattern 2. Next, as shown in FIG. 1(b), a metal layer 3 is formed on the semiconductor substrate 1 including the photoresist pattern 2 by vapor deposition or sputtering. Next, as shown in FIG. 1(c), the metal layer 3 around the photoresist pattern 2 and the metal layer 3 on the photoresist pattern 2 are removed by anisotropic dry etching. This leaves the metal layer 3a deposited on the sidewalls of the photoresist layer of the photoresist pattern 2. Next, Figure 1 (d
), the photoresist pattern 2 is removed by etching, leaving only the metal layer 3a. Next, as shown in FIG. 1(e), a photoresist 1 pattern 2a is formed to cover a part of the metal layer 3a.
Next, as shown in FIG. 1(f), wet etching is performed using the photoresist pattern 2a as a mask.
The metal layer 3a exposed through the mask is removed to obtain a fine wiring pattern 3C. Here, according to this embodiment, the thickness of the wiring in this wiring pattern can be controlled by the thickness of the photoresist layer, and the width of the wiring can be controlled by changing the thickness of the metal layer attached to the photoresist layer. Therefore, the wiring width and thickness of this wiring pattern can be controlled arbitrarily by changing the manufacturing conditions during the process. FIGS. 2(a) to 2(g) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention. First, as shown in FIG. 2(a), a metal layer 3 is formed on a semiconductor substrate 1, a photoresist layer is further formed on the metal layer 3, and this photoresist layer is selectively etched. The photoresist pattern 2 is then removed. Next, as shown in FIG. 2(b), this photoresist film is applied. An oxide film 4 is formed on the semiconductor substrate including the turn 2 by the CVD method. Next, as shown in FIG. 2(C), the oxide film 4 on the photoresist pattern 2 is removed by anisotropic dry etching, leaving only the oxide film 4a attached to the sidewalls of the photoresist layer of the photoresist pattern 2. ．． Next, as shown in FIG. 2(d), a plated metal layer 5 is formed on the metal layer 3 using the exposed metal layer 3 as an electrode by a plating method. Next, as shown in FIG. 2(e), the oxide film 4a on the sidewalls of the photoresist pattern 2 is etched away using butic acid. Next, as shown in FIG. 2(f), the photoresist pattern 2 is removed by etching. Next, the second
As shown in Figure (g), using the plated metal layer 5 as a mask, the metal layer 3 other than the metal layer 3 that is the underlying metal of the plated metal layer 5 is removed by anisotropic dry etching to form fine wiring. Obtain pattern 3C. In this embodiment, an oxide film is formed on the sidewalls of the photoresist layer of the photoresist pattern 2, resulting in a wiring layer having a width narrower than the window of the photoresist pattern. Furthermore, the wiring width of the wiring pattern can be changed arbitrarily by changing the thickness of this oxidized layer, and the wiring thickness can be changed by changing the plating thickness. [Effects of the Invention] As explained above, in the first method of the present invention, a photoresist pattern is formed on a semiconductor substrate, a metal layer is formed by sputtering or metal vapor deposition, and this metal layer is removed by anisotropic dry etching. By etching away the photoresist pattern until it is exposed and selectively etching away the metal layer left on the side walls of this photoresist pattern to form wiring, a finer wiring pattern can be formed. Further, the wiring width and thickness of this wiring pattern can be easily changed by changing the resist film thickness of the photoresist pattern and the thickness of the metal layer. On the other hand, in the second method, after forming a metal layer on a semiconductor substrate, a photoresist pattern is formed on the metal layer,
An oxide film is formed on the photoresist pattern. This oxide film is removed by anisotropic dry etching except for the oxide film that adheres to the sidewalls of the photoresist layer, which is the same as using a mask narrower than the window spacing of the photoresist pattern, so that Since the wiring pattern is formed using metal plating, a narrower wiring pattern can be obtained. Furthermore, the width of this wiring can be changed arbitrarily depending on the heat of the oxide film. Furthermore, the thickness of the wiring can be easily changed by changing the thickness of the plating layer. Therefore, according to the present invention, it is possible to obtain a method for forming a wiring pattern in which a finer wiring pattern can be obtained and the wiring width of the wiring pattern can be varied with one mask pattern.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views and partial plan views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. 2(a) to (g) are the main views of the semiconductor chip. Second according to invention
3(a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps to explain an example of the conventional wiring pattern forming method. FIGS. This is a diagram.

Claims (1)

[Claims] 1. A step of forming a photoresist pattern on a semiconductor substrate, a step of forming a metal layer by sputtering or metal vapor deposition on the semiconductor substrate including the photoresist pattern, and a step of forming a metal layer on the semiconductor substrate including the photoresist pattern; and removing the metal layer other than the metal layer by anisotropic dry etching the surface of the semiconductor substrate including the metal layer, leaving the metal layer attached to the side surface of the photoresist layer of the photoresist pattern. A first wiring pattern forming method characterized by: 2. A step of forming a metal layer on a semiconductor substrate by sputtering or metal vapor deposition, a step of forming a photoresist pattern on the metal layer, and anisotropic anisotropy of the surface of the semiconductor substrate including the metal layer and photoresist pattern. removing the oxide film other than the oxide film adhering to the sidewall of the photoresist layer by dry etching;
The method includes forming a plated metal layer on the metal layer by a plating method, and removing the metal layer other than the metal layer that is a base metal layer of the plated metal layer after removing the photoresist pattern. A second wiring pattern forming method characterized in that.