JPH03257825A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve an extremely fine pattern of a layer where the pattern is formed by patterning a layer where the pattern is formed by utilizing a side wall which is formed on the layer where the pattern is formed. CONSTITUTION:A silicon nitriding film (SiN) 18 is deposited and formed between side walls 17 which are formed on a first polycrystal silicon film 13 by the plasma CDV method so that it is lower than the side wall 17. Then, a second polycrystal silicon film forming the side wall 17 and the first polycrystal silicon film 13 below the side wall 17 are removed by etching using the RIE method. After that, the silicon nitriding film 18 is removed, thus enabling the first polycrystal silicon film 13 which is formed below the side wall 17 to be eliminated selectively, the first polycrystal silicon film 13 to remain with a gap of the side wall 17, and the first polycrystal silicon film 13 to be subject to patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device that improves microfabrication of the semiconductor device.

(Prior Art) Conventionally, in the manufacture of semiconductor devices, photolithography, which combines various exposure and development techniques and etching techniques, has been used to obtain desired circuit patterns.

In the photolithography technique, a desired pattern is obtained in a photographic manner as shown in the process cross-sectional view of FIG. Specifically, when patterning a polycrystalline silicon layer 3 formed on a semiconductor substrate 1 via a silicon oxide film 2, first, a photoresist 4 is applied over the entire surface of the polycrystalline silicon layer 3. . After that, the applied photoresist 4
Exposure is performed by irradiating ultraviolet rays, electron beams, ions, etc. through a mask pattern. Subsequently, the photoresist 4 is developed and patterned according to the circuit pattern to be formed (FIG. 2(a)).
.

Next, using the patterned photoresist 4 as a mask, a portion of the polycrystalline silicon layer 3 is etched away by, for example, reactive ion etching (RIE).

Thereafter, the remaining photoresist 4 is removed and the polycrystalline silicon layer 3 is processed into a desired pattern.

In such a manufacturing process, as a method for etching a part of the layer to be patterned, as described above, the RIE method, which has high anisotropy, is often used. This RIE
This method allows the mask pattern to be almost accurately transferred to the pattern-forming layer, and has excellent mask pattern fidelity.

Therefore, in order to achieve ultra-fine circuit patterns, it is necessary to miniaturize the mask pattern and improve the resolution of the mask pattern.

On the other hand, in forming a circuit pattern in a semiconductor device, the pattern of the photoresist 4 shown in FIG. 2(a) is
The line width cannot be set very short from the viewpoint of signal transmission loss in the layer to be patterned. However, the space width S in the pattern of the photoresist 4 can be set short enough to prevent short circuits from occurring in the layer to be patterned. For these reasons, in order to form a very fine circuit pattern and to realize a fine mask pattern, it is required to form a mask pattern with a short space width S.

However, with conventionally used photolithography techniques, the space width S of the photoresist pattern 4 could only be formed to a width equivalent to or larger than the line width.

This is because the radiation causes interference phenomena such as scattering and diffraction within the photoresist 4.

Another reason is that in order to obtain fine circuit patterns, a positive type photoresist, which generally has a higher resolution than a negative type, is used.

(Problems to be Solved by the Invention) As described above, in conventional photolithography techniques, it has been extremely difficult to miniaturize mask patterns due to fundamental phenomena such as radiation interference phenomena. Moreover, even if exposure technology and resist materials are improved in the future, this problem cannot be solved.

Therefore, in the conventional method of forming a circuit pattern using a resist material as a mask, there is a limit to the reduction in pattern spacing, making it extremely difficult to achieve ultra-fine design and high integration in semiconductor devices.

Therefore, the present invention has been made in view of the above, and its purpose is to reduce the pattern interval in a mask pattern and realize ultra-fine patterning of a layer to be patterned. An object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to ultra-fine and highly integrated semiconductor devices.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention forms a first pattern on a layer to be patterned using a material different from that of the layer to be patterned. a step of forming a sidewall on a side surface of the first pattern using the same material as the layer to be patterned; a step of selectively removing the first pattern; and a step of forming the pattern between the sidewalls. on the layer,
forming a second pattern; using the second pattern as a mask, selectively removing the sidewall and the layer to be patterned under the sidewall; and removing only the layer to be patterned under the second pattern; The gist of the invention is to have a step of causing the remaining .

(Function) In the above method, the present invention is capable of removing the patterned layer under the sidewall made of the same material as the patterned layer formed on the side surface of the material different from the patterned layer. The formation layer is patterned.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a process cross-section showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. The embodiment shown in FIG. 1 uses sidewalls formed by the sidewall leaving technique to form a polycrystalline silicon pattern on a semiconductor substrate with a space width S shorter than the line width. This is what I did.

First, a first silicon oxide film 12 is deposited on a silicon semiconductor substrate 11 to a thickness of about 200 layers by thermal oxidation. Subsequently, a first polycrystalline silicon film 13, which will become a layer to be patterned, is deposited on the silicon oxide film 12 to a thickness of about 5000 Å by CVD. after that,
A second silicon oxide film 14 is deposited on the first polycrystalline silicon film 13 to a thickness of about 4,000 by CVD (FIG. 1(a)).

Next, after applying a photoresist material to the entire surface, this photoresist material is patterned by the RIE method to form a photoresist batten 15 with a line width of approximately 0.8μ■ and a space width S of approximately 1.4μ■. is formed on the second silicon oxide film 14 (FIG. 1(b)).

Next, using the photoresist pattern 15 as a mask, a portion of the second silicon oxide film 14 is selectively etched away by RIE. Thereafter, the entire photoresist pattern 15 is removed.

As a result, only the second silicon oxide film 14 under the photoresist pattern 15 is left selectively. continue,
A second polycrystalline silicon film 16 is deposited on the entire surface by CVD method.
The second silicon oxide film 14 is selectively deposited to be thicker than the remaining second silicon oxide film 14. Subsequently, the deposited second polycrystalline silicon film 16 is etched by anisotropic etching using the RIE method. Thereby, the second polycrystalline silicon film 16 is attached to the side surface of the second silicon oxide film 14, and a sidewall 17 of the second polycrystalline silicon film 14 is formed. Here, the width of the sidewall 17 formed on the side surface of the second silicon oxide film 14 is 0.3.
It is formed to be extremely short, on the order of μm (Fig. 1(C)).

Next, the second silicon oxide film 14 with the sidewalls 17 formed on the side surfaces is entirely removed, leaving only the sidewalls 17 on the first polycrystalline silicon film 13 (FIG. 1(d)).

Next, a silicon nitride film (SIN) 18 is deposited between the side walls 17 formed on the first polycrystalline silicon film 13 using plasma C.
The layer is deposited by the DV method so as to be lower than the height of the side wall 17 (FIG. 1(e)).

Next, using the silicon nitride film 18 as a mask, the second polycrystalline silicon H16 forming the sidewall 17 and the first polycrystalline silicon film 13 under the sidewall 17 are etched away by RIE. Thereafter, silicon nitride film 18 is removed.

As a result, the first polycrystalline silicon film 13 formed under the sidewall 17 is selectively removed, the first polycrystalline silicon film 13 is left at intervals equal to the width of the sidewall 17, and the first polycrystalline silicon film 13 is removed. The silicon film 13 is patterned (FIG. 1(f)).

As described above, in the manufacturing method described in the above embodiment, the first polycrystalline silicon film 13 as the pattern formation layer is formed so that the line width L (pattern width) is about 0.8 μm and the space width S It becomes possible to perform patterning with a (pattern interval) of approximately 0.3 μm. Therefore, it becomes possible to obtain a pattern in which the space width S is extremely short compared to the conventional pattern, and it becomes possible to provide a processing technique that is extremely useful for microfabrication of integrated circuits.

Note that the present invention is not limited to the above embodiments, and the layer to be patterned may be made of a metal such as Al, and is not limited to the material used as the layer to be patterned or the mask during etching. It is possible to implement.

[Effects of the Invention] As described above, according to the present invention, the sidewalls formed on the layer to be patterned are used to pattern the layer to be patterned. The interval between the mass patterns can be reduced to about the width of the side wall. As a result, it becomes possible to form ultra-fine patterns on the layer to be patterned, and it becomes possible to provide a method for manufacturing a semiconductor device that can contribute to ultra-fine and highly integrated semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional method of manufacturing a semiconductor device. 11...Semiconductor substrate 13...First polycrystalline silicon film 14...Second silicon oxide film 16...Second polycrystalline silicon film 17...Side wall 18...Silicon nitride film

Claims (1)

[Scope of Claims] A step of forming a first pattern on a layer to be patterned using a material different from that of the layer to be patterned; and a step of forming a first pattern on a side surface of the first pattern using the same material as the layer to be patterned. a step of selectively removing the first pattern; a step of forming a second pattern on the patterned layer between the sidewalls; As a mask, the sidewall and the layer to be patterned under the sidewall are selectively removed;
a step of leaving only the layer to be patterned under the pattern.