JPH03108330A - Manufacture of semiconductor - Google Patents
Manufacture of semiconductorInfo
- Publication number
- JPH03108330A JPH03108330A JP24592289A JP24592289A JPH03108330A JP H03108330 A JPH03108330 A JP H03108330A JP 24592289 A JP24592289 A JP 24592289A JP 24592289 A JP24592289 A JP 24592289A JP H03108330 A JPH03108330 A JP H03108330A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- level
- etched
- difference part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 12
- 229910021332 silicide Inorganic materials 0.000 abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法、特に半導体装置の
段差部上の被エツチング材料を有効にエツチング除去(
異方性エツチング)する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for effectively etching away material to be etched on a stepped portion of a semiconductor device.
The present invention relates to a method for performing anisotropic etching.
第2図a〜bは従来の半導体装置の製造方法の主要工程
を示す断面図である。FIGS. 2a to 2b are cross-sectional views showing the main steps of a conventional method for manufacturing a semiconductor device.
図において、1は半導体基板、2はポリシリコン膜、3
はMoなどのシリサイド膜、4はレジスト膜であり、7
はエツチング残渣である。そして、第2図aはポリシリ
コン膜2およびMo等のシリサイド膜3を成膜し、所望
のレジストパターンを形成したところを示す断面図であ
り、第2図すはエツチング後の断面図を示す。In the figure, 1 is a semiconductor substrate, 2 is a polysilicon film, and 3 is a semiconductor substrate.
is a silicide film such as Mo, 4 is a resist film, and 7 is a silicide film such as Mo.
is the etching residue. FIG. 2a is a cross-sectional view showing a polysilicon film 2 and a silicide film 3 made of Mo or the like formed to form a desired resist pattern, and FIG. 2a is a cross-sectional view after etching. .
次に、従来の製造方法について説明する。ここでは、特
にゲート部の形成方法について説明する。Next, a conventional manufacturing method will be explained. Here, a method for forming the gate portion will be particularly described.
まず、シリコン基板1内にウェル形成などの工程を経た
後、ポリシリコン膜2を成膜し、ゲート電極の材料とな
るシリサイドM3を成膜する。その後、レジスト膜4を
塗布し露光・現像工程により所望のレジストパターンを
形成する。更に該レジストパターンをマスクとし、エツ
チングを行いゲート部6を形成する。このとき、高精度
の寸法制御を必要とするため、リアクティブイオンエツ
チング(RIE)などの異方性エツチングを行う。First, after going through steps such as forming a well in a silicon substrate 1, a polysilicon film 2 is formed, and then a silicide M3, which is a material for a gate electrode, is formed. Thereafter, a resist film 4 is applied and a desired resist pattern is formed by exposure and development steps. Further, using the resist pattern as a mask, etching is performed to form the gate portion 6. At this time, since highly accurate dimensional control is required, anisotropic etching such as reactive ion etching (RIE) is performed.
この様にして、レジストパターンよりのシフト量が少な
いゲートパターンを得る。In this way, a gate pattern with a smaller shift amount than the resist pattern is obtained.
従来の半導体装置の製造方法は以上の様に構成されてい
るので、特に段差部においてはポリシリコンllI2.
シリサイド膜3等の膜厚が厚くなるために、基板表面に
対し均一に進行する異方性エツチングを行うと、エツチ
ング残渣7が発生する。Since the conventional semiconductor device manufacturing method is configured as described above, polysilicon llI2.
Since the film thickness of the silicide film 3 and the like becomes thick, etching residue 7 is generated when anisotropic etching that progresses uniformly on the substrate surface is performed.
このエツチング残渣7を除去するために、追加エツチン
グやウェットエツチングなどの方法を行うが、膜下地へ
のダメージや、サイドエッチにより所望するパターンの
寸法制御が困難になるなどの問題点があった。In order to remove this etching residue 7, methods such as additional etching and wet etching are used, but there are problems such as damage to the film base and side etching that makes it difficult to control the dimensions of the desired pattern.
この発明は上記のような問題点を解消するためになされ
たもので、段差部でのエツチング残渣を無くし、高精度
な寸法制御を可能とし、所望のパターンを得る半導体装
置の製造方法を提供することを目的とする。This invention has been made to solve the above-mentioned problems, and provides a method for manufacturing a semiconductor device that eliminates etching residue at stepped portions, enables highly accurate dimensional control, and obtains a desired pattern. The purpose is to
この発明に係る半導体装置の製造方法は、半導体基板上
に形成された絶縁膜や導電膜等に対して、写真製版及び
エツチングを行い、所望のパターンを形成する方法にお
いて、
段差部上の被エツチング材料のみを露出させる耐エツチ
ング被膜を形成し、段差部上の被エツチング材料を所望
量先行エツチングした後、所望のパターンをレジストに
て形成してエツチングすることを特徴とする半導体装置
の製造方法。A method for manufacturing a semiconductor device according to the present invention is a method for forming a desired pattern by photolithography and etching on an insulating film, a conductive film, etc. formed on a semiconductor substrate. A method for manufacturing a semiconductor device, which comprises forming an etching-resistant film that exposes only the material, pre-etching a desired amount of the material to be etched on the stepped portion, and then forming a desired pattern with a resist and etching.
この発明の半導体装置の製造方法においては、段差部の
みを露出する耐エツチング被膜を形成し、先行エツチン
グすることにより、被エツチング材料の膜厚を均一にす
る。その後、平坦部をエツチングすることにより、段差
部のエツチング残渣を有しない所望のパターンを得るこ
とができる。In the method of manufacturing a semiconductor device of the present invention, an etching-resistant film is formed that exposes only the step portion, and the film thickness of the material to be etched is made uniform by performing preliminary etching. Thereafter, by etching the flat portions, it is possible to obtain a desired pattern without etching residues on the stepped portions.
以下、この発明の一実施例を第1図a % Cについて
説明する0図において、1は半導体基板、2はポリシリ
コン膜、3はMO等のシリサイド膜、4はレジスト膜、
5は耐エツチング被膜である。Hereinafter, an embodiment of the present invention will be explained with reference to FIG.
5 is an etching-resistant coating.
次に、製造方法について説明する。ここでは、従来と同
様ゲート部の形成方法を例に挙げて説明する。Next, the manufacturing method will be explained. Here, a method for forming a gate portion will be described as an example, similar to the conventional method.
まず、第1図aに示すように、シリコン基板1上にポリ
シリコン膜2及びシリサイド膜3を形成した後、例えば
薄いレジスト膜なる耐エツチング被膜5を塗布形成し、
段差部のみを露出させる。First, as shown in FIG. 1a, after forming a polysilicon film 2 and a silicide film 3 on a silicon substrate 1, an etching-resistant film 5, such as a thin resist film, is applied and formed.
Expose only the step part.
さらにゲート形成のためレジスト膜4によりレジストパ
ターンを形成する。Furthermore, a resist pattern is formed using the resist film 4 to form a gate.
次に、第1図すに示すように、耐エツチング被11[5
をマスクとして異方性エツチングを行い、露出された段
差部のみエツチングする。ここで、シリサイド膜3と一
層目の薄いレジスト膜である耐エツチング被膜5との選
択比により、所望のレジストパターン下以外の耐エツチ
ング被膜らを除去した状態で、段差部のみ所望量エツチ
ングする。Next, as shown in FIG.
Anisotropic etching is performed using the mask as a mask, and only the exposed step portions are etched. Here, depending on the selectivity between the silicide film 3 and the etching-resistant film 5, which is the first thin resist film, only the stepped portion is etched by a desired amount while removing the etching-resistant film other than under the desired resist pattern.
さらに、第1図Cに示すように、異方性エツチングを行
いゲート形成のためのレジストパターン部を除いて均一
な膜厚となった平坦部をジャストエツチングする。Furthermore, as shown in FIG. 1C, anisotropic etching is carried out to just etch the flat part, which has a uniform film thickness, except for the resist pattern part for forming the gate.
上記実施例によれば、段差部のみ先行エツチングされる
ので、異方性エツチングにより発生する段差部で生じる
エツチング残渣を防ぐことができる。According to the above embodiment, since only the step portion is etched in advance, it is possible to prevent etching residues from being generated at the step portion due to anisotropic etching.
以上の様にこの発明によれば、段差部のみを露出させ先
行エツチングした後、平坦部をエツチングしたので、ジ
ャストエツチングでのエツチング残渣を防ぎ、追加エツ
チングやウェットエツチングなどによるサイドエツチン
グなどを不要とするとかでき、高精度の寸法制御が可能
となる。As described above, according to the present invention, only the stepped portions are exposed and etched first, and then the flat portions are etched, thereby preventing etching residues caused by just etching and eliminating the need for side etching by additional etching or wet etching. This enables highly accurate dimensional control.
第1図a −cはこの発明の一実施例による半導体装置
の製造方法を示す主要工程断面図、第2図a −bは従
来の半導体装置の製造方法を示す断面図である。
図中、1は半導体基板、2はポリシリコン膜、3はシリ
サイド膜、4はレジスト膜、5は耐エツチング被膜であ
る。
なお、図中同一符号は同−又は相当部分を示す。FIGS. 1a-c are sectional views showing main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2a-b are sectional views showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a polysilicon film, 3 is a silicide film, 4 is a resist film, and 5 is an etching-resistant coating. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
真製版及びエッチングを行い、所望のパターンを形成す
る半導体装置の製造方法において、段差部の被エッチン
グ材料のみを露出させる耐エッチング被膜を形成し、段
差部の被エッチング材料を所望量先行エッチングした後
、所望のパターンをレジストにて形成してエッチングす
ることを特徴とする半導体装置の製造方法。In a semiconductor device manufacturing method in which a desired pattern is formed by performing photolithography and etching on an insulating film or a conductive film formed on a semiconductor substrate, an etching-resistant film that exposes only the material to be etched in the stepped portion is used. 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device and pre-etching a desired amount of a material to be etched in a stepped portion, and then forming a desired pattern using a resist and etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24592289A JPH03108330A (en) | 1989-09-20 | 1989-09-20 | Manufacture of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24592289A JPH03108330A (en) | 1989-09-20 | 1989-09-20 | Manufacture of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03108330A true JPH03108330A (en) | 1991-05-08 |
Family
ID=17140842
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24592289A Pending JPH03108330A (en) | 1989-09-20 | 1989-09-20 | Manufacture of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03108330A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010187696A (en) * | 2010-04-27 | 2010-09-02 | Iseki & Co Ltd | Thresher |
JP2011188865A (en) * | 2011-05-30 | 2011-09-29 | Iseki & Co Ltd | Thresher |
JP2012089902A (en) * | 1995-01-31 | 2012-05-10 | Fujitsu Semiconductor Ltd | Manufacturing method for semiconductor device |
US8674421B2 (en) | 1995-01-31 | 2014-03-18 | Fujitsu Semiconductor Limited | Semiconductor device |
-
1989
- 1989-09-20 JP JP24592289A patent/JPH03108330A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012089902A (en) * | 1995-01-31 | 2012-05-10 | Fujitsu Semiconductor Ltd | Manufacturing method for semiconductor device |
US8674421B2 (en) | 1995-01-31 | 2014-03-18 | Fujitsu Semiconductor Limited | Semiconductor device |
JP2010187696A (en) * | 2010-04-27 | 2010-09-02 | Iseki & Co Ltd | Thresher |
JP2011188865A (en) * | 2011-05-30 | 2011-09-29 | Iseki & Co Ltd | Thresher |
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