JP2841484B2 - Method for manufacturing MOS transistor - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS transistor.

[Conventional technology]

Conventionally, a method shown in FIGS. 3A to 3D has been used as a method of manufacturing a MOS transistor, particularly as a method of manufacturing a gate electrode thereof.

That is, as shown in FIG. 3A, a thermal oxide film 12 is formed on the surface of a silicon substrate 11, and a polycrystalline silicon film 13 as a gate electrode material is formed thereon. Then, a positive photoresist 14 is formed thereon.

Then, as shown in FIG.
14 is patterned into a gate electrode shape. And the third
As shown in FIG. 3C, the polycrystalline silicon film 13 is etched using the photoresist 14 as a mask.

Thereafter, as shown in FIG. 3D, the photoresist 14 is removed to complete the gate electrode 13A.

[Problems to be solved by the invention]

In the conventional method for manufacturing a gate electrode described above, the length dimension of the gate electrode that affects the characteristics of the MOS transistor is determined by the mask dimension of the photoresist. Therefore, the processing limit dimension of the gate electrode 13A is
Is determined by the resolving power of the photolithography technology such as the light source and the exposure apparatus, and there is a problem that the miniaturization is limited.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a manufacturing method capable of forming a gate electrode that is finer than the processing limit of the photolithography technique.

[Means for solving the problem]

According to the method of manufacturing a MOS transistor of the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of forming a first polycrystalline silicon film thereon, and a step of forming a polycrystalline silicon film on the first polycrystalline silicon film are performed. Forming a first insulating film having an etching selectivity with respect to crystalline silicon; and selectively removing an area of the first insulating film where a gate electrode is to be formed by anisotropic etching. Forming an opening where the film is exposed, forming a second insulating film having an etching selectivity with polycrystalline silicon over the entire surface,
Anisotropically etching the second insulating film to leave the second insulating film only on the side surface of the opening, exposing the first polycrystalline silicon film, and leaving the second insulating film only on the side surface. Forming a second polycrystalline silicon film over the entire surface including the opening where the film remains, and etching the second polycrystalline silicon film until the first and second insulating films are exposed; And a step of etching and removing the first and second insulating films thereafter, and a step of etching and removing the first polycrystalline silicon film using the second polycrystalline silicon film as a mask.

[Action]

In this manufacturing method, by using the first polycrystalline silicon film, even when the first and second insulating films are etched, damage to the surface of the semiconductor substrate can be prevented, and the fine gate electrode can be formed. Realize the formation.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (i) are longitudinal sectional views showing a first embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1A, a thermal oxide film having a thickness of about 150.degree.
Is formed. A first polycrystalline silicon film (second film) 3 having a thickness of about 500 ° is formed thereon as a conductive film by a vapor phase growth method. Furthermore, as a film having a high etching rate selectivity with a polycrystalline silicon film,
A vapor growth oxide film (third film) 4 of about 0.3 μm is formed.

Next, as shown in FIG. 1 (b), a photoresist 5 is applied, and a required pattern is exposed and developed to form an opening 5a having a width of 1 μm at a position where a gate electrode is to be formed.
Then, using the photoresist 5 as a mask, the vapor growth oxide film 4 is etched by a reactive ion etching method to form an opening 4a.

Next, as shown in FIG. 1 (c), after removing the photoresist 5, a silicon nitride film having a thickness of 0.2 μm is formed as a film having a high etching rate selectivity by using a vapor phase growth method. A film (fourth film) 6 is formed on the entire surface.

Then, as shown in FIG. 1D, the silicon nitride film 6 is etched using a reactive ion etching technique until the surface of the vapor growth oxide film 4 is exposed. Since the silicon nitride film 6 has excellent step coverage, the etching leaves the silicon nitride film 6 only on the side surface of the opening 4a. As a result, the width of the opening 4a has a width reduced from 1 μm by twice the thickness of the silicon nitride film 6.
0.6 μm.

Next, as shown in FIG. 1E, a second polycrystalline silicon film (fifth film) 7 having a thickness of about 0.5 μm is formed using a vapor phase growth method. As a result, the opening 4a is buried with the second polycrystalline silicon film 7, and the entire surface is covered with the second polycrystalline silicon film 7.

Next, as shown in FIG. 1 (f), the second polycrystalline silicon film 7 is etched by the reactive ion etching method until the surface of the vapor growth oxide film 4 is exposed. As a result, the second polycrystalline silicon film 7 is left buried only in the opening 4a.

Next, as shown in FIG. 1 (g), the vapor-grown oxide film 4 is completely removed by using a diluted HF solution.
The silicon nitride film 6 is completely removed using phosphoric acid heated to an appropriate temperature as described above. The first polycrystalline silicon film 3
Serves as a mask for these etchings.

Thereafter, the first polycrystalline silicon film 3 is removed by etching by reactive ion etching, whereby the first polycrystalline silicon film 3 is removed.
As shown in FIG. (I), the gate electrode 7A having a gate length of 0.6 μm
Is completed. At this time, the thickness of gate electrode 7A is slightly smaller than that of second polycrystalline silicon film 7.

Therefore, the gate electrode 7A can be formed to have a gate length smaller than the critical dimension of the resolving power of the photolithography technique by twice the thickness of the silicon nitride film 6, and the miniaturization can be promoted.

2 (a) to 2 (c) are views showing a second embodiment of the present invention in the order of steps.

FIG. 2A shows a state in which the steps up to the step of FIG. 1D in the first embodiment have been performed.

Next, as shown in FIG. 2B, a tungsten (fifth film) 8 is selectively grown in the opening 4a by using a selective tungsten growth technique.

Thereafter, by performing the steps of FIGS. 1 (g) and (h), a gate electrode 8A is formed as shown in FIG. 2 (c).

Also in this embodiment, a gate electrode having the same fine dimensions as in the first embodiment is formed.

In this manufacturing method, the electrical resistance of tungsten constituting the gate electrode is lower than that of polycrystalline silicon, which is advantageous when applied to a high-speed MOS transistor.

〔The invention's effect〕

As described above, according to the present invention, the width of the opening is reduced to the processing limit described in the photolithography by leaving the second insulating film on the side surface of the opening of the first insulating film formed by the photolithography technique. Since the second polycrystalline silicon film is selectively formed in the opening and the gate electrode is formed by the first polycrystalline silicon film immediately below the second polycrystalline silicon film, the finer than the processing limit of the photolithography technique. A gate electrode having a gate length can be manufactured. Further, the first and second insulating films are formed on the first polycrystalline silicon film, and the second polycrystalline silicon film is formed on the first polycrystalline silicon film to form the gate electrode. When etching the first and second insulating films, the etching of the first polycrystalline silicon film is suppressed by the etching selectivity, whereby damage to the surface of the semiconductor substrate can be prevented, and the fine gate electrode can be prevented. To realize the formation of

[Brief description of the drawings]

FIGS. 1A to 1I are longitudinal sectional views showing a first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2A to 2C show main steps of a second embodiment of the present invention. Longitudinal sectional view, FIG. 3 (a)
(D) are longitudinal sectional views showing a conventional method for manufacturing a gate electrode in the order of steps. 1 ... silicon substrate, 2 ... thermal oxide film (first film), 3
... first polycrystalline silicon film (second film), 4 ... vapor-grown oxide film (third film), 5 ... photoresist, 6 ...
... Silicon nitride film (fourth film), 7 ... second polycrystalline silicon film (fifth film), 7A ... gate electrode, 11 ... silicon substrate, 12 ... thermal oxide film, 13 ... Polycrystalline silicon film,
13A ... gate electrode, 14 ... photoresist.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/3205 H01L 21/3213 H01L 21/44-21/445 H01L 29 / 40-29/51

Claims (1)

(57) [Claims] A step of forming a gate insulating film on a semiconductor substrate, a step of forming a first polycrystalline silicon film thereon, and an etching selectivity of polycrystalline silicon on the first polycrystalline silicon film. Forming a first insulating film having an opening, and selectively removing an area of the first insulating film on which a gate electrode is to be formed by anisotropic etching to expose the first polycrystalline silicon film. Forming a;
Forming a second insulating film having an etching selectivity with polycrystalline silicon over the entire surface, and anisotropically etching the second insulating film to leave the second insulating film only on the side surface of the opening; Forming a second polycrystalline silicon film on the entire surface including the opening in which the first polycrystalline silicon film is exposed and the second insulating film remains only on the side surface;
Etching the second polycrystalline silicon film until the second insulating film is exposed, and then etching and removing the first and second insulating films; and etching the second polycrystalline silicon film. Etching the first polycrystalline silicon film using a mask as a mask.