JPH06224161A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a wiring or a mask pattern of very fine width which surpasses the limit of photolithography technique. CONSTITUTION:A side wall 7 of polycrystalline silicon film 6 is formed on an island 4a of silicon nitride film 4, and then the island 4a is removed, whereby only the side wall 7 is left unremoved, and the side wall 7 can be made to serve as a wiring. The wire width of a wiring is the width of a side wall or determined basing on the thickness of a wiring layer, so that the wire width of a wiring passing the limits of a lithography technique can be realized. The same as above, a side wall of silicon nitride film is formed on an island of certain material different from those of a doped polycrystalline silicon film and a mask pattern, and then the island is removed, whereby a mask pattern whose line width passes the limit of a lithography technique can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device,
The present invention relates to a technique for forming a wiring or mask pattern having a fine width.

[0002]

2. Description of the Related Art Conventionally, an optical lithography technique has been used for forming wiring in a semiconductor device. For example,
After forming a chemically sensitized ionizing radiation resist on a semiconductor substrate, it is exposed to a predetermined pattern, the resist surface is forcibly baked at the time of baking after exposure, and then developed. It is possible to obtain a highly accurate pattern in this manner.
No. 101218 (H01L21 / 027).

[0003]

In the photolithography technique as in the conventional example, since the required minimum line width of the element has recently become equal to the wavelength of light used for transfer, , The size has reached its limit. For example, in the 64M DRAM currently under development, i-line (wavelength: 0.365 μm) is likely to be used as a light source. When this i-line is used, the minimum line width is 0.35 μm.
The limit is m to 0.4 μm.

The present invention relates to a method of manufacturing a semiconductor device, and an object thereof is to form a wiring or a mask pattern that exceeds the limit of lithography.

[0005]

A method of manufacturing a semiconductor device according to a first aspect of the present invention is to form wiring on a semiconductor substrate, and to form a layer made of a material different from the wiring on the semiconductor substrate. Then, a step of performing patterning, a step of forming a layer to be the wiring on the pattern, and an etchback process of the layer to be the wiring to form a side wall on the line portion of the pattern. The process and the process of removing the different material are performed.

A method of manufacturing a semiconductor device according to a second aspect of the present invention is to form a mask pattern on a semiconductor substrate and to form a mask pattern on a region to be etched on the semiconductor substrate.
A step of forming a layer made of a material different from the region to be etched and the mask pattern and performing patterning to form a predetermined island shape, and forming a layer to be the mask pattern on the island shape part The step of performing the etching, the step of etching back the layer to be the mask pattern to form the side wall on the island-shaped portion, and the step of removing the island-shaped portion are performed.

In the method for manufacturing a semiconductor device according to the third aspect of the present invention, the region to be etched is made of a wiring material, etching is performed using the mask pattern remaining as the sidewall as a mask, and the region to be etched is used as a wiring. It is to be processed. The wiring material may be either a substance having conductivity itself or a substance having conductivity by doping impurities, for example, LS.
Materials used in the I technology include polycrystalline silicon, single crystal silicon, aluminum, tungsten, titanium,
Conductive materials such as chromium, nickel, iron, copper, gold, silver, platinum, alloys of these, or compounds of these with silicon are used.

The material different from the wiring material may be an insulating material or a conductive material such as silicon oxide, silicon nitride, polycrystalline silicon, and aluminum alloy. The material of the mask pattern may be any material such as conductivity or insulation, as long as it is different from the material of the region to be etched.

[0009]

That is, if the island-shaped portion is removed after forming the side wall made of the wiring material on the island-shaped portion made of a material different from the wiring material, only the side wall remains, and this can be used as wiring. Since the line width of the wiring is determined by the width of the side wall, that is, the thickness of the wiring layer, the dimension smaller than the lithography is possible.

Similarly, if a side wall made of a mask pattern material is formed on an island-shaped portion made of a material different from that of the region to be etched and the mask pattern, and then the island-shaped portion is removed, a mask having dimensions smaller than lithography can be obtained. A pattern is formed. Further, if the etched region is formed of a wiring material, the wiring having a width equal to or smaller than the lithography can be obtained by etching using the mask pattern as a mask.

[0011]

EXAMPLE A first example of the present invention will be described with reference to FIG. 1A to 1C are sectional views sequentially showing a manufacturing process of a semiconductor device according to the present invention. Step 1: A silicon oxide film 2 is formed on the semiconductor substrate 1 by a thermal oxidation method, a CVD method or the like, and a local oxidation method (L
A field oxide film 3 is formed by OCOS (see FIG. 1).
A).

Step 2: The silicon nitride film 4 having a high etching selection ratio with respect to the silicon oxide film 3 is formed by CVD.
The resist 5 is deposited to a thickness of 2 μm, and the resist 5 is patterned through operations such as lithography technology, mask exposure, and development. At this time, the line portion of the pattern is located above the field oxide film 3 and its width is set larger than that of the oxide film 3 (that is, the line portion of the pattern is formed so as to straddle the oxide film 3). However, only the desired line portion is required) (FIG. 1B).

Step 3: RI using the resist 5 as a mask
After etching the silicon nitride film 4 by the E method,
The resist is removed by oxygen plasma ashing, wet treatment using hot sulfuric acid, or the like, and the silicon nitride film 4 is processed into an island shape (hereinafter referred to as an island shape portion 4a). This island-shaped portion 4a naturally has the same width as the line portion of the resist 5 (FIG. 1C).

Step 4: Silicon oxide film 2 and island-shaped portion 4
A polycrystalline silicon film 6 is deposited on the surface a by 0.1 μm by the low pressure CVD method. (FIG. 1D) Step 5: This polycrystalline silicon film 6 is etched back by RIE to form sidewalls 7 of 0.1 μm width made of polycrystalline silicon material on the island-shaped portion 4a (FIG. 1).
E).

Step 6: Chemical dry etching (CD
When the island-shaped portion 4a (silicon nitride film 4) is removed by E) or a wet treatment using hot phosphoric acid, a gate electrode pattern 8 made of a polycrystalline silicon material and having a width of 0.1 μm is formed on the silicon oxide film 2. Formed (FIG. 1F). To give conductivity to the polycrystalline silicon 6 (7, 8), it is sufficient to dope P, As, B or the like, as is well known. Specifically, in the step 4, CV
PH ₃ is added to D, ion implantation is performed in any of the steps 4 to 6, and thermal diffusion is performed by POCl _{3 in the} step 4.

As described above, according to the present invention, a desired line width can be obtained even if the thickness is 0.5 μm or less simply by changing the film thickness of the polycrystalline silicon in the step 4. In the embodiment, the formation of the gate electrode pattern as the wiring is taken as an example, but it can be applied to the formation of all patterns such as line patterns of bit lines and signal lines.

Next, a second embodiment in which the technique of this embodiment is applied for forming a mask pattern will be described with reference to FIGS. 2 to 4. 2 to 4 are sectional views sequentially showing the manufacturing process of the semiconductor device in this embodiment. Step: A silicon oxide film 10 is formed on the semiconductor substrate 9 by a thermal oxidation method, a CVD method, or the like, and a field oxide film 11 is formed by a local oxidation method (LOCOS) (FIG. 2A).

Step: A polycrystalline silicon film 12 having a thickness of about 0.3 μm is deposited on the entire surface of the substrate formed in the step by a low pressure CVD method, and phosphorus (P) is doped to give conductivity (FIG. 2B). ). Process: A silicon oxide film 13 having a high etching selectivity with respect to the polycrystalline silicon film 12 is formed by a CVD method.
Deposit 5 μm (FIG. 2C).

Step: A resist 14 is patterned on the silicon oxide film 13 through operations such as lithography technology, exposure and development. At this time, the line portion of the resist 14 is located above the field oxide film 11 and its width is set larger than that of the oxide film 11 (that is, the line portion is formed so as to extend over the oxide film 11, However, only the desired line portion is required) (FIG. 2D).

Process: R using the resist 14 as a mask
After the silicon oxide film 13 is anisotropically etched by the IE method, the resist is removed by oxygen plasma ashing or wet treatment using hot sulfuric acid to process the silicon oxide film 13 into an island shape (hereinafter, island shape). Part 13a). This island-shaped portion 13a naturally has the same width as the line portion of the resist 14 (FIG. 3E).

Step: A silicon nitride film 15 is deposited to a thickness of 0.1 μm on the polycrystalline silicon film 12 and the island-shaped portion 13a by a low pressure CVD method. (FIG. 3F) Step: The silicon nitride film 15 is etched back by RIE to form a sidewall 16 of a silicon nitride film material having a width of 0.1 μm only on the side surface of the island-shaped portion 13a (FIG. 3G). .

Step: The island-shaped portion 13a (silicon oxide film 13) is formed by wet treatment using diluted hydrofluoric acid or the like.
Is removed, a mask pattern 17 made of a silicon nitride film material and having a width of 0.1 μm is formed on the polycrystalline silicon film 12.
(Sidewall 16) is formed (FIG. 3H). Process: Using this mask pattern 17 as a mask, RI
After the polycrystalline silicon film 12 is anisotropically etched by the E method (FIG. 4I), the mask pattern 17 is removed by using hot phosphoric acid or the like. The gate electrode 18 made of a 1 μm polycrystalline silicon material is formed (FIG. 4J).

As described above, according to the present invention, it is possible to change the film thickness of the silicon nitride film in the process.
Even if the thickness is 0.5 μm or less, a desired mask pattern can be obtained. In the second embodiment, an example in which a fine mask pattern is formed on polycrystalline silicon and a gate electrode having a fine width is processed is shown. However, for example, it is formed on the lower electrode of the stack type capacitor, There are various application methods such as etching the lower electrode to increase its surface area.

[0024]

According to the method of manufacturing a semiconductor device of the present invention, a wiring pattern or a mask pattern having a fine width exceeding the limit can be formed by the conventional photolithography technique.

[Brief description of drawings]

FIG. 1 is a sectional view sequentially showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view sequentially showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view sequentially showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view sequentially showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

 1, 9 Semiconductor substrate 4 Silicon nitride film (layer made of different material) 4a Island-shaped portion 6 Polycrystalline silicon film (layer to be wiring) 7, 16 Sidewall 8 Gate electrode pattern (wiring) 12 Polycrystalline silicon film (to be etched) Area 13 Silicon oxide film (layer made of different material) 13a Island-shaped portion 15 Silicon nitride film (layer to be mask pattern) 17 Mask pattern

Claims (3)

[Claims] 1. A process for forming a wiring on a semiconductor substrate, wherein a layer made of a material different from that of the wiring is formed on the semiconductor substrate, patterned, and processed into a predetermined island shape. And a step of forming a layer to be the wiring on the island-shaped portion, a step of etching back the layer to be the wiring to form a sidewall on the island-shaped portion, and removing the island-shaped portion. A method of manufacturing a semiconductor device, comprising: 2. A pattern for forming a mask pattern on a semiconductor substrate, wherein a layer made of a material different from the etched region and the mask pattern is formed on the etched region on the semiconductor substrate. Processing to form a predetermined island shape, a step of forming a layer serving as the mask pattern on the island shaped portion, and a step of etching back the mask pattern layer to form the island shaped portion. A method of manufacturing a semiconductor device, which comprises performing a step of forming a side wall and a step of removing the island-shaped portion. 3. The etching target region is formed of a wiring material, etching is performed using the mask pattern remaining as the side wall as a mask, and the etching target region is processed as a wiring. Manufacturing method of semiconductor device.