JPH03276633A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03276633A
JPH03276633A JP7611490A JP7611490A JPH03276633A JP H03276633 A JPH03276633 A JP H03276633A JP 7611490 A JP7611490 A JP 7611490A JP 7611490 A JP7611490 A JP 7611490A JP H03276633 A JPH03276633 A JP H03276633A
Authority
JP
Japan
Prior art keywords
etching
residue
electrode layer
gate electrode
isotropic etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7611490A
Other languages
Japanese (ja)
Inventor
Toshiaki Kuniyasu
利明 国安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP7611490A priority Critical patent/JPH03276633A/en
Publication of JPH03276633A publication Critical patent/JPH03276633A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To highly precisely form a fine gate electrode layer free from short- circuiting, by quickly eliminating poly silicon residue generated by anisotropic etching, without damaging a substrate, by using isotropic etching. CONSTITUTION:A resist layer 14 is stuck on the upper part turning to a gate electrode layer, and a poly silicon film 13 is anisotropically etched by using the resist layer 14 as a mask, thereby forming a gate electrode layer 15. As the result, residue 16 of poly silicon is formed at a step-difference part of an insulating film 12. Then the residue 16 is eliminated by performing isotropic etching without eliminating the resist layer 14. The isotropic etching is performed under the condition that RF power is 60-120W, by using mixed gas of SF6, He, CCl4, CF4 plasma as etching gas. Hence etching equivalent to the vertical direction can be performed also in the horizontal direction, so that the residue 16 can be quickly eliminated.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は半導体装置の製造方法に関し、特に電極・配線
の形成方法の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming electrodes and wiring.

(ロ)従来の技術 近年、半導体集積回路の高集積化に伴なって電極・配線
の寸法も微細化される方向にある。
(b) Prior Art In recent years, as semiconductor integrated circuits have become more highly integrated, the dimensions of electrodes and wiring have also become smaller.

一般に、正確で微細な寸法をもって、短絡等をともなう
ことなくかかる電極・配線を加工する方法として異方性
エツチングが用いられている。
Generally, anisotropic etching is used as a method for processing such electrodes and wiring with accurate and minute dimensions without causing short circuits or the like.

第2図A乃至第2図りに従来の半導体装置の製造方法を
示す。
A conventional method for manufacturing a semiconductor device is shown in FIGS. 2A and 2B.

まず第2図Aに示す如く、シリコン基板(1)上にSi
n、より成る絶縁膜(2)を形成する。
First, as shown in FIG. 2A, Si is placed on a silicon substrate (1).
An insulating film (2) made of n.

ここで絶縁膜(2)は急峻な段差形状を有しているが、
このような形状はフィールド酸化膜の端部等で一般に形
成されるものである。
Here, the insulating film (2) has a steep step shape,
Such a shape is generally formed at the edge of a field oxide film.

続いてポリシリコン膜(3)をLPCVD法によって堆
積する。
Subsequently, a polysilicon film (3) is deposited by the LPCVD method.

次に第2図Bに示す如く、ゲート電極層となる部分上方
にレジスト層(4)を被覆し、続いて第2図Cに示す如
くレジスト層(4〉をマスクとしてボッシリコン膜〈3
)にSF、プラズマ等のエツチングガスを用いて異方性
エツチング処理を施し、ゲート電極N(5)を形成する
Next, as shown in FIG. 2B, a resist layer (4) is coated above the portion that will become the gate electrode layer, and then, as shown in FIG.
) is subjected to an anisotropic etching process using an etching gas such as SF or plasma to form a gate electrode N(5).

かかる異方性エツチング処理によれば、エツチングガス
はポリシリコン膜(3)に対して垂直方向のみに作用す
るのでサイドエツチング量をきわめて小さくすることが
でき、微細なゲート電極層(5)を精度良く加工するこ
とができる。
According to this anisotropic etching process, since the etching gas acts only in the vertical direction on the polysilicon film (3), the amount of side etching can be extremely small, and the fine gate electrode layer (5) can be formed with high precision. It can be processed well.

しかしながら、絶縁膜(2)の段差部分上のポリシリコ
ン膜(3)の垂直方向の膜厚は、ゲート電極層(5)の
膜厚に比べて厚くなるために、異方性エツチングの結果
としてこの部分にポリシリコンの残渣(6)が形成され
、この残渣(6)を介して電極層間の短絡を招くという
問題がある。
However, since the vertical film thickness of the polysilicon film (3) on the stepped portion of the insulating film (2) is thicker than the film thickness of the gate electrode layer (5), as a result of anisotropic etching, There is a problem in that a polysilicon residue (6) is formed in this portion, causing a short circuit between the electrode layers through this residue (6).

また、異方性エツチングを施す前にポリシリフン膜(3
)上にマスク作用を有する異物(酸化膜もしくはパーテ
ィクル)が付着している場合、異方性エツチングによっ
てこの異物下方に柱状残渣が形成されるという問題もあ
る。
Also, before anisotropic etching, a polysilicon film (3
) If foreign matter (oxide film or particles) having a masking effect is attached to the surface of the substrate, there is a problem that columnar residues are formed under the foreign matter due to anisotropic etching.

この点に関して従来技術においては、これらの残渣を取
り除くためにオーバーエツチング量を増やすという方法
がとられていた。
In this regard, the conventional technique has been to increase the amount of overetching in order to remove these residues.

(ハ〉発明が解決しようとする課題 しかしながらこのような方法で残渣を完全に除去するの
は困難であった。
(c) Problems to be Solved by the Invention However, it is difficult to completely remove the residue using this method.

しかも第1図りに示す如く異方性エツチング処理のオー
バーエツチング量を増やすと、絶縁膜(2)も同時にエ
ツチングされるので、絶縁膜(2)の薄い部分が全く除
去され、シリコン基板(1)に結晶欠陥等のダメージを
与えるという問題がある。
Moreover, as shown in the first diagram, when the overetching amount of the anisotropic etching process is increased, the insulating film (2) is also etched at the same time, so that the thin part of the insulating film (2) is completely removed and the silicon substrate (1) is etched. There is a problem in that it causes damage such as crystal defects.

本発明は斯上の問題点に鑑みて創作きれたものであり、
異方性エツチング時に生じる残渣をダメージを伴うこと
なく除去した電極・配線の形成方法を提供することを目
的としている。
The present invention was created in view of the above problems,
The object of the present invention is to provide a method for forming electrodes and wiring in which residues generated during anisotropic etching can be removed without causing damage.

(ニ)課題を解決するための手段 本発明は、半導体基板上に絶縁膜を介して導電膜を被着
する工程と、前記導電膜に選択的に異方性エツチングを
施して所定の領域に電極層を形成する工程と、前記所定
の領域以外に残存する前記導電膜の残渣を除去するため
に等方性エツチングを施す工程とを具備することを特徴
としている。
(d) Means for Solving the Problems The present invention comprises a step of depositing a conductive film on a semiconductor substrate via an insulating film, and selectively anisotropically etching the conductive film in a predetermined region. The method is characterized by comprising a step of forming an electrode layer, and a step of performing isotropic etching to remove residues of the conductive film remaining in areas other than the predetermined regions.

(*)作用 本発明によれば、異方性エツチングによって生した導電
膜の残渣に等方性エツチングを施すことによって、主と
して等方性エツチングの水平方向成分を利用して残渣を
すみやかにかつ完全に除去することができる。
(*) Function According to the present invention, by applying isotropic etching to the residue of the conductive film produced by anisotropic etching, the residue can be quickly and completely removed mainly by using the horizontal component of isotropic etching. can be removed.

しかも等方性エツチングにおいてはポリシリコン膜の絶
縁膜に対するエツチング選択比を異方性エツチングに比
べて大きくとることが可能なので、絶縁膜のエツチング
量が少なくて済み、基板にダメージを与えるおそれがな
い。
Moreover, in isotropic etching, the etching selectivity of the polysilicon film to the insulating film can be made larger than in anisotropic etching, so the amount of etching of the insulating film is small, and there is no risk of damaging the substrate. .

この結果、微細な寸法の電極・配線を、短絡をともなう
ことなく高精度に形成することができる。
As a result, electrodes and wiring with minute dimensions can be formed with high precision without causing short circuits.

(へ)実施例 次に第1図A乃至第1図りを参照しながら本発明の実施
例を詳細に説明する。
(F) Embodiment Next, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1D.

まず第1図Aに示す如く、シリコン基板(11〉上にS
in、より成る絶縁膜(12)を形成する。
First, as shown in Figure 1A, a silicon substrate (11) is
An insulating film (12) made of in.

続いてポリシリコン膜(13)をLPCVD法によって
4000人の厚さに堆積する。
Subsequently, a polysilicon film (13) is deposited to a thickness of 4000 nm using the LPCVD method.

ここでポリシリコン膜(13)上に高融点金属シリサイ
ド膜を形成してもよい。
Here, a refractory metal silicide film may be formed on the polysilicon film (13).

次に第2図Bに示す如く、ゲート電極層となる部分上方
にレジスト層(14)を被着し、続いて第2図Cに示す
如くレジスト層(14)をマスクとしてポリシリコン膜
(13)に異方性エツチング処理を施してゲート電極層
(15)を形成する。
Next, as shown in FIG. 2B, a resist layer (14) is deposited above the portion that will become the gate electrode layer, and then as shown in FIG. 2C, using the resist layer (14) as a mask, a polysilicon film (13) is deposited. ) is subjected to an anisotropic etching process to form a gate electrode layer (15).

ココで、異方性エツチングはエツチングガスにSF、プ
ラズマを用い、RFパフ−150〜200Wの条件にて
行なう。
Here, the anisotropic etching is performed using SF and plasma as etching gas under the condition of RF puff -150 to 200W.

この結果、絶縁膜(1,2)の段差部にはポリシリコン
の残渣(16)が形成される。
As a result, polysilicon residues (16) are formed in the stepped portions of the insulating films (1, 2).

続いてレジスト層(14)を除去せずに等方性エツチン
グ処理を施して残渣(16)を除去する。
Subsequently, isotropic etching is performed to remove the residue (16) without removing the resist layer (14).

ここで、等方性エツチングはエツチングガスにSF、、
He、CCj!、、CF、プラズマの混合ガスを用い、
RFパワー60〜120Wの条件にて行なうことによっ
て水平方向に対しても垂直方向と等価のエツチングをす
ることができるので、残渣(16)をすみやかに除去す
ることができる。
Here, in isotropic etching, the etching gas is SF,
He, CCj! , , using a mixed gas of CF and plasma,
By performing the etching under the condition of RF power of 60 to 120 W, it is possible to perform etching in the horizontal direction equivalent to that in the vertical direction, so that the residue (16) can be promptly removed.

また、マスク作用を有する異物(酸化膜もしくはパーテ
ィクル)に起因する柱状残渣も同時に除去可能である。
Further, columnar residues caused by foreign substances (oxide films or particles) having a masking effect can also be removed at the same time.

さらに上記の等方性エツチングでは、ポリシリコンのS
in、に対するエツチング選択比は30:工程度と異方
性エツチングに比べて2倍程度の選択比にすることが可
能であるので、絶縁膜(12)のエツチング量を小さく
することができ、基板(11)にダメージを与えるおそ
れがないという利点もある。
Furthermore, in the isotropic etching described above, S of polysilicon is
The etching selectivity ratio for the insulating film (12) can be set to 30:2, which is about twice that of anisotropic etching. There is also the advantage that there is no risk of damaging (11).

以上のように本発明の実施例によれば、異方性エツチン
グによって生じたポリシリコン残渣を等方性エツチング
を用いることによっ1基板(11)ニダメージを与える
ことなくすみやかに除去できるので、短絡をともなうこ
とのない微細なゲート賞極層(15)を高精度に形成す
ることが可能である。
As described above, according to the embodiment of the present invention, the polysilicon residue generated by anisotropic etching can be quickly removed without damaging one substrate (11) by using isotropic etching. It is possible to form a fine gate electrode layer (15) with high precision without causing any damage.

(ト)発明の詳細 な説明したように、本発明によれば異方性エツチングに
よって生じた導電膜の残渣を除去するための等方性エツ
チング工程を具備しているので、微細な寸法の電極・配
線を短絡をともなうことなく高精度に形成することがで
きる。
(G) As described in detail, the present invention includes an isotropic etching process for removing conductive film residues caused by anisotropic etching, so that electrodes with minute dimensions can be removed. - Wiring can be formed with high precision without causing short circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A乃至第1図りは本発明の実施例に係る半導体装
置の製造方法を示す断面図、 第2図A乃至第2図りは従来例に係る半導体装置の製造
方法を示す断面図である。
1A to 1D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2D are cross-sectional views showing a method for manufacturing a semiconductor device according to a conventional example. .

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜を介して導電膜を被着する
工程と、 前記導電膜に選択的に異方性エッチングを施して所定の
領域に電極層を形成する工程と、 前記所定の領域以外に残存する前記導電膜の残渣を除去
するために等方性エッチングを施す工程とを具備するこ
とを特徴とする半導体装置の製造方法。
(1) a step of depositing a conductive film on a semiconductor substrate via an insulating film; a step of selectively anisotropically etching the conductive film to form an electrode layer in a predetermined region; A method for manufacturing a semiconductor device, comprising the step of performing isotropic etching to remove residues of the conductive film remaining in areas other than the regions.
(2)前記電極層をゲート電極層とすることを特徴とす
る請求項第1項記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the electrode layer is a gate electrode layer.
JP7611490A 1990-03-26 1990-03-26 Manufacture of semiconductor device Pending JPH03276633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7611490A JPH03276633A (en) 1990-03-26 1990-03-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7611490A JPH03276633A (en) 1990-03-26 1990-03-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03276633A true JPH03276633A (en) 1991-12-06

Family

ID=13595875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7611490A Pending JPH03276633A (en) 1990-03-26 1990-03-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03276633A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1012613A (en) * 1996-06-21 1998-01-16 Nec Corp Semiconductor device
US6139647A (en) * 1995-12-21 2000-10-31 International Business Machines Corporation Selective removal of vertical portions of a film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6139647A (en) * 1995-12-21 2000-10-31 International Business Machines Corporation Selective removal of vertical portions of a film
JPH1012613A (en) * 1996-06-21 1998-01-16 Nec Corp Semiconductor device

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