JPH1012613A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent very small unetched parts from being left on conductors at the step sections of an interlayer insulating film without performing flattening treatment by forming conductors which are not used as elements nor wiring at the step sections and their vicinities at the time of forming conductors on the interlayer insulating film having the steps as elements or wiring. SOLUTION: In a semiconductor device in which conductors 6 are formed as elements or wiring on an interlayer insulating film 5 having steps, conductors 9 which are not used as elements nor wiring are formed at the step sections and their vicinities. For example, after a capacitive element is constituted of a lower capacitor electrode 2, capacitor insulating film 4, and upper capacitor electrode 3 on a field insulating film 1, a first insulating film 5 is formed on the capacitive element as the interlayer insulating film. Then polysilicon which is used as a resistor 6 is grown on the insulating film 5 and the polysilicon is patterned to a desired shape. When the polysilicon is patterned, side-wall polysilicon 9 is simultaneously formed by patterning the polysilicon at the step sections of the film 5 and, thereafter, a second insulating film 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure of a semiconductor device having a stepped shape.

[0002]

2. Description of the Related Art FIG. 3 shows, as an example of a conventional semiconductor device having a stepped shape, a structure in which a resistor 6 (polysilicon) is formed on a capacitive element via an interlayer insulating film 5 (first insulating film). Is shown. When forming a resistor without flattening the interlayer insulating film, if a resistive material (polysilicon) is patterned by anisotropic etching in order to form a resistor with high accuracy, the step of the interlayer insulating film due to the capacitive element Polysilicon etching residue 11 occurs in the portion.

Another conventional example is disclosed in JP-A-61-9.
In 4342, there is an example of patterning polysilicon on a step. In the conventional example, after the polysilicon on the interlayer insulating film is patterned, the polysilicon etching residue at the step portion is selectively oxidized to a non-conductive material, thereby preventing a short circuit due to the polysilicon etching residue.

[0004]

As described above, in a conventional semiconductor device having a stepped shape in an interlayer insulating film, when a conductive film is patterned on the interlayer insulating film by anisotropic etching, etching is performed in the stepped portion. The rest occurs. Since the etching residue is fine and easily peeled off, there are problems such as contamination of the production line, and re-adhesion of the peeled one, thereby lowering the product yield. When the interlayer insulating film is flattened to eliminate a step, the number of steps increases, and thus there is a problem that manufacturing costs increase.

In Japanese Unexamined Patent Application Publication No. Sho 61-94342, the polysilicon etching residue is oxidized to make it non-conductive, but the fine etching residue is still easily peeled off, and the above problem cannot be solved.

[0006]

According to the semiconductor device of the present invention, when a conductor is formed as an element or a wiring on an interlayer insulating film having a step, a conductor which is not used as an element or a wiring in the step portion and in the vicinity thereof. Is formed.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a plan view showing an embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA ′ of FIG. A capacitance element is formed on the field insulating film 1 by a capacitor lower electrode 2 of about 2000 ° polysilicon, a capacitor insulating film 4 of an oxide film of about 400 °, and a capacitor upper electrode 3 of about 2000 ° tungsten silicide. Then, a first insulating film 5 was grown as an interlayer insulating film by about 1000 °. The first
Polysilicon used as the resistor 6 on the insulating film 5 is about 2
After the growth of 000 °, patterning into a desired shape is performed by photolithography. At this time, the side wall polysilicon 9 is formed by patterning the step portion of the first insulating film 5 at the same time. The sidewall polysilicon 9 is not used as an element or a wiring, and is in an electrically floating state. Thereafter, the second insulating film 7 is grown and planarized, and the contact hole 8 is opened to realize the structure of the present invention.

FIGS. 2A and 2B show the structure of another embodiment of the present invention, wherein FIG. 2A is a plan view and FIG. 2B is a sectional view taken along line AA 'of FIG. In this embodiment, when the capacitor lower electrode 2 is patterned simultaneously with the gate electrode of the MOS transistor (not shown), and the spacer side wall is formed on the gate electrode, the capacitor lower electrode 2 is simultaneously formed on the capacitor lower electrode 2. Is formed, the corners of the steps of the first insulating film 5 are relaxed, so that the area of the side-wall polysilicon 9 can be reduced as shown in FIG. The degree of freedom in layout could be expanded.

[0010]

As described above, in a semiconductor device having a stepped shape in an interlayer insulating film, a structure in which a conductor which is not used as an element or a wiring is formed in the stepped portion and in the vicinity of the stepped portion makes it possible to reduce the conductive property in the stepped portion. Fine etching residue of the body can be eliminated. Thereby, it is possible to prevent the conductor from peeling off and contaminating the production line. Further, since the fine etching residue does not peel off and re-attach, the product yield can be improved. In the semiconductor device of the present invention, the same yield as that of a product that has been subjected to a flattening process so that no etching residue occurs at the stepped portion can be obtained, and about 10 flattening processes can be eliminated.

[Brief description of the drawings]

FIG. 1A is a plan view illustrating a structure of a semiconductor device according to an embodiment of the present invention; (B) is an AA 'line cross-sectional view of (a).

FIG. 2A is a plan view showing the structure of a semiconductor device according to another embodiment of the present invention. (B) is an AA 'line cross-sectional view of (a).

FIG. 3 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 field insulating film 2 capacitor lower electrode 3 capacitor upper electrode 4 capacitor insulating film 5 first insulating film 6 resistor (polysilicon) 7 second insulating film 8 contact hole 9 sidewall polysilicon 10 side wall 11 polysilicon etching residue

Claims (1)

[Claims] 1. A semiconductor device in which a conductor is formed as an element or a wiring on an interlayer insulating film having a step,
A semiconductor device, wherein a conductor not used as an element or a wiring is formed in a step portion and in the vicinity thereof.