JPH0417363A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a fine gate electrode to be formed accurately and preventing etching residue from remaining at a lower electrode level difference part by forming an upper electrode by performing metaanisotropic etching of a polysilicon film while a gate electrode which is formed accurately is protected by a mask layer. CONSTITUTION:After a field oxide film 2 is formed on a substrate 1, a lower electrode 3 is formed, the substrate 1 is exposed, a gate oxide film 4 is formed, a dielectric body film 5 is formed on the lower electrode 3, and then a polysilicon film 6 is formed on the entire surface. Then, the polysilicon film 6 is etched by anisotropic etching using mask layers 7a and 7b which are formed on a region corresponding to the lower electrode and on a larger region than a region corresponding to the upper electrode for forming a gate electrode 8. Then, the mask layers 7a and 7b are eliminated, a mask layer 9a is further formed on the entire surface, a mask layer 9b is formed on a region corresponding to the upper electrode, an upper electrode 10 is formed by etching the polysilicon film 6 by mesaanisotropic etching, and the mask layers 9a and 9b are eliminated.

Description

[Detailed Description of the Invention] [Summary] Regarding a method of manufacturing a semiconductor device, the present invention provides a method for manufacturing a semiconductor device that can prevent etching residue from remaining on a step portion of a lower electrode and can form a fine gate electrode with high precision. The purpose of the present invention is to provide a manufacturing method, which includes the steps of: forming a first conductive film pattern on a base film; forming an insulating film to cover the first conductive film pattern; a step of forming a second conductive film on a base film so as to cover the film; and a step formed in the second conductive film by a region corresponding to the gate electrode and the first conductive film pattern. removing the second conductive film by anisotropic etching leaving a region including a portion of the second conductive film to form a gate TLA electrode and a residual film of the second conductive film; and covering the gate electrode. selectively forming a mask layer in a region corresponding to the second conductive film pattern on the mask layer and the residual film of the second conductive film; and forming a second conductive film pattern by quasi-anisotropic or isotropic etching of the conductive film, or forming a first conductive film pattern on the underlying film. a step of forming an insulating film to cover the first conductive film pattern; a step of forming a second conductive film on the underlying film to cover the insulating film; the second conductive film pattern so as to leave a larger area than the area on the second conductive film pattern on the conductive film and the area corresponding to the gate electrode.
a step of removing the conductive film by quasi-anisotropic or isotropic etching and leaving a second conductive film pattern and a residual film of the second conductive film; and the second conductive film pattern. and forming a mask layer so as to cover the first conductive film pattern, and forming a mask layer in a region corresponding to the gate electrode on the second conductive crotch; and forming a gate electrode by anisotropically etching the remaining film of the second conductive film.

[Industrial application field]

The present invention can be applied to a method of manufacturing a semiconductor device having a MOS transistor and a capacitor, and particularly relates to a method of manufacturing a semiconductor device that can form a fine gate electrode with high precision.

As semiconductor devices have become smaller and more sophisticated in recent years, there has been an increasing demand for the integration of various film patterns. Therefore, it is necessary to use the most suitable processing method for each pattern.

[Conventional technology]

FIGS. 3(a) to 3(d) are diagrams illustrating a conventional method of manufacturing a semiconductor device. In FIG. 3, 31 is a substrate made of Sr, etc., 32 is a field oxide film made of 5jO2, etc., 33 is a lower electrode made of poly-Si, etc., and 34 is, for example, Sr.
A gate oxide film 35 made of iC2 or the like is, for example, SiC2.
36 is a polysilicon film, 37a,
37b is a mask layer made of resist or the like, 38 is poly 81
39 is an upper electrode made of poly-Si or the like.

Next, the manufacturing method will be explained.

First, a silicon oxide film and a silicon nitride film are formed by depositing 5in2 and S 3N4 on the substrate 31 by, for example, the CVD method, and a mask made of the silicon nitride film is formed by patterning the silicon nitride film by, for example, RIE. Using a mask made of silicon nitride film, LOGO3
After oxidizing the substrate 31 to form a field oxide film 32 having a thickness of, for example, 6000, the silicon nitride film used as a mask is removed. Next, poly-Si is deposited to a thickness of, for example, 4000 on the entire surface by, for example, the CVD method, and the lower electrode 33 is formed by selectively etching the poly-Si and the silicon oxide film by, for example, RIE.
After exposing the substrate 31, the substrate 31 and the lower electrode 33 are thermally oxidized to form a gate oxide film 34 on the substrate 31 with a thickness of, for example, 200 mm, and on the lower electrode 33 with a thickness of, for example, 300 mm. A dielectric film 35 is formed (see FIG. 3 (
a)).

Next, as shown in FIG. 3(b), a polysilicon film 36 having a film thickness of, for example, 4,000 is formed by depositing poly-Si over the entire surface by, for example, the CVD method, and after coating the entire surface with a resist, it is exposed to light.・The resist is patterned by development so that only the regions corresponding to the gate electrode and the upper electrode on the polysilicon film 36 remain, and the mask layers 37a, 37 are formed.
form b.

Next, as shown in FIG. 3(C), for example, SF.

The mask layer 3 is etched by quasi-anisotropic etching (isotropic etching may also be used) using a mixed gas of gas and C2ClF5 gas.
By etching the polysilicon film 36 using etching layers 7a and 37b, a gate electrode 38 and an upper electrode 39 are formed. At this time, a capacitor section consisting of the upper electrode 39, the dielectric film 35, and the lower electrode 33 is formed.

Next, as shown in FIG. 3(d), a mask layer 37a,
37b is removed.

Then, a semiconductor device can be obtained by forming a source/drain diffusion layer, a glabellar insulating film made of PSG or the like, a contact hole, a wiring layer made of A1 or the like, and the like.

The conventional semiconductor device manufacturing method described above uses mask layers 37a and 37b made of resist to form a polysilicon film 3.
The upper electrode 39 of the capacitor portion and the gate electrode 38 of the MOS FET were simultaneously formed by performing quasi-anisotropic or isotropic processing. In this manufacturing method, since the polysilicon film 36 is etched quasi-anisotropically or isotropically, there is an advantage that no etching residue is left on the stepped portion of the lower electrode 33, which may cause wiring shorts or dust. There is.

[Problem to be solved by the invention]

However, in the conventional semiconductor device manufacturing method described above, since the polysilicon film 36 is etched quasi-anisotropically or isotropically, side etching occurs and the gate electrode 3
8 cross sections tended to have a hemmed shape. Therefore, especially when forming a transistor with a short gate length and requiring strict precision, there is a problem in that it is difficult to form a fine gate electrode 38 pattern with high precision due to poor width control. If the gate electrode 38 has an extremely trailing shape, punch-through is likely to occur. Although the upper electrode 39 is also side-etched, it does not require much precision compared to the gate electrode 38.

As a means to solve the above problem, the polysilicon film 36
It is thought that anisotropic etching should be applied to the lower electrode 33 (see Fig. 3 (C)).
There was a problem in that etching residue remained on the surface (see the arrow).

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent etching residue from remaining on the step portion of the lower electrode and can form a fine gate electrode with high precision. It is said that

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the first invention includes the steps of forming a first conductive film pattern on a base film, and forming an insulating film so as to cover the first 'AN film pattern. forming a second conductive film on the underlying film so as to cover the insulating film; and forming a second conductive film on the base film so as to cover the insulating film, and Leaving an area containing the step part that occurs in the conductive film,
removing the second conductive film by anisotropic etching to form a gate electrode and a residual film of the second conductive film; and forming a mask layer and the second conductive film so as to cover the gate electrode. selectively forming a mask layer on a region corresponding to the second conductive film pattern on the residual film of the conductive film; and using the mask layer to form the second conductive film into a quasi-anisotropic or and forming a second conductive film pattern by isotropic etching.

In order to achieve the above object, the method for manufacturing a semiconductor device according to the second invention includes the steps of forming a first conductive film pattern on a base film, and forming an insulating film to cover the first conductive film pattern. a step of forming a second conductive film on the underlying film so as to cover the insulating film; a region on the second conductive film pattern on the second conductive film and a gate; removing the second conductive film by quasi-anisotropic or isotropic etching so as to leave a larger area than the area corresponding to the electrode;
a second conductive film pattern and a step of leaving a residual film of the second conductive film;
forming a mask layer so as to cover the conductive film pattern, and forming a mask layer in a region corresponding to the gate electrode on the second conductive film pattern; The method includes a step of anisotropically etching the remaining film to form a gate electrode.

[Effect]

As shown in FIGS. 1(a) to 1(g), the first invention includes a mask layer formed in an area larger than the area corresponding to the gate electrode and the area corresponding to the upper electrode on the polysilicon film 6. Since the gate electrode 8 is formed by anisotropically etching the polysilicon film 6 using the polysilicon films 7a and 7b, there is almost no side etching in the gate electrode 8, and the cross section of the gate electrode 8 does not have a skirted shape. The fine gate electrode 8 can be formed with high precision. Moreover, at this time,
A polysilicon film 6 larger than the upper electrode 10 remains under the mask layer 7b. Next, a mask layer 9a is formed on the polysilicon film 6 in a region corresponding to the upper electrode 10 so as to cover the accurately formed gate electrode 8;
The upper electrode 10 is formed by etching the polysilicon film 6 in a quasi-anisotropic (or isotropic) manner using the polysilicon film 9b.

In this way, the upper electrode 10 is formed by quasi-anisotropically etching the polysilicon film 6 while protecting the accurately formed gate electrode 8 with the mask layer 9a.
The fine gate electrode 8 can be formed with high precision, and no etching residue will be left on the three-step portion of the lower electrode.

The second invention is, as shown in FIGS. 2(a) to 2(d), a mask layer formed in an area larger than the area corresponding to the upper electrode and the area corresponding to the gate electrode on the polysilicon film 6. Since the upper electrode 10 is formed by quasi-anisotropic etching (isotropic etching is also acceptable) of the polysilicon film 6 using the polysilicon films 15a and 15b, etching residues are not left on the three-step portion of the lower electrode. It can be done. Moreover, at this time, the gate electrode 8 is under the mask layer 15a.
A larger polysilicon film 6 remains. Then,
A mask layer 16 is formed on the polysilicon film 6 in a region corresponding to the gate electrode 8 so as to cover the upper electrode 10.
The gate electrode 8 is formed by anisotropically etching the polysilicon film 6 using the layers a and 16b. In this way, with the upper electrode 10 protected by the mask layer 16b, the polysilicon film 6 is anisotropically etched to form the gate electrode 8.
As a result, the fine gate electrode 8 can be formed with high precision, and no etching residue will be left on the three-step portion of the lower electrode.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(g) are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. In Figure 1,
1 is a substrate made of sj etc., 2 is a field oxide film made of 5iQz etc., 3 is a lower electrode made of poly 81 etc., 4 is a gate oxide film made of 5in2 etc., 5 is a dielectric film made of SiO2 etc., 6 is a dielectric film made of SiO2 etc. Polysilicon film, 7a, 7b are mask layers made of resist etc. 8 are gate electrodes, 9a, 9b
10 is a mask layer made of resist or the like, and 10 is an upper electrode. For convenience, FIGS. 1 and 2 are not shown to the scale of the actual device.

Next, the manufacturing method will be explained.

First, SiO□ and S are deposited on the substrate 1 by, for example, the CVD method.
A silicon oxide film and a silicon nitride film are formed by depositing N. After oxidizing the substrate 1 to form a field oxide film 2 having a thickness of, for example, 6000, the silicon nitride film used as a mask is removed. Next, poly-Si is deposited on the entire surface by, for example, a CVD method to a film thickness of, for example, 4,000 mm.
After selectively etching the poly-Si and silicon oxide films by IE to form the lower electrode 3 and exposing the substrate 1, the substrate 1 and the lower electrode 3 are thermally oxidized to form a base viJ.
A gate oxide film 4 having a thickness of, for example, 200 wafers is formed thereon, and a dielectric film 5 having a thickness of, eg, 300 thinners is formed on the lower electrode 3 (FIG. 1(a)).

Next, as shown in FIG. 1B, poly-Si is deposited over the entire surface by, for example, the CVD method to form a polysilicon film 6 having a thickness of, for example, 4,000.

Next, as shown in FIG. 1(c), after applying a resist to the entire surface, exposure and development are performed to remove only an area larger than the area corresponding to the gate electrode and the area corresponding to the upper electrode on the polysilicon film 6. The resist is patterned so that the resist remains to form mask layers 7a and 7b. In addition, in the figure, the resist film is actually considerably larger than the thickness of the polysilicon film 6, so even if there is a step difference in the polysilicon film 60 due to the influence of the lower electrode, there is no corresponding step difference on the surface of the resist film. Not possible. Further, the same applies to the gate electrode and the capacitor portion.

Next, as shown in FIG. 1(d), the gate electrode 8 is etched by etching the polysilicon film 6 using the mask layers 7a and 7b by anisotropic etching using a mixed gas of CCβ4 gas and 02 gas, for example. Form. At this time, a polysilicon film 6 larger than the upper electrode is formed under the mask layer 7b.
remains.

Next, as shown in FIG. 1(e), mask layers 7a and 7b are formed.
is removed, and a resist is further coated on the entire surface, and then the resist is patterned by exposure and development to cover the gate electrode 8 to form a mask layer 9a, and a region corresponding to the upper electrode on the polysilicon film 6 is patterned. The mask layer 9b is formed by patterning the resist so that the resist remains on the mask layer 9b.

Next, as shown in FIG. 1(f), for example, SF.

The upper electrode 10 is formed by etching the polysilicon film 6 using mask layers 9a and 9b by quasi-anisotropic etching (isotropic etching may also be used) using a mixed gas of gas and Cz C12F s gas. At this time, a capacitor section consisting of the upper electrode 10, the dielectric film 5, and the lower electrode 3 is formed. Next, as shown in FIG. 1(g), the mask layers 9a and 9b are removed.

Then, source/drain diffusion layers, interlayer insulating films made of PSG, etc., contact holes, and AI! A semiconductor device can be obtained by forming a wiring layer or the like consisting of the following.

That is, in the above embodiment, the polysilicon film 6 is made anisotropic by using the mask layers 7a and 7b formed in an area larger than the area corresponding to the gate electrode and the area corresponding to the upper electrode on the polysilicon film 6. Gate electrode 8 by etching
As a result, the gate electrode 8 is hardly side etched, and the cross section of the gate electrode 8 does not have a skirted shape, so that a fine gate electrode 8 can be formed with high precision. Moreover, at this time, a polysilicon film 6 larger than the upper electrode 10 remains under the mask layer 7b.

Next, the polysilicon film 6 is made quasi-anisotropic using mask layers 9a and 9b formed on the polysilicon film 6 in a region corresponding to the upper electrode 10 so as to cover the accurately formed gate electrode 8. The upper electrode 10 is formed by etching (isotropic etching may also be used). In this way, the gate electrode 8 formed with high precision is connected to the mask layer 9.
Since the upper electrode 10 is formed by quasi-anisotropic etching of the polysilicon film 6 while protected by a, it is possible to form the fine gate electrode 8 with high accuracy, and also to form the fine gate electrode 8 at the three-step portion of the lower electrode. It is possible to avoid leaving etching residue.

In addition, in the present invention, as shown in FIG. 2(a),
Mask layers 15a and 15b made of resist are formed on the polysilicon film 6 in a region corresponding to the upper electrode and a region larger than the region corresponding to the gate electrode, and as shown in FIG. 5a and 15b, the polysilicon film 6 is subjected to quasi-anisotropic etching (isotropic etching may also be used) using, for example, a mixed gas of SF6 gas and CzCj2Fs gas to form the upper electrode 10, and a polysilicon film is etched under the mask layer 15b. Leaving the silicon 1116, Figure 2 (C
), the mask layers 15a and 15b are removed and a mask layer 16 made of resist is formed to cover the upper electrode 10.
After forming a mask layer 16b made of resist in a region corresponding to the gate electrode on the polysilicon film 6, as shown in FIG. 2(d), a mask Fi1 is formed.
6a and 16b to form the polysilicon film 6, for example CC1.
, gas and 0□ gas to form the gate electrode 8, and then the mask layers 16a, 16
It is also possible to remove b.

That is, in this embodiment, the polysilicon film 6 is made quasi-anisotropic using mask layers 15a and 15b formed in an area larger than the area corresponding to the upper electrode and the gate electrode on the polysilicon film 6. Since the upper electrode 10 is formed by etching (isotropic etching may also be used), it is possible to prevent etching residue from remaining on the three-step portion of the lower electrode. Moreover, at this time, a polysilicon film 6 larger than the gate electrode 8 remains under the mask layer 15a. Next, the polysilicon film 6 is anisotropically etched using mask layers 16a and 16b formed in regions corresponding to the gate electrode 8 on the polysilicon film 6 so as to cover the upper electrode 10, thereby forming the gate electrode 8. We are trying to form a In this way, since the gate electrode 8 is formed by anisotropically etching the polysilicon film 6 while the upper electrode 10 is protected by the mask layer 16b, the fine gate electrode 8 can be formed with high precision. At the same time, it is possible to prevent etching residue from remaining on the three-step portion of the lower electrode.

〔Effect of the invention〕

According to the present invention, it is possible to prevent etching residue from remaining on the step portion of the lower electrode, and a fine gate electrode can be formed with high precision.

7a, 7b, 9a, 9 b, 15a, 15b, 16 a, 16 b -・-・・-
Mask layer, 8...gate electrode, 10...-upper electrode.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the manufacturing method of one embodiment of the semiconductor device manufacturing method according to the present invention, FIG. 2 is a diagram for explaining the manufacturing method of another embodiment, and FIG. 3 is a diagram for explaining the manufacturing method of the conventional example. FIG. 2...Field oxide film, 3...Lower electrode, 5...Dielectric film, 6...Polysilicon film, 9a, 9b: Mask layer 1 Figure 1O: Diagram for explaining the manufacturing method of the embodiment.

Claims (1)

[Scope of Claims] [1] First conductive film pattern (3) on base film (2)
), and forming an insulating film ( ) to cover the first conductive film pattern (3).
5); forming a second conductive film (6) on the underlying film so as to cover the insulating film (5); The second conductive film (6) is removed by anisotropic etching, leaving a region including a stepped portion formed in the second conductive film due to the conductive film pattern, and the gate electrode (8) and the second conductive film (6) are removed by anisotropic etching. forming a residual film of the second conductive film (6) on the mask layer (9a) and the residual film of the second conductive film (6) so as to cover the gate electrode (8);
selectively forming a mask layer (9b) in a region corresponding to the conductive film pattern, and the mask layer (9a, 9b)
and forming a second conductive film pattern (10) by quasi-anisotropically or isotropically etching the second conductive film (6) using Method. [2] First conductive film pattern (3) on base film (2)
), and forming an insulating film ( ) to cover the first conductive film pattern (3).
forming a second conductive film (6) on the underlying film so as to cover the insulating film (5); removing the second conductive film (6) by quasi-anisotropic or isotropic etching so as to leave a larger area than the area on the second conductive film pattern and the area corresponding to the gate electrode; a step of leaving a residual film of the second conductive film pattern (10) and the second conductive film (6); and a step of leaving the second conductive film pattern (10) and the first conductive film pattern. forming a mask layer (16a) so as to cover the second conductive film (6), and forming a mask layer (16b) in a region corresponding to the gate electrode on the second conductive film (6); ) to anisotropically etch the remaining film of the second conductive film (6) to form a gate electrode (8).
) A method for manufacturing a semiconductor device, the method comprising: [3] Claim 1 or 2, wherein a capacitor portion is formed from the first conductive film pattern (3), the insulating film (5), and the second conductive film pattern (10). A method of manufacturing the semiconductor device described above.