JPS6081828A - Fine pattern forming process - Google Patents
Fine pattern forming processInfo
- Publication number
- JPS6081828A JPS6081828A JP19028983A JP19028983A JPS6081828A JP S6081828 A JPS6081828 A JP S6081828A JP 19028983 A JP19028983 A JP 19028983A JP 19028983 A JP19028983 A JP 19028983A JP S6081828 A JPS6081828 A JP S6081828A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- thin film
- active layer
- resist
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- 150000002739 metals Chemical class 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体基板上に微細な薄膜パターンを形成する
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of forming a fine thin film pattern on a semiconductor substrate.
周知のように、半導体装置等の製造においては高集積化
の要求にともない1μm以下の微細パターン形成技術が
必要とされている。微細パターン形成法には大別して、
■リフトオフ法及び■エツチング法がある。As is well known, in the manufacture of semiconductor devices and the like, with the demand for higher integration, techniques for forming fine patterns of 1 μm or less are required. Fine pattern formation methods can be roughly divided into
■Lift-off method and ■Etching method.
リフトオフ法は、まず第1図(、)に示すように、半導
体基板11上にホトレジストパターン12を形成し、そ
の上に所望の薄膜18を蒸着法等により被着形成する、
その後レジスト膜上に形成された薄膜の不要部分はレジ
ストと供に除去され、第1図(b)に示すように半導体
基板11上には必要な薄板21表表面体に薄膜28を被
着し、その上シーレジストパターン22′を形成する、
次に第1図Φ)に示すようにレジストパターンをマスク
として薄膜8を選択エツチングし、さらにレジストを除
去すれば所望の薄膜パターン23′が得られる。In the lift-off method, as shown in FIG. 1(, ), a photoresist pattern 12 is first formed on a semiconductor substrate 11, and a desired thin film 18 is deposited thereon by a vapor deposition method or the like.
Thereafter, unnecessary parts of the thin film formed on the resist film are removed together with the resist, and a thin film 28 is deposited on the surface of the thin plate 21 on the semiconductor substrate 11 as shown in FIG. 1(b). , forming a sea resist pattern 22' thereon,
Next, as shown in FIG. 1 Φ), the thin film 8 is selectively etched using the resist pattern as a mask, and the resist is further removed to obtain a desired thin film pattern 23'.
上記リフトオフ法、エツチング法におけるレジストパタ
ーンは通常密着露光法によって形成される。これは半導
体基板上に全面塗布したレジストをマスクパターンを介
して選択露光・現像してレジストパターンを形成する方
法である。微細なパターンを形成するためには、レジス
ト膜厚の均一性、ホトマスクとレジスト面の密着性の良
否が問題となる。The resist pattern in the above-mentioned lift-off method and etching method is usually formed by a contact exposure method. This is a method in which a resist coated on the entire surface of a semiconductor substrate is selectively exposed and developed through a mask pattern to form a resist pattern. In order to form a fine pattern, the uniformity of the resist film thickness and the adhesion between the photomask and the resist surface are important issues.
薄膜パターン84が形成されている半導体基板81表面
上の34ではさまれた間の領域31′に第2の薄膜パタ
ーンを形成する場合を考える。全面た塗布されたレジス
ト82の表面は平坦でなく、第1の薄膜84の端部の段
差のため領域81′の上方で低く段差d′が生じる。d
′の大きさは34間の距離りが小さくなれば小さくなる
が、領域31’上のレジスト厚dは他の部分に比べ厚く
なり、レジスト厚さの均一性が失なわれる。このd′及
びdの大きさは、第8図(b)に示すところの形成され
たレジストパターン82′の開口部32“の精度に影響
する。Lが太きければ、dは第1種の薄膜34」−のレ
ジスト厚シてほぼ等しいと考えられる。このときd′は
34の厚さにほぼ等しい。このときホトマスクは領域3
1′上のレジスト表面に密着せず、距離d′だけ離れる
。このため、寸法精度は悪くなり、開口部幅lはホトマ
スク上の寸法と異なる。Let us consider the case where a second thin film pattern is formed in a region 31' between 34 on the surface of the semiconductor substrate 81 where the thin film pattern 84 is formed. The surface of the resist 82 coated on the entire surface is not flat, and due to the step difference at the end of the first thin film 84, a low step d' occurs above the region 81'. d
The size of ' becomes smaller as the distance between the regions 34 becomes smaller, but the resist thickness d on the region 31' becomes thicker than on other parts, and the uniformity of the resist thickness is lost. The sizes of d' and d affect the accuracy of the opening 32'' of the formed resist pattern 82' as shown in FIG. 8(b). It is considered that the resist thicknesses of the thin film 34 are approximately equal. At this time, d' is approximately equal to the thickness of 34. At this time, the photomask is
It does not come into close contact with the resist surface on 1', but is separated by a distance d'. Therefore, the dimensional accuracy deteriorates, and the opening width l differs from the dimension on the photomask.
Lが小さい場合には、d′は小さく、マスクの密着性は
良くなるが、レジスト厚dが大きくなり、露光・現像条
件は34・上のレジスト開口32“′ と32“とで異
なることになる。したがって微細な開口部82“の寸法
精度を再現性良く制御するのは難しい。When L is small, d' is small and the mask adhesion is good, but the resist thickness d becomes large and the exposure and development conditions are different between the resist openings 32'' and 32'' above 34. Become. Therefore, it is difficult to control the dimensional accuracy of the minute opening 82'' with good reproducibility.
すなわち、半導体基板表面に既に第1種の薄膜パターン
が形成されており、表面に段差が存在する場合、レジス
ト膜厚の均一性、ホトマスクとレジスト面の密着性は両
立しなかった。That is, when the first type thin film pattern has already been formed on the surface of the semiconductor substrate and there is a step on the surface, uniformity of the resist film thickness and adhesion between the photomask and the resist surface are not compatible.
本発明は、このような不都合をなくシ、微細な薄膜パタ
ーンを形成する方法を提供するものである。The present invention eliminates such inconveniences and provides a method for forming fine thin film patterns.
以下GaAs ショットキー障壁電界効果トランジスタ
の製造工程を実施例として本発明の詳細な説明する。The present invention will be described in detail below using the manufacturing process of a GaAs Schottky barrier field effect transistor as an example.
第4図(a)において、半絶縁性GaAs 基板4,1
上に形成された活性層42の表面には、オーミック金属
パターン形成用のレジストパターン418が形成されて
いる。従来オーミック金属はこのレジストパターンをマ
スクとして被着形成後リフトオフされていた。したがっ
てGaAs 基板表面1=は前述のようにオーミック金
属の厚さ分(例えば約2oooX)の段差が生じてしま
う。本発明では、同図(b)のようにオーミック金属被
着前にレジストパターン48をマスクとして活性層42
をエツチングする工程を付加する。In FIG. 4(a), semi-insulating GaAs substrates 4, 1
A resist pattern 418 for forming an ohmic metal pattern is formed on the surface of the active layer 42 formed above. Conventionally, ohmic metals were deposited using this resist pattern as a mask and then lifted off. Therefore, as described above, a step equal to the thickness of the ohmic metal (for example, approximately 200X) is generated on the surface 1 of the GaAs substrate. In the present invention, the resist pattern 48 is used as a mask before the ohmic metal is deposited on the active layer 42, as shown in FIG.
Add an etching process.
このエツチング深さはオーミック金属厚さと同程度であ
る。This etching depth is comparable to the ohmic metal thickness.
この後オーミック金属44を被着形成し、リフトオフす
ればGaAs 基板表面は平坦なものとなる。Thereafter, an ohmic metal 44 is deposited and lifted off, so that the surface of the GaAs substrate becomes flat.
活性層とオーミック接触を得るため基板をN2 ガス中
で400℃4分間の熱処理を行なう。次に活性5一
層表面のオーミック金属間の領域4噸5にショットキー
ゲート金属パターンを形成する。ショットキー金属バク
ーン形成用のレジス) 4.6.はGaAs 表面が従
来法に比べ平坦なため、均一な厚さで塗布でき、したが
って微細なゲート(例えばゲート長0.5μm)形成用
の開口部4・7を精度良く形成できる。(同図(C))
。レジストパターン4,6を利用してゲート金属48を
リフトオフ形成すれば、同図(d)の工うにショットキ
ー障壁電界効果トランジスタを形成できる。In order to obtain ohmic contact with the active layer, the substrate is heat-treated at 400° C. for 4 minutes in N2 gas. Next, a Schottky gate metal pattern is formed in the regions 4 and 5 between the ohmic metals on the surface of the active layer 5. Resist for Schottky metal Bakoon formation) 4.6. Since the GaAs surface is flat compared to the conventional method, it can be coated with a uniform thickness, and therefore the openings 4 and 7 for forming fine gates (for example, gate length 0.5 μm) can be formed with high precision. (Same figure (C))
. By lift-off forming the gate metal 48 using the resist patterns 4 and 6, a Schottky barrier field effect transistor can be formed as shown in FIG. 4(d).
本発明により、形成されたショットキー障壁電界効果ト
ランジスタのゲート長しg は、ホトマスクパターンの
寸法に精度よく対応しており、従来法に比べて再現性良
く微細ゲートが得られる。The gate length g of the Schottky barrier field effect transistor formed according to the present invention corresponds precisely to the dimensions of the photomask pattern, and a fine gate can be obtained with better reproducibility than in the conventional method.
ゲート長Lg の短縮はトランジスタの高周波化に欠か
すことのできない課題であり、本発明によって、比較的
容易にこれを達成することができる。Reducing the gate length Lg is an indispensable task for increasing the frequency of transistors, and the present invention can achieve this relatively easily.
前述の説明かられかるように本発明は従来法による工程
にエツチング工程を付加するだけであり、場合によって
はホトマスクの変更も必要としない。As can be seen from the above description, the present invention merely adds an etching step to the conventional process, and in some cases does not require changing the photomask.
6−
したがって繁雑な工程を追加することなく、微細パター
ンを形成し得る本発明の効果が大きいことは明らかであ
る。6- Therefore, it is clear that the present invention is highly effective in forming fine patterns without adding complicated steps.
また他の実施例としては、第4・図(C)においてゲー
ト金属を被着形成する前にホトレジスト4・6をマスク
として領域4・5をエツチングしておき、その後ゲート
金属パターンをリフトオフ形成することも可能である。As another example, in FIG. 4(C), before depositing and forming the gate metal, regions 4 and 5 are etched using photoresists 4 and 6 as masks, and then a gate metal pattern is formed by lift-off. It is also possible.
この場合のショットキー障壁電界効果トランジスタの断
面形状は模式的には第5図に示すようなものとなる。シ
ョットキーゲート58直下の活性層厚さa′は電界効果
トランジスタの特性を決める1つのパラメータであるが
、この値はThe cross-sectional shape of the Schottky barrier field effect transistor in this case is schematically shown in FIG. The active layer thickness a' directly under the Schottky gate 58 is one parameter that determines the characteristics of a field effect transistor, and this value is
第1図(、) (b)は従来のリフトオフ法による薄膜
バタン形成法を示す図、第2図(、)と(b)は従来の
エツチング法による薄膜パターン形成法を示す図、第3
図(、)と(b)は従来のパターン形成法における問題
点を示す図、第4図(a)、(b)、(C)及び(d)
は本発明の実施例を示す図、第5図は本発明の実施例の
変形を示す図である。
11.2331.41.51・・・半導体基板12.2
2′、82′、4嘩3.4(6・・・フォトレジストパ
ターン
13’、28′、84・・・第1の薄膜パターン4.2
52・・・活性層
4+4「、54・・・オーミック金属
48.58・・・ゲート金属
(0)、2+
、21
官2図
(O) 〜41
(d)Figure 1 (,) (b) is a diagram showing a thin film pattern forming method using a conventional lift-off method, Figures 2 (,) and (b) are diagrams showing a thin film pattern forming method using a conventional etching method, and Figure 3 is a diagram showing a thin film pattern forming method using a conventional etching method.
Figures (,) and (b) are diagrams showing problems in the conventional pattern forming method, Figure 4 (a), (b), (C) and (d)
5 is a diagram showing an embodiment of the present invention, and FIG. 5 is a diagram showing a modification of the embodiment of the present invention. 11.2331.41.51...Semiconductor substrate 12.2
2', 82', 4 3.4 (6... Photoresist patterns 13', 28', 84... 1st thin film pattern 4.2
52... Active layer 4+4'', 54... Ohmic metal 48.58... Gate metal (0), 2+, 21 Figure 2 (O) ~ 41 (d)
Claims (2)
、前記薄膜パターンの周辺部間の距離が数μm以下であ
る、前記半導体表面における前記第1種薄膜間に狭まれ
た領域に、新たに第2種の薄膜パターンを形成する工程
において、第1種の薄膜パターン形成用ホトレジストパ
ターンをマスクとして該半導体基板表面をエツチングし
た後、エッチングニヨり形成された凹部内に第1種薄膜
パターンを形成し、その後第2種の薄膜パターンを形成
することを特徴とする微細パターン形成法。(1) A first type thin film pattern is formed on the surface of the semiconductor substrate, and the distance between the peripheral parts of the thin film pattern is several μm or less, in a region narrowed between the first type thin films on the semiconductor surface, In the process of newly forming a second type of thin film pattern, the surface of the semiconductor substrate is etched using the photoresist pattern for forming the first type of thin film pattern as a mask, and then the first type of thin film pattern is etched into the recesses formed by the etching. A fine pattern forming method characterized by forming a thin film pattern, and then forming a second type thin film pattern.
2種薄膜がゲート金属であることを特徴とする特許請求
の範囲第1項記載の微細パターン形成法。(2) The method for forming a fine pattern according to claim 1, wherein the first type thin film is an ohmic metal, and the second type thin film is a gate metal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19028983A JPS6081828A (en) | 1983-10-12 | 1983-10-12 | Fine pattern forming process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19028983A JPS6081828A (en) | 1983-10-12 | 1983-10-12 | Fine pattern forming process |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6081828A true JPS6081828A (en) | 1985-05-09 |
Family
ID=16255689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19028983A Pending JPS6081828A (en) | 1983-10-12 | 1983-10-12 | Fine pattern forming process |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6081828A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007236522A (en) * | 2006-03-07 | 2007-09-20 | Takanori Tsuneyama | Liquid container holder and flat-shaped object holder |
-
1983
- 1983-10-12 JP JP19028983A patent/JPS6081828A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007236522A (en) * | 2006-03-07 | 2007-09-20 | Takanori Tsuneyama | Liquid container holder and flat-shaped object holder |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4145459A (en) | Method of making a short gate field effect transistor | |
US5338703A (en) | Method for producing a recessed gate field effect transistor | |
US4902646A (en) | MESFET process employing dummy electrodes and resist reflow | |
JPS6081828A (en) | Fine pattern forming process | |
KR950005489B1 (en) | T-gate making method of mesfet | |
KR100436566B1 (en) | Method for fabricating fet of mmic for improving high-frequency characteristic by reducing length of gate electrode for transistor | |
JP2714026B2 (en) | Method for forming electrode for semiconductor device | |
JPS5937494B2 (en) | Thin film pattern formation method | |
JPH01165126A (en) | Manufacture of semiconductor device | |
JPS5827655B2 (en) | Manufacturing method of aperture diaphragm | |
JPS61240684A (en) | Schottky-type field effect transistor and manufacture thereof | |
JPH03104127A (en) | Formation of fine pattern | |
JPS6390171A (en) | Manufacture of field effect transistor | |
JPS60120574A (en) | Manufacture of field effect transistor | |
JPH04124822A (en) | Manufacture of semiconductor device | |
JPS62299033A (en) | Manufacture of semiconductor device | |
JPH0684950A (en) | Manufacture of field effect transistor | |
JPS61285771A (en) | Manufacture of semiconductor device | |
JPH0366656B2 (en) | ||
JPH065629A (en) | Method for manufacturing semiconductor device | |
JPS61100977A (en) | Pattern forming method | |
EP0613174A2 (en) | Method for making fine-line semiconductor devices | |
JPH01101634A (en) | Pattern formation | |
JPS62131584A (en) | Manufacture of semiconductor device | |
JPS6246577A (en) | Manufacture of semiconductor device |