KR950005489B1 - T-gate making method of mesfet - Google Patents

T-gate making method of mesfet Download PDF

Info

Publication number
KR950005489B1
KR950005489B1 KR1019920015907A KR920015907A KR950005489B1 KR 950005489 B1 KR950005489 B1 KR 950005489B1 KR 1019920015907 A KR1019920015907 A KR 1019920015907A KR 920015907 A KR920015907 A KR 920015907A KR 950005489 B1 KR950005489 B1 KR 950005489B1
Authority
KR
South Korea
Prior art keywords
photoresist
gate
etching
oxide layer
oxide
Prior art date
Application number
KR1019920015907A
Other languages
Korean (ko)
Other versions
KR940008117A (en
Inventor
이원상
Original Assignee
주식회사금성사
이헌조
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사금성사, 이헌조 filed Critical 주식회사금성사
Priority to KR1019920015907A priority Critical patent/KR950005489B1/en
Publication of KR940008117A publication Critical patent/KR940008117A/en
Application granted granted Critical
Publication of KR950005489B1 publication Critical patent/KR950005489B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045—Field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The method is for manufacturing T gate of a MESFET using a single layer photo-resister and an oxide layer. The method comprises the steps of; (A) forming a photo-resister (2) on a GaAs wafer and etching the photo-resister (2); (B) depositing an oxide layer (3) on the oxide layer (3) to form a well shape; (C) etching inside of the well shape and recess-etching exposed GaAs wafer; (D) vaporizing a gate metal (4) inside the well shape and the oxide layer (3) and (E) lifting off the photo-resister (2) and the oxide layer (3).

Description

엠이에스에프이티(MESFET)의 티(T) 게이트 제조방법Method for manufacturing T (T) gate of MESFET

제1도의 (a) 내지 (c)는 종래의 MESFET의 T게이트 제조공정도.(A)-(c) of FIG. 1 is a T-gate manufacturing process diagram of a conventional MESFET.

제2도는 (a) 내지 (e)는 본 발명의 MESFET의 T게이트 제조공정도.2 is a T-gate manufacturing process diagram of the MESFET of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,11 : GaAs웨이퍼 2,12,13,14 : 포토레지스,1,11: GaAs wafer 2,12,13,14: Photoresist,

3 : 산화막 4 : 게이트금속3: oxide film 4: gate metal

본 발명은 MESFET(Metal-Semiconductor Field Effect Transistor)의 T게이트 제조방법에 과한 것으로서, 특히 단층의 포토레지스터와 산화막층을 이용하여 T형 게이트 제조할 수 있도록 하여 생산공정을 단순화시킬 수 있게 한 것에 관한 것이다.The present invention relates to a method for manufacturing a T gate of a metal-semiconductor field effect transistor (MESFET), and more particularly, to simplify the production process by allowing a T-type gate to be manufactured using a single photoresist and an oxide layer. will be.

종래의 MESFET의 T형 게이트 제조공정은 제1도를 참조하여 설명하기로 한다.A conventional T-type gate fabrication process of a MESFET will be described with reference to FIG.

GaAs웨이퍼(11)위에 3층의 포토레지스터(photo-Resister)(12)(13)(14)를 (a)와 같이 증착하고 전자비임 리소그래피(Electron-Beam lithography)에 의해서 조사(Exposure)한 후 3층의 포토레지스터(12)(13)(14)를 수율(Develop rate)로서 식각의 길이를 적당히 설정하여 (b)와 같이 T형 게이트형틀을 제조한다.After three layers of photo-resistors 12, 13, 14 are deposited on GaAs wafer 11 as shown in (a) and exposed by electron-beam lithography. The three-layer photoresist 12, 13, and 14 are suitably set to the length of the etching as a development rate to produce a T-type gate mold as shown in (b).

즉, 제1포토레지스터(12)의 식각실이(t1)가 가장 짧고 제2포토레지스터(13)의 식각길이(t2)가 가장 길게 하며 제3포토레지스터(14)의 식각길이(t3)는 중간정도로 하여서 식각길이 t1＜t3＜t2로 3층의 포토레지스터(12)(13)(14)를 식각하여서 T향 게이트형틀(profile)을 제조한다.That is, the etching chamber t 1 of the first photoresist 12 is shortest, the etching length t 2 of the second photoresist 13 is longest, and the etching length t3 of the third photoresist 14 is long. ) Is made medium and the three-layer photoresist 12, 13, 14 is etched with an etching length t 1 < t 3 < t 2 to produce a T-shaped gate profile.

그리고 상기 T형 게이트형틀에 (c)과 같이 리세트에칭을 한다음 게이트금속(gate metal)을 증착하고 그 후에 리프트오프(Lift-of) 공정을 거쳐서 (d)와 같이 T게이트를 제조한 것이다.After the etching is performed on the T-type gate mold as in (c), the gate metal is deposited, and then, through the lift-of process, the T gate is manufactured as in (d). .

그러나 종래와 같이 T게이트를 제조하는 방법은 고가의 장비인 전자비임 리소그래피로서만 게이트를 제조할 수 있고 3층의 포토레지스터를 사용하여야 함으로써 복제(Reproducibility) 및 공정시간의 장기화로 생산성이 저하되며 정밀(accuracy)등에 문제가 있었다.However, the conventional method of manufacturing a T gate can only manufacture the gate using electron beam lithography, which is an expensive equipment, and requires three-layer photoresist to reduce productivity due to reproducibility and prolongation of processing time. (accuracy) etc. There was a problem.

상기와 같이 종래의 문제점을 해결하고자, 본 발명은 단층의 포토레지스터와 산화막층을 이용하여 T게이트를 제조할 수 있도록 하므로써 생산공정이 단순하므로 생산성을 향상시킬 수 있고 전자비임 리소그래피와 같은 고가의 장비를 사용하지 않아도 되므로 생산원가를 절감할 수 있게 한 것에 목적을 둔 것이다.In order to solve the conventional problems as described above, the present invention is to simplify the production process by allowing the T gate to be manufactured using a single layer photoresist and an oxide film layer to improve productivity and expensive equipment such as electron beam lithography. The purpose is to reduce the production cost because it does not have to use.

상기와 같은 목적을 가진 본 발명은 GaAs웨이퍼(1)위에 형성한 포토레지스터(2)를 하부가 드러나게 함과 아울러 비수직적 형태로 에칭시키는 포토레지스터 에칭공정과, 상기 포토레지스터 위에 산화막 절연층을 디포지션(deposition)하는 산화막 절연층 디포지션공정과, 상기 산화막과 기판의 중앙을 식각시키는 식각공정과, 상기 식각된 기판의 위치와 산화막 위에 금속전극을 증착하는 금속전극증착공정과, 상기 포토레지스터와 산화막층을 리프트오프공정을 통하여 T게이트를 제조함을 특징으로 한다.The present invention having the above object has a photoresist etching process for etching the photoresist (2) formed on the GaAs wafer (1) in a non-vertical form while revealing the lower portion thereof, and deoxidizing an oxide insulating layer on the photoresist. An oxide insulating layer deposition process for positioning, an etching process for etching the center of the oxide film and the substrate, a metal electrode deposition process for depositing a metal electrode on the oxide substrate and the position of the etched substrate, and the photoresist; The oxide film layer is characterized in that the T gate is manufactured through a lift-off process.

이를 첨부도면 제2도에 따라서 상세히 설명하면 다음과 같다.This will be described in detail with reference to FIG. 2 as follows.

GaAs웨이퍼(1)위에 형성된 포토레지스터(2)를 (a)와 같이 하부가 드러나게 함과 함께 비수직적 형태로 에칭시키는 포토레지스터 에칭공정과, 상기 포토레지스터(2)위에 (b)와 같이 산화막층(3)을 PECVD(Plasma Enhanced Chemical Vaper Deposition)법으로 디포지션(deposition)하여 하부(a)는 두께가 얇고 상부(b)는 두께가 두껍게 형성하는 산화막층 디포지션공정과, 상기 산화막층(3)을 에칭하는데 이때 하부(a)는 두께가 얇기 때문에 에칭되고 상부(b)는 두께가 두껍기 때문에 거의 남아있는 상태가 되도록 (c)와 같이 산화막층을 에칭하는 산화막 에칭공정과, 상기 산화막층이 에칭된 GaAs웨이퍼(1)위를 (d)와 같이 리세스에칭하는 리세스에칭공정과, 상기 산화막층과 리세스 에칭된 GaAs웨이퍼(1)위에 (e)와 같이 게이트금속(4)을 증착하여 T자 형태나 버섯형태로 게이트금속증착공정과, 상기 게이트금속(4)을 증착한 후 HF용액에 담궈서 상기 포토레지스터(2)와 산화막층(3)을 리프트오프(Lift-off)시키는 리프트 오프공정으로 T게이트를 제조한 것이다.A photoresist etching process of etching the photoresist 2 formed on the GaAs wafer 1 in a non-vertical form while exposing the lower portion as shown in (a), and an oxide film layer on the photoresist 2 as shown in (b). (3) by depositing the PECVD (Plasma Enhanced Chemical Vaper Deposition) method (deposition) of the oxide film layer deposition process of forming a lower thickness (a) and a thick thickness of the upper (b), and the oxide film layer (3) In this case, the lower portion (a) is etched because of its thin thickness and the upper portion (b) is etched by the oxide layer etching process as in (c) so that the remaining portion is almost left because of its thickness, and the oxide layer is A recess etching process for recess etching the etched GaAs wafer 1 as shown in (d), and a gate metal 4 as shown in (e) is deposited on the oxide layer and the recess etched GaAs wafer 1 as shown in (e). Gate metal deposition process in T-shape or mushroom form , It is manufactured a T gate by a lift-off process to soak the photoresist 2 and the oxide film layer 3, the lift-off (Lift-off) in HF solution after depositing the gate metal (4).

상기와 같이 본 발명의 MESFET의 T게이트제조는 GaAs웨이퍼(1)위에 포토레지스터(2)와 산화막 절연층(3)을 형성하며 에칭한 다음 게이트금속전극을 증착한 후 리세스오프공정으로서 제조하므로서, 종전과 같이 다층(3층)의 포토레지스터형성과 고가의 전자비임리소그래피가 필요하지 않으므로 생산원가절감과 생산공정수를 단축시킬 수 있게 된 것이다.As described above, the T-gate manufacturing of the MESFET of the present invention is performed by forming a photoresist 2 and an oxide insulating layer 3 on the GaAs wafer 1, etching them, depositing a gate metal electrode, and then manufacturing the recess-off process. As a result, the formation of multi-layer (3 layers) photoresist and expensive electron non-lithography are not required, thus reducing the production cost and the number of production processes.

이와 같이 본 발명의 MESFET의 T게이트 제조는 생산공정이 단순하고 고가의 장비를 필요치 않으므로 생산원가절감과 생산성을 향상시킬 수 있게 한 것이다.As described above, the T-gate manufacturing of the MESFET of the present invention can reduce production costs and improve productivity since the production process is simple and does not require expensive equipment.

Claims (3)

GaAs웨이퍼위 포토레지스터(2)에 형성한 후 하부가 드러나게 함과 함께 비수직적 형태로 에칭하는 포토레지스터에칭공정과, 상기 포토레지스터위에 산화막층(3)을 디포지션하여 우물형태의 형틀을 형성하는 산화막 디포지션공정과, 상기 산하막층(3)의 형틀하부만 에칭되도록 하고, 그 하측의 GaAs웨이퍼를 리세스에칭시키는 산화막층과 GaAs웨이퍼에칭공정과, 상기 산화막층(3)과 형틀내부에 게이트금속(4)을 증착시키는 게이트금속 증착공정과, 상기 포토레지스터(2)와 산화막층(3)을 리프트오프시키는 리프트오프공정으로 제조함을 특징으로 하는 MESFET의 T게이트 제조방법.A photoresist etching process for forming a photoresist (2) on the GaAs wafer and then exposing the lower portion and etching it in a non-vertical form, and forming a well-shaped mold by depositing an oxide layer (3) on the photoresist. An oxide layer deposition process, an oxide layer and a GaAs wafer etching process for recess-etching the GaAs wafer on the lower side so that only the lower portion of the underlayer film layer is etched, and a gate inside the oxide layer 3 and the mold A gate metal deposition process for depositing a metal (4) and a lift-off process for lifting off the photoresist (2) and the oxide layer (3). 제1항에 있어서, 산화막 디포지션공정은 PEVCD법으로 형성하되 포토레지스터(2)가 제거된 부분과 포토레지스터(2)가 남아 있는 부분의 산화막 두께를 다르게 형성하여 제조함을 특징으로 하는 MESFET의 T게이트 제조방법.The MESFET according to claim 1, wherein the oxide deposition process is formed by using a PEVCD method, but the oxide film deposition process is performed by differently forming oxide film thicknesses of the portion where the photoresist 2 is removed and the portion where the photoresist 2 remains. T-gate manufacturing method. 제1항에 있어서, 게이트금속 증착공정은, 게이트금속이 T자 형태나 버섯형태로 형성 되도록 제조함을 특징으로 하는 MESFET의 T게이트 제조방법.The method of claim 1, wherein the gate metal deposition process is performed such that the gate metal is formed in a T shape or a mushroom shape.
KR1019920015907A 1992-09-02 1992-09-02 T-gate making method of mesfet KR950005489B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920015907A KR950005489B1 (en) 1992-09-02 1992-09-02 T-gate making method of mesfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920015907A KR950005489B1 (en) 1992-09-02 1992-09-02 T-gate making method of mesfet

Publications (2)

Publication Number Publication Date
KR940008117A KR940008117A (en) 1994-04-28
KR950005489B1 true KR950005489B1 (en) 1995-05-24

Family

ID=19338913

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920015907A KR950005489B1 (en) 1992-09-02 1992-09-02 T-gate making method of mesfet

Country Status (1)

Country Link
KR (1) KR950005489B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7468295B2 (en) 2005-12-07 2008-12-23 Electronics And Telecommunications Research Institute Method of fabricating T-gate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7468295B2 (en) 2005-12-07 2008-12-23 Electronics And Telecommunications Research Institute Method of fabricating T-gate

Also Published As

Publication number Publication date
KR940008117A (en) 1994-04-28

Similar Documents

Publication Publication Date Title
US4045594A (en) Planar insulation of conductive patterns by chemical vapor deposition and sputtering
US5240868A (en) Method of fabrication metal-electrode in semiconductor device
GB1319682A (en) Thin film metallization process for microcircuits
US4145459A (en) Method of making a short gate field effect transistor
US4048712A (en) Processes for manufacturing semiconductor devices
US5322806A (en) Method of producing a semiconductor device using electron cyclotron resonance plasma CVD and substrate biasing
KR950005489B1 (en) T-gate making method of mesfet
US5338703A (en) Method for producing a recessed gate field effect transistor
KR0161917B1 (en) Method of manufacturing semiconductor device
US6686128B1 (en) Method of fabricating patterned layers of material upon a substrate
JPH022175A (en) Manufacture of thin film transistor
KR100259822B1 (en) Method for manufacturing semiconductor device
JPS6081828A (en) Fine pattern forming process
JPH03104127A (en) Formation of fine pattern
KR100266560B1 (en) Fabrication method of thin-film transistor
JPH06168919A (en) Patterning of semiconductor device
KR100323694B1 (en) method for fabricating a T-gate
JPS6390171A (en) Manufacture of field effect transistor
JPH0228333A (en) Manufacture of semiconductor device
KR100270363B1 (en) Method of manufacturing thin-film transistor
JPH07335667A (en) Manufacture of semiconductor device
JPH04291733A (en) Gaas device and forming method for t-shaped gate electorode
JPH04196540A (en) Manufacture of semiconductor device
JPH05335339A (en) Method of forming t-shaped gate electrode
KR930020720A (en) Transistor structure and manufacturing method with narrow gate electrode

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030407

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee