KR940008117A - Method for manufacturing T (T) gate of MESFET - Google Patents
Method for manufacturing T (T) gate of MESFET Download PDFInfo
- Publication number
- KR940008117A KR940008117A KR1019920015907A KR920015907A KR940008117A KR 940008117 A KR940008117 A KR 940008117A KR 1019920015907 A KR1019920015907 A KR 1019920015907A KR 920015907 A KR920015907 A KR 920015907A KR 940008117 A KR940008117 A KR 940008117A
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist
- oxide film
- oxide
- etching
- gate
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims abstract 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 10
- 238000005530 etching Methods 0.000 claims abstract 6
- 238000000151 deposition Methods 0.000 claims abstract 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract 4
- 239000002184 metal Substances 0.000 claims abstract 4
- 238000005137 deposition process Methods 0.000 claims abstract 2
- 238000001465 metallisation Methods 0.000 claims 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000000609 electron-beam lithography Methods 0.000 abstract 1
- 239000002356 single layer Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 단층의 포토레지스터와 산화막층을 이용하여 T게이트를 제조할 수 있도록 함으로서 생산공정이 단순하므로 생산성을 향상시킬 수 있고 전자비임 리소그래피와 같은 고가의 장비를 사용하지 않아도 되므로 생산 원가를 절감할 수 있게 한것에 목적을 두것이다.According to the present invention, the T gate can be manufactured by using a single layer photoresist and an oxide layer, thereby simplifying the production process, thereby improving productivity and reducing production costs since it does not require expensive equipment such as electron beam lithography. The goal is to make it possible.
상기와 같은 목적을 가진 본 발명은 GaAs웨이퍼(1)위에 포토레지스터(2)를 D에칭시키는 포토레지스터 에칭공정과, 상기 포토레지스터위에 산화막 절연층을 디포지션(deposition)하는 산화막 절연층 디포지션공정과, 상기 산화막과 기판의 중앙을 식각시키는 식각공정과, 상기 식각된 기판의 위치와 산화막 위에 금속전극을 증착하는 금속전극증착공정과, 상기 포토레지스터와 산화막층을 리프트오프공정을 통하여 T게이트를 제조함을 특징으로 한다.The present invention having the above object has a photoresist etching process for D-etching the photoresist 2 on a GaAs wafer 1, and an oxide insulation layer deposition process for depositing an oxide insulation layer on the photoresist. And etching the center of the oxide film and the substrate, depositing a metal electrode on the etched substrate, and depositing a metal electrode on the oxide film. It is characterized in that the manufacturing.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도의 (가)내지(마)는 본 발명의 MESFET의 T게이트 제조공정도.(A) to (e) of FIG. 2 are T-gate manufacturing process diagrams of the MESFET of the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920015907A KR950005489B1 (en) | 1992-09-02 | 1992-09-02 | T-gate making method of mesfet |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920015907A KR950005489B1 (en) | 1992-09-02 | 1992-09-02 | T-gate making method of mesfet |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940008117A true KR940008117A (en) | 1994-04-28 |
KR950005489B1 KR950005489B1 (en) | 1995-05-24 |
Family
ID=19338913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920015907A KR950005489B1 (en) | 1992-09-02 | 1992-09-02 | T-gate making method of mesfet |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950005489B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100636597B1 (en) | 2005-12-07 | 2006-10-23 | 한국전자통신연구원 | Fabrication method of t-gate |
-
1992
- 1992-09-02 KR KR1019920015907A patent/KR950005489B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950005489B1 (en) | 1995-05-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR940001443A (en) | Method for manufacturing a field effect transistor having a gate metal electrode having a T-type cross-sectional structure | |
US4145459A (en) | Method of making a short gate field effect transistor | |
US4843024A (en) | Method of producing a Schottky gate field effect transistor | |
US3639186A (en) | Process for the production of finely etched patterns | |
US5185278A (en) | Method of making self-aligned gate providing improved breakdown voltage | |
KR940008117A (en) | Method for manufacturing T (T) gate of MESFET | |
US3526555A (en) | Method of masking a semiconductor with a liftable metallic layer | |
JPS5730376A (en) | Manufacture of schottky barrier fet | |
JPS6424466A (en) | Manufacture of semiconductor device | |
JPS62211957A (en) | Manufacture of field-effect transistor | |
KR950008264B1 (en) | Making method of gaas fet | |
KR100236662B1 (en) | Photoetching method of an ingap layer | |
JPS6453467A (en) | Formation of miniaturized pattern | |
JPS648676A (en) | Manufacture of semiconductor device | |
JPS57130477A (en) | Manufacture of field-effect transistor | |
JP2804499B2 (en) | Manufacturing method of fine pattern | |
KR970008265A (en) | Method for manufacturing 3-pole field emitter coated with metal | |
KR930024106A (en) | Contact Forming Method of Semiconductor Device | |
JPH03259528A (en) | Manufacture of semiconductor device | |
JPS616870A (en) | Manufacture of field-effect transistor | |
JPH03227528A (en) | Manufacture of semiconductor device | |
JPS6081828A (en) | Fine pattern forming process | |
JPH065629A (en) | Method for manufacturing semiconductor device | |
JPS6476776A (en) | Manufacture of semiconductor device | |
KR20000074002A (en) | method for fabricating a T-gate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030407 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |