JPS648676A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS648676A
JPS648676A JP16431087A JP16431087A JPS648676A JP S648676 A JPS648676 A JP S648676A JP 16431087 A JP16431087 A JP 16431087A JP 16431087 A JP16431087 A JP 16431087A JP S648676 A JPS648676 A JP S648676A
Authority
JP
Japan
Prior art keywords
sidewall
pattern
cured
gate electrode
reactive ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16431087A
Other languages
Japanese (ja)
Inventor
Yasutaka Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16431087A priority Critical patent/JPS648676A/en
Publication of JPS648676A publication Critical patent/JPS648676A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To form an extrafine pattern with good reproducibility by curing the sidewall of the resist pattern of a photoresist by reactive ion plasma to form a sidewall thin film cured layer, and forming the extrafine pattern with the cured layer. CONSTITUTION:The sidewall of a resist pattern 3 provided at the position of a gate electrode is cured by a reactive ion plasma of CF4, CF4+O2 or the like to form a sidewall cured thin film layer 4. Then, after source, drain electrodes 6, 5 are formed by a depositing lift-OFF method, the pattern 3 and a photoresist 9 are moved, and a high melting point gate metal 7a which becomes a gate electrode is deposited. Thereafter, with the remaining photoresist 10 by the etching as a mask the metal 7a is etched by reactive ion etching, the layer 4 is further etched by O2 plasma to form a gate electrode 7. Thus, a distance between the electrodes 6 and 7 can be reduced to 0.05mum or shorter.
JP16431087A 1987-06-30 1987-06-30 Manufacture of semiconductor device Pending JPS648676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16431087A JPS648676A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16431087A JPS648676A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS648676A true JPS648676A (en) 1989-01-12

Family

ID=15790703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16431087A Pending JPS648676A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS648676A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681293A (en) * 2012-09-10 2014-03-26 中芯国际集成电路制造(上海)有限公司 Self-alignment duplex patterning method
CN103681234A (en) * 2012-09-10 2014-03-26 中芯国际集成电路制造(上海)有限公司 Method for forming self-alignment duplex pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681293A (en) * 2012-09-10 2014-03-26 中芯国际集成电路制造(上海)有限公司 Self-alignment duplex patterning method
CN103681234A (en) * 2012-09-10 2014-03-26 中芯国际集成电路制造(上海)有限公司 Method for forming self-alignment duplex pattern
CN103681234B (en) * 2012-09-10 2016-03-16 中芯国际集成电路制造(上海)有限公司 The formation method of self-alignment duplex pattern

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