JPS5728352A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Semiconductor integrated circuit and manufacture thereof

Info

Publication number
JPS5728352A
JPS5728352A JP10334080A JP10334080A JPS5728352A JP S5728352 A JPS5728352 A JP S5728352A JP 10334080 A JP10334080 A JP 10334080A JP 10334080 A JP10334080 A JP 10334080A JP S5728352 A JPS5728352 A JP S5728352A
Authority
JP
Japan
Prior art keywords
film
collector
layer
base
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10334080A
Other languages
Japanese (ja)
Inventor
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10334080A priority Critical patent/JPS5728352A/en
Priority to DE19813129755 priority patent/DE3129755C2/en
Publication of JPS5728352A publication Critical patent/JPS5728352A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: To prevent the short circuit between the collector and the base due to making a semiconductor integrated circuit minuter, by a method wherein in an I2L in which a collector having an inverted structrure is formed from doped polycrystalline Si and a base contact is drawn out by self-alignment, an insulating film is left directly beneath the periphery of the polycrystalline Si.
CONSTITUTION: On a substrate provied with an injector 15 and a base layer 16, for example, an Si3N4 film 19 is form, and a collector region is opened, and then a polycrystalline Si layer 18 doped with phosphorus or the like is depointed. Next, the layer 18 is patterned and heattreated in an oxygen atmosphare to form a collector 17 an oxide film 22. With the film 22 used as a mask, Si3N4 is selectively removed by, for example, reactive ion etching, and then the lower SiO2 film 23 is removed. Next, Al wiring 21 is formed in the base and injector regions, but the Si3N4 film 19 is left under the peripheral part of the Si layer 18 to be a collector electrode. Accordingly, when the SiO2 film 23 is etched in self-alignment, side- etching is prevented from occuring, and the short-circuit between electrodes can be hindered even if the circuit is made minuter.
COPYRIGHT: (C)1982,JPO&Japio
JP10334080A 1980-07-28 1980-07-28 Semiconductor integrated circuit and manufacture thereof Pending JPS5728352A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10334080A JPS5728352A (en) 1980-07-28 1980-07-28 Semiconductor integrated circuit and manufacture thereof
DE19813129755 DE3129755C2 (en) 1980-07-28 1981-07-28 Method for manufacturing an I → 2 → L semiconductor circuit arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10334080A JPS5728352A (en) 1980-07-28 1980-07-28 Semiconductor integrated circuit and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5728352A true JPS5728352A (en) 1982-02-16

Family

ID=14351409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10334080A Pending JPS5728352A (en) 1980-07-28 1980-07-28 Semiconductor integrated circuit and manufacture thereof

Country Status (2)

Country Link
JP (1) JPS5728352A (en)
DE (1) DE3129755C2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6294648A (en) * 1985-10-21 1987-05-01 株式会社ノダ Building substrate material and its production
JP2003004198A (en) * 2001-06-20 2003-01-08 Miyawaki Inc Steam trap

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52117579A (en) * 1976-03-30 1977-10-03 Nec Corp Semiconductor device
JPS53142196A (en) * 1977-05-18 1978-12-11 Hitachi Ltd Bipolar type semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2757762C2 (en) * 1977-12-23 1985-03-07 Siemens AG, 1000 Berlin und 8000 München Monolithic combination of two complementary bipolar transistors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52117579A (en) * 1976-03-30 1977-10-03 Nec Corp Semiconductor device
JPS53142196A (en) * 1977-05-18 1978-12-11 Hitachi Ltd Bipolar type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6294648A (en) * 1985-10-21 1987-05-01 株式会社ノダ Building substrate material and its production
JP2003004198A (en) * 2001-06-20 2003-01-08 Miyawaki Inc Steam trap

Also Published As

Publication number Publication date
DE3129755A1 (en) 1982-02-25
DE3129755C2 (en) 1986-03-06

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